default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDKaushik Roy 0001
Person information
- affiliation: Purdue University, West Lafayette, IN, USA
Other persons with the same name
- Kaushik Roy — disambiguation page
- Kaushik Roy 0002 — North Carolina A&T State University, Cyber Defense and AI Lab, Department of Computer Science, Greensboro, NC, USA (and 1 more)
- Kaushik Roy 0003
![[0000-0002-9026-5322]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-9026-5322")
— North Carolina State University, Raleigh, NC, USA - Kaushik Roy 0004 — West Bengal State University, Barasat, India
- Kaushik Roy 0005 — RV College of Engineering, Bangalore, India
- Kaushik Roy 0006 — University of Windsor, Canada
- Kaushik Roy 0007 — Stanford University, Stanford, CA, USA
- Kaushik Roy 0008 — Sungkyunkwan University, MOPIC, R&B Center, Suwon-si, South Korea (and 1 more)
- Kaushik Roy 0009 — University of South Carolina, Department of computer science, AI Institute, Columbia, SC, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j278]Manish Nagaraj, Isha Garg, Kaushik Roy:
TOFU: Toward Obfuscated Federated Updates by Encoding Weight Updates Into Gradients From Proxy Data. IEEE Access 12: 57209-57224 (2024)- [j277]Sayeed Shafayet Chowdhury, Soumyadeep Chandra, Kaushik Roy:
Toward Visual Syntactical Understanding. IEEE Access 12: 64360-64375 (2024) - [j276]Lei Deng, Huajin Tang, Kaushik Roy:
Editorial: Understanding and bridging the gap between neuromorphic computing and machine learning, volume II. Frontiers Comput. Neurosci. 18 (2024) - [j275]Andrea Soltoggio, Eseoghene Ben-Iwhiwhu, Vladimir Braverman, Eric Eaton, Benjamin Epstein, Yunhao Ge, Lucy Halperin, Jonathan P. How, Laurent Itti, Michael A. Jacobs, Pavan Kantharaju, Long Le, Steven Lee, Xinran Liu, Sildomar T. Monteiro, David Musliner, Saptarshi Nath, Priyadarshini Panda, Christos Peridis, Hamed Pirsiavash, Vishwa S. Parekh, Kaushik Roy, Shahaf S. Shperberg, Hava T. Siegelmann, Peter Stone, Kyle Vedder, Jingfeng Wu, Lin Yang, Guangyao Zheng, Soheil Kolouri:
A collective AI via lifelong learning and sharing at the edge. Nat. Mac. Intell. 6(3): 251-264 (2024) - [j274]Guoqi Li, Lei Deng, Huajin Tang, Gang Pan, Yonghong Tian, Kaushik Roy, Wolfgang Maass:
Brain-Inspired Computing: A Systematic Survey and Future Trends. Proc. IEEE 112(6): 544-584 (2024) - [j273]Sourav Sanyal, Rohan Kumar Manna, Kaushik Roy:
EV-Planner: Energy-Efficient Robot Navigation via Event-Based Physics-Guided Neuromorphic Planner. IEEE Robotics Autom. Lett. 9(3): 2080-2087 (2024) - [j272]Amitangshu Mukherjee, Isha Garg, Kaushik Roy:
Encoding Hierarchical Information in Neural Networks Helps in Subpopulation Shift. IEEE Trans. Artif. Intell. 5(2): 827-838 (2024) - [j271]Buddhi Wickramasinghe, Gobinda Saha, Kaushik Roy:
Continual Learning: A Review of Techniques, Challenges, and Future Directions. IEEE Trans. Artif. Intell. 5(6): 2526-2546 (2024) - [j270]Guoqi Li, Emre Neftci, Rong Xiao, Pablo Lanillos, Kaushik Roy:
Guest Editorial: Special Issue on Advancing Machine Intelligence With Neuromorphic Computing. IEEE Trans. Cogn. Dev. Syst. 16(5): 1623-1625 (2024) - [j269]Buddhi Wickramasinghe, Sayeed Shafayet Chowdhury, Adarsh Kumar Kosta, Wachirawit Ponghiran, Kaushik Roy:
Unlocking the Potential of Spiking Neural Networks: Understanding the What, Why, and Where. IEEE Trans. Cogn. Dev. Syst. 16(5): 1648-1663 (2024) - [j268]Timur Ibrayev, Amitangshu Mukherjee, Sai Aparna Aketi, Kaushik Roy:
Toward Two-Stream Foveation-Based Active Vision Learning. IEEE Trans. Cogn. Dev. Syst. 16(5): 1843-1860 (2024) - [j267]Marco Paul E. Apolinario, Adarsh Kumar Kosta, Utkarsh Saxena, Kaushik Roy:
Hardware/Software Co-Design With ADC-Less In-Memory Computing Hardware for Spiking Neural Networks. IEEE Trans. Emerg. Top. Comput. 12(1): 35-47 (2024) - [j266]Sakshi Choudhary, Sai Aparna Aketi, Gobinda Saha, Kaushik Roy:
CoDeC: Communication-Efficient Decentralized Continual Learning. Trans. Mach. Learn. Res. 2024 (2024) - [j265]Sangamesh Kodge, Gobinda Saha, Kaushik Roy:
Deep Unlearning: Fast and Efficient Gradient-free Class Forgetting. Trans. Mach. Learn. Res. 2024 (2024) - [j264]Deepak Ravikumar, Gobinda Saha, Sai Aparna Aketi, Kaushik Roy:
Homogenizing Non-IID Datasets via In-Distribution Knowledge Distillation for Decentralized Learning. Trans. Mach. Learn. Res. 2024 (2024) - [j263]Efstathia Soufleri, Deepak Ravikumar, Kaushik Roy:
DP-ImgSyn: Dataset Alignment for Obfuscated, Differentially Private Image Synthesis. Trans. Mach. Learn. Res. 2024 (2024) - [c516]Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan:
Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms. DAC 2024: 336:1-336:6 - [c515]Sayeed Shafayet Chowdhury, Adarsh Kumar Kosta, Deepika Sharma, Marco Paul E. Apolinario, Kaushik Roy:
Unearthing the Potential of Spiking Neural Networks. DATE 2024: 1-6 - [c514]Kang He, Yinghan Long, Kaushik Roy:
Prompt-Based Bias Calibration for Better Zero/Few-Shot Learning of Language Models. EMNLP (Findings) 2024: 12673-12691 - [c513]Utkarsh Saxena, Gobinda Saha, Sakshi Choudhary, Kaushik Roy:
Eigen Attention: Attention in Low-Rank Space for KV Cache Compression. EMNLP (Findings) 2024: 15332-15344 - [c512]Sai Aparna Aketi, Sakshi Choudhary, Kaushik Roy:
Averaging Rate Scheduler for Decentralized Learning on Heterogeneous Data. Tiny Papers @ ICLR 2024 - [c511]Isha Garg, Deepak Ravikumar, Kaushik Roy:
Memorization Through the Lens of Curvature of Loss Function Around Samples. ICML 2024 - [c510]Deepak Ravikumar, Efstathia Soufleri, Abolfazl Hashemi, Kaushik Roy:
Unveiling Privacy, Memorization, and Input Curvature Links. ICML 2024 - [c509]Nirmoy Modak, Kaushik Roy:
Energy Efficiency Through In-Sensor Computing: ADC-less Real-Time Sensing for Image Edge Detection. ISLPED 2024: 1-6 - [c508]Sai Aparna Aketi, Kaushik Roy:
Cross-feature Contrastive Loss for Decentralized Deep Learning on Heterogeneous Data. WACV 2024: 12-21 - [c507]Shristi Das Biswas, Adarsh Kosta, Chamika M. Liyanagedera, Marco Paul E. Apolinario, Kaushik Roy:
HALSIE: Hybrid Approach to Learning Segmentation by Simultaneously Exploiting Image and Event Modalities. WACV 2024: 5952-5962 - [i170]Sayeed Shafayet Chowdhury, Soumyadeep Chandra, Kaushik Roy:
Towards Visual Syntactical Understanding. CoRR abs/2401.17497 (2024) - [i169]Chun Tao, Timur Ibrayev, Kaushik Roy:
Towards Image Semantics and Syntax Sequence Learning. CoRR abs/2401.17515 (2024) - [i168]Kang He, Yinghan Long, Kaushik Roy:
Prompt-Based Bias Calibration for Better Zero/Few-Shot Learning of Language Models. CoRR abs/2402.10353 (2024) - [i167]Deepak Ravikumar, Efstathia Soufleri, Abolfazl Hashemi, Kaushik Roy:
Unveiling Privacy, Memorization, and Input Curvature Links. CoRR abs/2402.18726 (2024) - [i166]Sai Aparna Aketi, Sakshi Choudhary, Kaushik Roy:
Averaging Rate Scheduler for Decentralized Learning on Heterogeneous Data. CoRR abs/2403.03292 (2024) - [i165]Sangamesh Kodge, Deepak Ravikumar, Gobinda Saha, Kaushik Roy:
Verifix: Post-Training Correction to Improve Label Noise Robustness with Verified Samples. CoRR abs/2403.08618 (2024) - [i164]Timur Ibrayev, Isha Garg, Indranil Chakraborty, Kaushik Roy:
Pruning for Improved ADC Efficiency in Crossbar-based Analog In-memory Accelerators. CoRR abs/2403.13082 (2024) - [i163]Shubham Negi, Utkarsh Saxena, Deepika Sharma, Kaushik Roy:
HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads. CoRR abs/2403.13577 (2024) - [i162]Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan:
Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms. CoRR abs/2403.15717 (2024) - [i161]Timur Ibrayev, Amitangshu Mukherjee, Sai Aparna Aketi, Kaushik Roy:
Towards Two-Stream Foveation-based Active Vision Learning. CoRR abs/2403.15977 (2024) - [i160]Amitangshu Mukherjee, Timur Ibrayev, Kaushik Roy:
On Inherent Adversarial Robustness of Active Vision Systems. CoRR abs/2404.00185 (2024) - [i159]Sai Aparna Aketi, Abolfazl Hashemi, Kaushik Roy:
AdaGossip: Adaptive Consensus Step-size for Decentralized Deep Learning with Communication Compression. CoRR abs/2404.05919 (2024) - [i158]Soumyadeep Chandra, Sayeed Shafayet Chowdhury, Courtney Yong, Chandru P. Sundaram, Kaushik Roy:
ViTALS: Vision Transformer for Action Localization in Surgical Nephrectomy. CoRR abs/2405.02571 (2024) - [i157]Sakshi Choudhary, Sai Aparna Aketi, Kaushik Roy:
SADDLe: Sharpness-Aware Decentralized Deep Learning with Heterogeneous Data. CoRR abs/2405.13961 (2024) - [i156]Marco Paul E. Apolinario, Arani Roy, Kaushik Roy:
LLS: Local Learning Rule for Deep Neural Networks Inspired by Neural Activity Synchronization. CoRR abs/2405.15868 (2024) - [i155]Jeffry Victor, Dong Eun Kim, Chunguang Wang, Kaushik Roy, Sumeet Gupta:
SWANN: Shuffling Weights in Crossbar Arrays for Enhanced DNN Accuracy in Deeply Scaled Technologies. CoRR abs/2406.14706 (2024) - [i154]Amogh Joshi, Sourav Sanyal, Kaushik Roy:
Real-Time Neuromorphic Navigation: Integrating Event-Based Vision and Physics-Driven Planning on a Parrot Bebop2 Quadrotor. CoRR abs/2407.00931 (2024) - [i153]Adnan Mehonic, Daniele Ielmini, Kaushik Roy, Onur Mutlu, Shahar Kvatinsky, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Sabina Spiga, Sergey Savelev, Alexander G. Balanov, Nitin Chawla, Giuseppe Desoli, Gerardo Malavena, Christian Monzio Compagnoni, Zhongrui Wang, J. Joshua Yang, Syed Ghazi Sarwat, Abu Sebastian, Thomas Mikolajick, Beatriz Noheda, Stefan Slesazeck, Bernard Dieny, Tuo-Hung Hou, Akhil Varri, Frank Brückerhoff-Plückelmann, Wolfram H. P. Pernice, Xixiang Zhang, Sebastian Pazos, Mario Lanza, Stefan Wiefels, Regina Dittmann, Wing H. Ng, Mark Buckwell, Horatio Cox, Daniel J. Mannion, Anthony J. Kenyon, Yingming Lu, Yuchao Yang, Damien Querlioz, Louis Hutin, Elisa Vianello, Sayeed Shafayet Chowdhury, Piergiulio Mannocci, Yimao Cai, Zhong Sun, Giacomo Pedretti, John Paul Strachan, Dmitri B. Strukov, Manuel Le Gallo, Stefano Ambrogio, Ilia Valov, Rainer Waser:
Roadmap to Neuromorphic Computing with Emerging Technologies. CoRR abs/2407.02353 (2024) - [i152]Efstathia Soufleri, Deepak Ravikumar, Kaushik Roy:
Advancing Compressed Video Action Recognition through Progressive Knowledge Distillation. CoRR abs/2407.02713 (2024) - [i151]Deepak Ravikumar, Efstathia Soufleri, Kaushik Roy:
Curvature Clues: Decoding Deep Learning Privacy with Input Loss Curvature. CoRR abs/2407.02747 (2024) - [i150]Utkarsh Saxena, Gobinda Saha, Sakshi Choudhary, Kaushik Roy:
Eigen Attention: Attention in Low-Rank Space for KV Cache Compression. CoRR abs/2408.05646 (2024) - [i149]Arkapravo Ghosh, Hemkar Reddy Sadana, Mukut Debnath, Panthadip Maji, Shubham Negi, Sumeet Gupta, Mrigank Sharad, Kaushik Roy:
Approximate ADCs for In-Memory Computing. CoRR abs/2408.06390 (2024) - [i148]Arjun Roy, Kaushik Roy:
DCT-CryptoNets: Scaling Private Inference in the Frequency Domain. CoRR abs/2408.15231 (2024) - [i147]Amogh Joshi, Adarsh Kumar Kosta, Kaushik Roy:
SHIRE: Enhancing Sample Efficiency using Human Intuition in REinforcement Learning. CoRR abs/2409.09990 (2024) - [i146]Sourav Sanyal, Kaushik Roy:
ASMA: An Adaptive Safety Margin Algorithm for Vision-Language Drone Navigation via Scene-Aware Control Barrier Functions. CoRR abs/2409.10283 (2024) - [i145]Jimmy Gammell, Anand Raghunathan, Kaushik Roy:
Power side-channel leakage localization through adversarial training of deep neural networks. CoRR abs/2410.22425 (2024) - 2023
- [j262]Deepak Ravikumar, Sangamesh Kodge, Isha Garg, Kaushik Roy:
Intra-Class Mixup for Out-of-Distribution Detection. IEEE Access 11: 25968-25981 (2023) - [j261]Nitin Rathi, Indranil Chakraborty, Adarsh Kosta, Abhronil Sengupta, Aayush Ankit, Priyadarshini Panda, Kaushik Roy:
Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware. ACM Comput. Surv. 55(12): 243:1-243:49 (2023) - [j260]Gobinda Saha, Kaushik Roy:
Online continual learning with saliency-guided experience replay using tiny episodic memory. Mach. Vis. Appl. 34(4): 65 (2023) - [j259]Deepak Ravikumar, Sangamesh Kodge, Isha Garg, Kaushik Roy:
TREND: Transferability-Based Robust ENsemble Design. IEEE Trans. Artif. Intell. 4(3): 534-548 (2023) - [j258]Dong Eun Kim, Aayush Ankit, Cheng Wang, Kaushik Roy:
SAMBA: Sparsity Aware In-Memory Computing Based Machine Learning Accelerator. IEEE Trans. Computers 72(9): 2615-2627 (2023) - [j257]Sai Aparna Aketi, Sangamesh Kodge, Kaushik Roy:
Neighborhood Gradient Mean: An Efficient Decentralized Learning Method for Non-IID Data. Trans. Mach. Learn. Res. 2023 (2023) - [j256]Nitin Rathi, Kaushik Roy:
DIET-SNN: A Low-Latency Spiking Neural Network With Direct Input Encoding and Leakage and Threshold Optimization. IEEE Trans. Neural Networks Learn. Syst. 34(6): 3174-3182 (2023) - [j255]Shrihari Sridharan, Jacob R. Stevens, Kaushik Roy, Anand Raghunathan:
X-Former: In-Memory Acceleration of Transformers. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1223-1233 (2023) - [c506]Gobinda Saha, Kaushik Roy:
Continual Learning with Scaled Gradient Projection. AAAI 2023: 9677-9685 - [c505]Utkarsh Saxena, Kaushik Roy:
McQueen: Mixed Precision Quantization of Early Exit Networks. BMVC 2023: 511-513 - [c504]Mustafa Fayez Ali, Indranil Chakraborty, Sakshi Choudhary, Muya Chang, Dong Eun Kim, Arijit Raychowdhury, Kaushik Roy:
A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads. CICC 2023: 1-2 - [c503]Arjun Roy, Manish Nagaraj, Chamika Mihiranga Liyanagedera, Kaushik Roy:
Live Demonstration: Real-time Event-based Speed Detection using Spiking Neural Networks. CVPR Workshops 2023: 4081-4082 - [c502]Adarsh Kumar Kosta, Marco Paul E. Apolinario, Kaushik Roy:
Live Demonstration: ANN vs SNN vs Hybrid Architectures for Event-based Real-time Gesture Recognition and Optical Flow Estimation. CVPR Workshops 2023: 4148-4149 - [c501]Isha Garg, Kaushik Roy:
Samples with Low Loss Curvature Improve Data Efficiency. CVPR 2023: 20290-20300 - [c500]Deepika Sharma, Adarsh Kumar Kosta, Kaushik Roy:
Lightning Talk: A Perspective on Neuromorphic Computing. DAC 2023: 1-2 - [c499]Yinghan Long, Sayeed Shafayet Chowdhury, Kaushik Roy:
Segmented Recurrent Transformer: An Efficient Sequence-to-Sequence Model. EMNLP (Findings) 2023: 8325-8337 - [c498]Timur Ibrayev, Manish Nagaraj, Amitangshu Mukherjee, Kaushik Roy:
Exploring Foveation and Saccade for Improved Weakly-Supervised Localization. Gaze Meets ML 2023: 61-89 - [c497]Wachirawit Ponghiran, Chamika Mihiranga Liyanagedera, Kaushik Roy:
Event-based Temporally Dense Optical Flow Estimation with Sequential Learning. ICCV 2023: 9793-9802 - [c496]Sourav Sanyal, Kaushik Roy:
RAMP-Net: A Robust Adaptive MPC for Quadrotors via Physics-informed Neural Network. ICRA 2023: 1019-1025 - [c495]Manish Nagaraj, Chamika Mihiranga Liyanagedera, Kaushik Roy:
DOTIE - Detecting Objects through Temporal Isolation of Events using a Spiking Architecture. ICRA 2023: 4858-4864 - [c494]Adarsh Kumar Kosta, Kaushik Roy:
Adaptive-SpikeNet: Event-based Optical Flow Estimation using Spiking Neural Networks with Learnable Neuronal Dynamics. ICRA 2023: 6021-6027 - [c493]Chamika Mihiranga Liyanagedera, Manish Nagaraj, Wachirawit Ponghiran, Kaushik Roy:
Low-Power Real-Time Sequential Processing with Spiking Neural Networks. ISCAS 2023: 1-5 - [c492]Utkarsh Saxena, Kaushik Roy:
Partial-Sum Quantization for Near ADC-Less Compute-In-Memory Accelerators. ISLPED 2023: 1-6 - [c491]Sai Aparna Aketi, Abolfazl Hashemi, Kaushik Roy:
Global Update Tracking: A Decentralized Learning Algorithm for Heterogeneous Data. NeurIPS 2023 - [c490]Gobinda Saha, Kaushik Roy:
Saliency Guided Experience Packing for Replay in Continual Learning. WACV 2023: 5262-5272 - [i144]Giovanni Finocchio, Supriyo Bandyopadhyay, Peng Lin, Gang Pan, J. Joshua Yang, Riccardo Tomasello, Christos Panagopoulos, Mario Carpentieri, Vito Puliafito, Johan Åkerman, Hiroki Takesue, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Kaushik Roy, Vinod K. Sangwan, Mark C. Hersam, Anna Giordano, Huynsoo Yang, Julie Grollier, Kerem Yunus Çamsari, Peter L. McMahon, Supriyo Datta, Jean Anne C. Incorvia, Joseph S. Friedman, Sorin Cotofana, Florin Ciubotaru, Andrii V. Chumak, Azad J. Naeemi, Brajesh Kumar Kaushik, Yao Zhu, Kang Wang, Belita Koiller, Gabriel Aguilar, Guilherme P. Temporão, Kremena Makasheva, Aida Todri-Sanial, Jennifer Hasler, William Levy, Vwani Roychowdhury, Samiran Ganguly, Avik W. Ghosh, Davi Rodriquez, Satoshi Sunada, Karin Everschor-Sitte, Amit Lal, Shubham Jadhav, Massimiliano Di Ventra, Yuriy V. Pershin, Kosuke Tatsumura, Hayato Goto:
Roadmap for Unconventional Computing with Nanotechnology. CoRR abs/2301.06727 (2023) - [i143]Gobinda Saha, Kaushik Roy:
Continual Learning with Scaled Gradient Projection. CoRR abs/2302.01386 (2023) - [i142]Shrihari Sridharan, Jacob R. Stevens, Kaushik Roy, Anand Raghunathan:
X-Former: In-Memory Acceleration of Transformers. CoRR abs/2303.07470 (2023) - [i141]Sakshi Choudhary, Sai Aparna Aketi, Gobinda Saha, Kaushik Roy:
CoDeC: Communication-Efficient Decentralized Continual Learning. CoRR abs/2303.15378 (2023) - [i140]Deepak Ravikumar, Gobinda Saha, Sai Aparna Aketi, Kaushik Roy:
Homogenizing Non-IID datasets via In-Distribution Knowledge Distillation for Decentralized Learning. CoRR abs/2304.04326 (2023) - [i139]Sai Aparna Aketi, Abolfazl Hashemi, Kaushik Roy:
Global Update Tracking: A Decentralized Learning Algorithm for Heterogeneous Data. CoRR abs/2305.04792 (2023) - [i138]Amogh Joshi, Adarsh Kosta, Wachirawit Ponghiran, Manish Nagaraj, Kaushik Roy:
FEDORA: Flying Event Dataset fOr Reactive behAvior. CoRR abs/2305.14392 (2023) - [i137]Yinghan Long, Sayeed Shafayet Chowdhury, Kaushik Roy:
Segmented Recurrent Transformer: An Efficient Sequence-to-Sequence Model. CoRR abs/2305.16340 (2023) - [i136]Shubham Negi, Deepika Sharma, Adarsh Kumar Kosta, Kaushik Roy:
Best of Both Worlds: Hybrid SNN-ANN Architecture for Event-based Optical Flow Estimation. CoRR abs/2306.02960 (2023) - [i135]Marco Paul E. Apolinario, Kaushik Roy:
S-TLLR: STDP-inspired Temporal Local Learning Rule for Spiking Neural Networks. CoRR abs/2306.15220 (2023) - [i134]Isha Garg, Kaushik Roy:
Memorization Through the Lens of Curvature of Loss Function Around Samples. CoRR abs/2307.05831 (2023) - [i133]Sourav Sanyal, Rohan Kumar Manna, Kaushik Roy:
EV-Planner: Energy-Efficient Robot Navigation via Event-Based Physics-Guided Neuromorphic Planner. CoRR abs/2307.11349 (2023) - [i132]Sai Aparna Aketi, Kaushik Roy:
Cross-feature Contrastive Loss for Decentralized Deep Learning on Heterogeneous Data. CoRR abs/2310.15890 (2023) - [i131]Sangamesh Kodge, Gobinda Saha, Kaushik Roy:
Deep Unlearning: Fast and Efficient Training-free Approach to Controlled Forgetting. CoRR abs/2312.00761 (2023) - [i130]Tanvi Sharma, Mustafa Fayez Ali, Indranil Chakraborty, Kaushik Roy:
WWW: What, When, Where to Compute-in-Memory. CoRR abs/2312.15896 (2023) - 2022
- [j254]Sandip Mondal, Zhen Zhang, A. N. M. Nafiul Islam, Robert Andrawis, Sampath Gamage, Neda Alsadat Aghamiri, Qi Wang, Hua Zhou, Fanny Rodolakis, Richard Tran, Jasleen Kaur, Chi Chen, Shyue Ping Ong, Abhronil Sengupta, Yohannes Abate, Kaushik Roy, Shriram Ramanathan:
All-Electric Nonassociative Learning in Nickel Oxide. Adv. Intell. Syst. 4(10) (2022) - [j253]Sai Aparna Aketi, Sangamesh Kodge, Kaushik Roy:
Low precision decentralized distributed training over IID and non-IID data. Neural Networks 155: 451-460 (2022) - [j252]Sourav Sanyal, Kaushik Roy:
Neuro-Ising: Accelerating Large-Scale Traveling Salesman Problems via Graph Neural Network Guided Localized Ising Solvers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5408-5420 (2022) - [j251]Chun Tao, Deboleena Roy, Indranil Chakraborty, Kaushik Roy:
On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1448-1460 (2022) - [j250]Mustafa Fayez Ali, Sourjya Roy, Utkarsh Saxena, Tanvi Sharma, Anand Raghunathan, Kaushik Roy:
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1615-1630 (2022) - [c489]Bing Han, Cheng Wang, Kaushik Roy:
Oscillatory Fourier Neural Network: A Compact and Efficient Architecture for Sequential Processing. AAAI 2022: 6838-6846 - [c488]Wachirawit Ponghiran, Kaushik Roy:
Spiking Neural Networks with Improved Inherent Recurrence Dynamics for Sequential Learning. AAAI 2022: 8001-8008 - [c487]Sarada Krithivasan, Sanchari Sen, Nitin Rathi, Kaushik Roy, Anand Raghunathan:
Efficiency attacks on spiking neural networks. DAC 2022: 373-378 - [c486]Shubham Negi, Indranil Chakraborty, Aayush Ankit, Kaushik Roy:
NAX: neural architecture and memristive xbar based accelerator co-design. DAC 2022: 451-456 - [c485]Gobinda Saha, Cheng Wang, Anand Raghunathan, Kaushik Roy:
A cross-layer approach to cognitive computing: invited. DAC 2022: 1327-1330 - [c484]Adarsh Kosta, Efstathia Soufleri, Indranil Chakraborty, Amogh Agrawal, Aayush Ankit, Kaushik Roy:
HyperX: A Hybrid RRAM-SRAM partitioned system for error recovery in memristive Xbars. DATE 2022: 88-91 - [c483]Utkarsh Saxena, Indranil Chakraborty, Kaushik Roy:
Towards ADC-Less Compute-In-Memory Accelerators for Energy Efficient Deep Learning. DATE 2022: 624-627 - [c482]Sayeed Shafayet Chowdhury, Nitin Rathi, Kaushik Roy:
Towards Ultra Low Latency Spiking Neural Networks for Vision and Sequential Tasks Using Temporal Pruning. ECCV (11) 2022: 709-726 - [c481]Kaushik Roy:
In-Memory Computing based Machine Learning Accelerators: Opportunities and Challenges. ACM Great Lakes Symposium on VLSI 2022: 203-204 - [c480]Kang He, Indranil Chakraborty, Cheng Wang, Kaushik Roy:
Design Space and Memory Technology Co-Exploration for In-Memory Computing Based Machine Learning Accelerators. ICCAD 2022: 91:1-91:9 - [c479]Chankyu Lee, Adarsh Kumar Kosta, Kaushik Roy:
Fusion-FlowNet: Energy-Efficient Optical Flow Estimation using Sensor Fusion and Deep Fused Spiking-Analog Network Architectures. ICRA 2022: 6504-6510 - [c478]Adarsh Kumar Kosta, Malik Aqeel Anwar, Priyadarshini Panda, Arijit Raychowdhury, Kaushik Roy:
RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning. ICRA 2022: 7492-7498 - [c477]Deepika Sharma, Aayush Ankit, Kaushik Roy:
Identifying Efficient Dataflows for Spiking Neural Networks. ISLPED 2022: 2:1-2:6 - [p4]Sourav Sanyal, Shubham Negi, Anand Raghunathan, Kaushik Roy:
Approximate Computing for Machine Learning Workloads: A Circuits and Systems Perspective. Approximate Computing 2022: 365-395 - [i129]Isha Garg, Manish Nagaraj, Kaushik Roy:
TOFU: Towards Obfuscated Federated Updates by Encoding Weight Updates into Gradients from Proxy Data. CoRR abs/2201.08494 (2022) - [i128]Md. Mazharul Islam, Shamiul Alam, Md. Shafayat Hossain, Kaushik Roy, Ahmedullah Aziz:
Cryogenic Neuromorphic Hardware. CoRR abs/2204.07503 (2022) - [i127]Deepak Ravikumar, Kaushik Roy:
Norm-Scaling for Out-of-Distribution Detection. CoRR abs/2205.03493 (2022) - [i126]Wilfried Haensch, Anand Raghunathan, Kaushik Roy, Bhaswar Chakrabarti, Charudatta M. Phatak, Cheng Wang, Supratik Guha:
A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks. CoRR abs/2206.08735 (2022) - [i125]Sourav Sanyal, Kaushik Roy:
RAMP-Net: A Robust Adaptive MPC for Quadrotors via Physics-informed Neural Network. CoRR abs/2209.09025 (2022) - [i124]Adarsh Kumar Kosta, Kaushik Roy:
Adaptive-SpikeNet: Event-based Optical Flow Estimation using Spiking Neural Networks with Learnable Neuronal Dynamics. CoRR abs/2209.11741 (2022) - [i123]Sai Aparna Aketi, Sangamesh Kodge, Kaushik Roy:
Neighborhood Gradient Clustering: An Efficient Decentralized Learning Method for Non-IID Data Distributions. CoRR abs/2209.14390 (2022) - [i122]Manish Nagaraj, Chamika Mihiranga Liyanagedera, Kaushik Roy:
DOTIE - Detecting Objects through Temporal Isolation of Events using a Spiking Architecture. CoRR abs/2210.00975 (2022) - [i121]Wachirawit Ponghiran, Chamika Mihiranga Liyanagedera, Kaushik Roy:
Event-based Temporally Dense Optical Flow Estimation with Sequential Neural Networks. CoRR abs/2210.01244 (2022) - [i120]Marco Paul E. Apolinario, Adarsh Kumar Kosta, Utkarsh Saxena, Kaushik Roy:
Hardware/Software co-design with ADC-Less In-memory Computing Hardware for Spiking Neural Networks. CoRR abs/2211.02167 (2022) - [i119]Shristi Das Biswas, Adarsh Kosta, Chamika M. Liyanagedera, Marco Paul E. Apolinario, Kaushik Roy:
HALSIE - Hybrid Approach to Learning Segmentation by Simultaneously Exploiting Image and Event Modalities. CoRR abs/2211.10754 (2022) - 2021
- [j249]Efstathia Soufleri, Kaushik Roy:
Network Compression via Mixed Precision Quantization Using a Multi-Layer Perceptron for the Bit-Width Allocation. IEEE Access 9: 135059-135068 (2021) - [j248]Gobinda Saha, Isha Garg, Aayush Ankit, Kaushik Roy:
SPACE: Structured Compression and Sharing of Representational Space for Continual Learning. IEEE Access 9: 150480-150494 (2021) - [j247]Amogh Agrawal, Deboleena Roy, Utkarsh Saxena, Kaushik Roy:
Embracing Stochasticity to Enable Neuromorphic Computing at the Edge. IEEE Des. Test 38(6): 28-35 (2021) - [j246]Aditi Anand, Sanchari Sen, Kaushik Roy:
Quantifying the Brain Predictivity of Artificial Neural Networks With Nonlinear Response Mapping. Frontiers Comput. Neurosci. 15: 609721 (2021) - [j245]Lei Deng, Huajin Tang, Kaushik Roy:
Editorial: Understanding and Bridging the Gap Between Neuromorphic Computing and Machine Learning. Frontiers Comput. Neurosci. 15: 665662 (2021) - [j244]Sayeed Shafayet Chowdhury, Chankyu Lee, Kaushik Roy:
Towards understanding the effect of leak in Spiking Neural Networks. Neurocomputing 464: 83-94 (2021) - [j243]Priyadarshini Panda, Kaushik Roy:
Implicit adversarial data augmentation and robustness with Noise-based Learning. Neural Networks 141: 120-132 (2021) - [j242]Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan:
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(2): 326-338 (2021) - [j241]Amogh Agrawal, Cheng Wang, Tanvi Sharma, Kaushik Roy:
Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6): 2281-2294 (2021) - [j240]Nitin Rathi, Kaushik Roy:
STDP Based Unsupervised Multimodal Learning With Cross-Modal Processing in Spiking Neural Networks. IEEE Trans. Emerg. Top. Comput. Intell. 5(1): 143-153 (2021) - [c476]Sitao Huang, Aayush Ankit, Plínio Silveira, Rodrigo Antunes, Sai Rahul Chalamalasetti, Izzat El Hajj, Dong Eun Kim, Glaucimar Aguiar, Pedro Bruel, Sergey Serebryakov, Cong Xu, Can Li, Paolo Faraboschi, John Paul Strachan, Deming Chen, Kaushik Roy, Wen-Mei W. Hwu, Dejan S. Milojicic:
Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators. ASP-DAC 2021: 372-377 - [c475]Deboleena Roy, Indranil Chakraborty, Timur Ibrayev, Kaushik Roy:
On the Intrinsic Robustness of NVM Crossbars Against Adversarial Attacks. DAC 2021: 565-570 - [c474]Wachirawit Ponghiran, Kaushik Roy:
Hybrid Analog-Spiking Long Short-Term Memory for Energy Efficient Computing on Edge Devices. DATE 2021: 581-586 - [c473]Nitin Rathi, Amogh Agrawal, Chankyu Lee, Adarsh Kumar Kosta, Kaushik Roy:
Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives. DATE 2021: 902-907 - [c472]Hussam Amrouch, Jian-Jia Chen, Kaushik Roy, Yuan Xie, Indranil Chakraborty, Wenqin Huangfu, Ling Liang, Fengbin Tu, Cheng Wang, Mikail Yayla:
Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper. ICCAD 2021: 1-9 - [c471]Isha Garg, Sayeed Shafayet Chowdhury, Kaushik Roy:
DCT-SNN: Using DCT to Distribute Spatial Information over Time for Low-Latency Spiking Neural Networks. ICCV 2021: 4651-4660 - [c470]Yinghan Long, Indranil Chakraborty, Gopalakrishnan Srinivasan, Kaushik Roy:
Complexity-aware Adaptive Training and Inference for Edge-Cloud Distributed AI Systems. ICDCS 2021: 573-583 - [c469]Gobinda Saha, Isha Garg, Kaushik Roy:
Gradient Projection Memory for Continual Learning. ICLR 2021 - [c468]Maryam Parsa, Catherine D. Schuman, Nitin Rathi, Amirkoushyar Ziabari, Derek C. Rose, J. Parker Mitchell, J. Travis Johnston, Bill Kay, Steven R. Young, Kaushik Roy:
Accurate and Accelerated Neuromorphic Network Design Leveraging A Bayesian Hyperparameter Pareto Optimization Approach. ICONS 2021: 14:1-14:8 - [c467]Sayeed Shafayet Chowdhury, Isha Garg, Kaushik Roy:
Spatio-Temporal Pruning and Quantization for Low-latency Spiking Neural Networks. IJCNN 2021: 1-9 - [c466]Kenneth Chaney, Artemis Panagopoulou, Chankyu Lee, Kaushik Roy, Kostas Daniilidis:
Self-Supervised Optical Flow with Spiking Neural Networks and Event Based Cameras. IROS 2021: 5892-5899 - [c465]Tanvi Sharma, Cheng Wang, Amogh Agrawal, Kaushik Roy:
Enabling Robust SOT-MTJ Crossbars for Machine Learning using Sparsity-Aware Device-Circuit Co-design. ISLPED 2021: 1-6 - [i118]Gobinda Saha, Isha Garg, Kaushik Roy:
Gradient Projection Memory for Continual Learning. CoRR abs/2103.09762 (2021) - [i117]Chankyu Lee, Adarsh Kumar Kosta, Kaushik Roy:
Fusion-FlowNet: Energy-Efficient Optical Flow Estimation using Sensor Fusion and Deep Fused Spiking-Analog Network Architectures. CoRR abs/2103.10592 (2021) - [i116]Sayeed Shafayet Chowdhury, Isha Garg, Kaushik Roy:
Spatio-Temporal Pruning and Quantization for Low-latency Spiking Neural Networks. CoRR abs/2104.12528 (2021) - [i115]Amogh Agrawal, Mustafa Fayez Ali, Minsuk Koo, Nitin Rathi, Akhilesh Jaiswal, Kaushik Roy:
IMPULSE: A 65nm Digital Compute-in-Memory Macro with Fused Weights and Membrane Potential for Spike-based Sequential Learning Tasks. CoRR abs/2105.08217 (2021) - [i114]Shubham Negi, Indranil Chakraborty, Aayush Ankit, Kaushik Roy:
NAX: Co-Designing Neural Network and Hardware Architecture for Memristive Xbar based Computing Systems. CoRR abs/2106.12125 (2021) - [i113]Wachirawit Ponghiran, Kaushik Roy:
Spiking Neural Networks with Improved Inherent Recurrence Dynamics for Sequential Learning. CoRR abs/2109.01905 (2021) - [i112]Gobinda Saha, Kaushik Roy:
Saliency Guided Experience Packing for Replay in Continual Learning. CoRR abs/2109.04954 (2021) - [i111]Yinghan Long, Indranil Chakraborty, Gopalakrishnan Srinivasan, Kaushik Roy:
Complexity-aware Adaptive Training and Inference for Edge-Cloud Distributed AI Systems. CoRR abs/2109.06440 (2021) - [i110]Adarsh Kumar Kosta, Malik Aqeel Anwar, Priyadarshini Panda, Arijit Raychowdhury, Kaushik Roy:
RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning. CoRR abs/2109.08231 (2021) - [i109]Deboleena Roy, Chun Tao, Indranil Chakraborty, Kaushik Roy:
On the Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars. CoRR abs/2109.09060 (2021) - [i108]Bing Han, Cheng Wang, Kaushik Roy:
Oscillatory Fourier Neural Network: A Compact and Efficient Architecture for Sequential Processing. CoRR abs/2109.13090 (2021) - [i107]Sayeed Shafayet Chowdhury, Nitin Rathi, Kaushik Roy:
One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency. CoRR abs/2110.05929 (2021) - [i106]Sangamesh Kodge, Kaushik Roy:
BERMo: What can BERT learn from ELMo? CoRR abs/2110.15802 (2021) - [i105]Sai Aparna Aketi, Sangamesh Kodge, Kaushik Roy:
Low Precision Decentralized Distributed Training with Heterogeneous Data. CoRR abs/2111.09389 (2021) - [i104]Jason M. Allred, Kaushik Roy:
L4-Norm Weight Adjustments for Converted Spiking Neural Networks. CoRR abs/2111.09446 (2021) - [i103]Amitangshu Mukherjee, Isha Garg, Kaushik Roy:
Encoding Hierarchical Information in Neural Networks helps in Subpopulation Shift. CoRR abs/2112.10844 (2021) - 2020
- [j239]Isha Garg, Priyadarshini Panda, Kaushik Roy:
A Low Effort Approach to Structured CNN Design Using PCA. IEEE Access 8: 1347-1360 (2020) - [j238]Syed Shakib Sarwar, Aayush Ankit, Kaushik Roy:
Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing. IEEE Access 8: 4615-4628 (2020) - [j237]Sai Aparna Aketi, Sourjya Roy, Anand Raghunathan, Kaushik Roy:
Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks. IEEE Access 8: 171924-171932 (2020) - [j236]Amogh Agrawal, Adarsh Kosta, Sangamesh Kodge, Dong Eun Kim, Kaushik Roy:
CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 295-305 (2020) - [j235]Amogh Agrawal, Adarsh Kosta, Sangamesh Kodge, Dong Eun Kim, Kaushik Roy:
Erratum to "CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays". IEEE J. Emerg. Sel. Topics Circuits Syst. 10(4): 588 (2020) - [j234]Aayush Ankit, Indranil Chakraborty, Amogh Agrawal, Mustafa Fayez Ali, Kaushik Roy:
Circuits and Architectures for In-Memory Computing-Based Machine Learning Accelerators. IEEE Micro 40(6): 8-22 (2020) - [j233]Indranil Chakraborty, Deboleena Roy, Isha Garg, Aayush Ankit, Kaushik Roy:
Constructing energy-efficient mixed-precision neural networks through principal component analysis for edge intelligence. Nat. Mach. Intell. 2(1): 43-55 (2020) - [j232]Deboleena Roy, Priyadarshini Panda, Kaushik Roy:
Tree-CNN: A hierarchical Deep Convolutional Neural Network for incremental learning. Neural Networks 121: 148-160 (2020) - [j231]Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Shubham Jain, Sourjya Roy, Shrihari Sridharan, Amogh Agrawal, Anand Raghunathan, Kaushik Roy:
Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges. Proc. IEEE 108(12): 2276-2310 (2020) - [j230]Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-Mei Hwu, Kaushik Roy:
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM. IEEE Trans. Computers 69(8): 1128-1142 (2020) - [j229]Aayush Ankit, Timur Ibrayev, Abhronil Sengupta, Kaushik Roy:
TraNNsformer: Clustered Pruning on Crossbar-Based Architectures for Energy-Efficient Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2361-2374 (2020) - [j228]Swagath Venkataramani, Vivek Joy Kozhikkottu, Amit Sabne, Kaushik Roy, Anand Raghunathan:
Logic Synthesis of Approximate Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2503-2515 (2020) - [j227]Mustafa Fayez Ali, Akhilesh Jaiswal, Kaushik Roy:
In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 155-165 (2020) - [j226]Mustafa Fayez Ali, Robert Andrawis, Kaushik Roy:
Dynamic Read Current Sensing With Amplified Bit-Line Voltage for STT-MRAMs. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 551-555 (2020) - [j225]Mustafa Fayez Ali, Akhilesh Jaiswal, Sangamesh Kodge, Amogh Agrawal, Indranil Chakraborty, Kaushik Roy:
IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2521-2531 (2020) - [j224]Minsuk Koo, Gopalakrishnan Srinivasan, Yong Shim, Kaushik Roy:
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2546-2555 (2020) - [j223]Akhilesh Jaiswal, Robert Andrawis, Amogh Agrawal, Kaushik Roy:
Functional Read Enabling In-Memory Computations in 1Transistor - 1Resistor Memory Arrays. IEEE Trans. Circuits Syst. 67-II(12): 3347-3351 (2020) - [j222]Akhilesh Jaiswal, Amogh Agrawal, Mustafa Fayez Ali, Saima Sharmin, Kaushik Roy:
i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs. IEEE Trans. Circuits Syst. 67-I(12): 4651-4659 (2020) - [j221]Amogh Agrawal, Indranil Chakraborty, Deboleena Roy, Utkarsh Saxena, Saima Sharmin, Minsuk Koo, Yong Shim, Gopalakrishnan Srinivasan, Chamika M. Liyanagedera, Abhronil Sengupta, Kaushik Roy:
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2481-2494 (2020) - [c464]Bing Han, Gopalakrishnan Srinivasan, Kaushik Roy:
RMP-SNN: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Network. CVPR 2020: 13555-13564 - [c463]Kaushik Roy, Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Amogh Agrawal:
In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview. DAC 2020: 1-6 - [c462]Indranil Chakraborty, Mustafa Fayez Ali, Dong Eun Kim, Aayush Ankit, Kaushik Roy:
GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks. DAC 2020: 1-6 - [c461]Chankyu Lee, Adarsh Kosta, Alex Zihao Zhu, Kenneth Chaney, Kostas Daniilidis, Kaushik Roy:
Spike-FlowNet: Event-Based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks. ECCV (29) 2020: 366-382 - [c460]Bing Han, Kaushik Roy:
Deep Spiking Neural Network: Energy Efficiency Through Time Based Coding. ECCV (10) 2020: 388-404 - [c459]Saima Sharmin, Nitin Rathi, Priyadarshini Panda, Kaushik Roy:
Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Non-linear Activations. ECCV (29) 2020: 399-414 - [c458]Gopalakrishnan Srinivasan, Chankyu Lee, Abhronil Sengupta, Priyadarshini Panda, Syed Shakib Sarwar, Kaushik Roy:
Training Deep Spiking Neural Networks for Energy-Efficient Neuromorphic Computing. ICASSP 2020: 8549-8553 - [c457]Nitin Rathi, Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy:
Enabling Deep Spiking Neural Networks with Hybrid Conversion and Spike Timing Dependent Backpropagation. ICLR 2020 - [c456]Krishna Reddy Kesari, Priyadarshini Panda, Gopalakrishnan Srinivasan, Kaushik Roy:
Enabling Homeostasis using Temporal Decay Mechanisms in Spiking CNNs Trained with Unsupervised Spike Timing Dependent Plasticity. IJCNN 2020: 1-8 - [c455]Maryam Parsa, Catherine D. Schuman, Prasanna Date, Derek C. Rose, Bill Kay, J. Parker Mitchell, Steven R. Young, Ryan Dellana, William Severa, Thomas E. Potok, Kaushik Roy:
Hyperparameter Optimization in Binary Communication Networks for Neuromorphic Deployment. IJCNN 2020: 1-9 - [c454]Mustafa Fayez Ali, Amogh Agrawal, Kaushik Roy:
RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks. ISLPED 2020: 61-66 - [c453]Ahmedullah Aziz, Kaushik Roy:
Insulator-Metal Transition Material Based Artificial Neurons: A Design Perspective. ISQED 2020: 444-451 - [c452]Sourav Sanyal, Aayush Ankit, Craig M. Vineyard, Kaushik Roy:
Energy-Efficient Target Recognition using ReRAM Crossbars for Enabling On-Device Intelligence. SiPS 2020: 1-6 - [c451]Priyadarshini Panda, Kaushik Roy:
Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems. VLSID 2020: 1-18 - [i102]Gobinda Saha, Isha Garg, Aayush Ankit, Kaushik Roy:
Structured Compression and Sharing of Representational Space for Continual Learning. CoRR abs/2001.08650 (2020) - [i101]Sai Aparna Aketi, Sourjya Roy, Anand Raghunathan, Kaushik Roy:
Gradual Channel Pruning while Training using Feature Relevance Scores for Convolutional Neural Networks. CoRR abs/2002.09958 (2020) - [i100]Sai Aparna Aketi, Priyadarshini Panda, Kaushik Roy:
Relevant-features based Auxiliary Cells for Energy Efficient Detection of Natural Errors. CoRR abs/2002.11052 (2020) - [i99]Minsuk Koo, Gopalakrishnan Srinivasan, Yong Shim, Kaushik Roy:
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network with On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge. CoRR abs/2002.11163 (2020) - [i98]Jason M. Allred, Steven J. Spencer, Gopalakrishnan Srinivasan, Kaushik Roy:
Explicitly Trained Spiking Sparsity in Spiking Neural Networks with Backpropagation. CoRR abs/2003.01250 (2020) - [i97]Bing Han, Gopalakrishnan Srinivasan, Kaushik Roy:
RMP-SNNs: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Networks. CoRR abs/2003.01811 (2020) - [i96]Chankyu Lee, Adarsh Kosta, Alex Zihao Zhu, Kenneth Chaney, Kostas Daniilidis, Kaushik Roy:
Spike-FlowNet: Event-based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks. CoRR abs/2003.06696 (2020) - [i95]Indranil Chakraborty, Mustafa Fayez Ali, Dong Eun Kim, Aayush Ankit, Kaushik Roy:
GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks. CoRR abs/2003.06902 (2020) - [i94]Saima Sharmin, Nitin Rathi, Priyadarshini Panda, Kaushik Roy:
Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Non-Linear Activations. CoRR abs/2003.10399 (2020) - [i93]Mustafa Fayez Ali, Akhilesh Jaiswal, Sangamesh Kodge, Amogh Agrawal, Indranil Chakraborty, Kaushik Roy:
IMAC: In-memory multi-bit Multiplication andACcumulation in 6T SRAM Array. CoRR abs/2003.12558 (2020) - [i92]Nitin Rathi, Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy:
Enabling Deep Spiking Neural Networks with Hybrid Conversion and Spike Timing Dependent Backpropagation. CoRR abs/2005.01807 (2020) - [i91]Maryam Parsa, Catherine D. Schuman, Prasanna Date, Derek C. Rose, Bill Kay, J. Parker Mitchell, Steven R. Young, Ryan Dellana, William Severa, Thomas E. Potok, Kaushik Roy:
Hyperparameter Optimization in Binary Communication Networks for Neuromorphic Deployment. CoRR abs/2005.04171 (2020) - [i90]Yinghan Long, Indranil Chakraborty, Kaushik Roy:
Conditionally Deep Hybrid Neural Networks Across Edge and Cloud. CoRR abs/2005.10851 (2020) - [i89]Sayeed Shafayet Chowdhury, Chankyu Lee, Kaushik Roy:
Towards Understanding the Effect of Leak in Spiking Neural Networks. CoRR abs/2006.08761 (2020) - [i88]Deepak Ravikumar, Sangamesh Kodge, Isha Garg, Kaushik Roy:
TREND: Transferability based Robust ENsemble Design. CoRR abs/2008.01524 (2020) - [i87]Nitin Rathi, Kaushik Roy:
DIET-SNN: Direct Input Encoding With Leakage and Threshold Optimization in Deep Spiking Neural Networks. CoRR abs/2008.03658 (2020) - [i86]Deboleena Roy, Indranil Chakraborty, Timur Ibrayev, Kaushik Roy:
Robustness Hidden in Plain Sight: Can Analog Computing Defend Against Adversarial Attacks? CoRR abs/2008.12016 (2020) - [i85]Isha Garg, Sayeed Shafayet Chowdhury, Kaushik Roy:
DCT-SNN: Using DCT to Distribute Spatial Information over Time for Learning Low-Latency Spiking Neural Networks. CoRR abs/2010.01795 (2020) - [i84]Deepak Ravikumar, Sangamesh Kodge, Isha Garg, Kaushik Roy:
Exploring Vicinal Risk Minimization for Lightweight Out-of-Distribution Detection. CoRR abs/2012.08398 (2020)
2010 – 2019
- 2019
- [j220]Priyadarshini Panda, Indranil Chakraborty, Kaushik Roy:
Discretization Based Solutions for Secure Machine Learning Against Adversarial Attacks. IEEE Access 7: 70157-70168 (2019) - [j219]Yinghan Long, Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy:
Structured Learning for Action Recognition in Videos. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 475-484 (2019) - [j218]Shubham Jain, Aayush Ankit, Indranil Chakraborty, Tayfun Gokmen, Malte J. Rasch, Wilfried Haensch, Kaushik Roy, Anand Raghunathan:
Neural network accelerator design with resistive crossbars: Opportunities and challenges. IBM J. Res. Dev. 63(6): 10:1-10:13 (2019) - [j217]Chankyu Lee, Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy:
Deep Spiking Convolutional Neural Network Trained With Unsupervised Spike-Timing-Dependent Plasticity. IEEE Trans. Cogn. Dev. Syst. 11(3): 384-394 (2019) - [j216]Amogh Agrawal, Aayush Ankit, Kaushik Roy:
SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives. IEEE Trans. Computers 68(8): 1190-1200 (2019) - [j215]Nitin Rathi, Priyadarshini Panda, Kaushik Roy:
STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 668-677 (2019) - [j214]Amogh Agrawal, Akhilesh Jaiswal, Deboleena Roy, Bing Han, Gopalakrishnan Srinivasan, Aayush Ankit, Kaushik Roy:
Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 3064-3076 (2019) - [j213]Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Ayan Biswas, Kaushik Roy, Shreyas Sen:
Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1365-1377 (2019) - [j212]Aayush Ankit, Minsuk Koo, Shreyas Sen, Kaushik Roy:
Powerline Communication for Enhanced Connectivity in Neuromorphic Systems. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1897-1906 (2019) - [j211]Akhilesh Jaiswal, Indranil Chakraborty, Amogh Agrawal, Kaushik Roy:
8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2556-2567 (2019) - [c450]Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-mei W. Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic:
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. ASPLOS 2019: 715-731 - [c449]Maryam Parsa, J. Parker Mitchell, Catherine D. Schuman, Robert M. Patton, Thomas E. Potok, Kaushik Roy:
Bayesian-based Hyperparameter Optimization for Spiking Neuromorphic Systems. IEEE BigData 2019: 4472-4478 - [c448]Akhilesh Jaiswal, Amogh Agrawal, Indranil Chakraborty, Mustafa Fayez Ali, Kaushik Roy:
Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAM. ACM Great Lakes Symposium on VLSI 2019: 371 - [c447]Maryam Parsa, Aayush Ankit, Amirkoushyar Ziabari, Kaushik Roy:
PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design. ICCAD 2019: 1-8 - [c446]Alex James, Georgios Ch. Sirakoulis, Kaushik Roy:
Smart cameras everywhere: AI vision on edge with emerging memories. ICECS 2019: 422-425 - [c445]Deboleena Roy, Indranil Chakraborty, Kaushik Roy:
Scaling Deep Spiking Neural Networks with Binary Stochastic Activations. ICCC 2019: 50-58 - [c444]Akhilesh Jaiswal, Amogh Agrawal, Indranil Chakraborty, Deboleena Roy, Kaushik Roy:
On Robustness of Spin-Orbit-Torque Based Stochastic Sigmoid Neurons for Spiking Neural Networks. IJCNN 2019: 1-6 - [c443]Priyadarshini Panda, Efstathia Soufleri, Kaushik Roy:
Evaluating the Stability of Recurrent Neural Models during Training with Eigenvalue Spectra Analysis. IJCNN 2019: 1-8 - [c442]Saima Sharmin, Priyadarshini Panda, Syed Shakib Sarwar, Chankyu Lee, Wachirawit Ponghiran, Kaushik Roy:
A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks. IJCNN 2019: 1-8 - [c441]Franck Le, Mudhakar Srivatsa, Krishna Kesari Reddy, Kaushik Roy:
Using Graphical Models as Explanations in Deep Neural Networks. MASS 2019: 283-289 - [c440]Deboleena Roy, Gopalakrishnan Srinivasan, Priyadarshini Panda, Richard Tomsett, Nirmit Desai, Raghu K. Ganti, Kaushik Roy:
Neural Networks at the Edge. SMARTCOMP 2019: 45-50 - [p3]Ashish Ranjan, Swagath Venkataramani, Shubham Jain, Younghoon Kim, Shankar Ganesh Ramasubramanian, Arnab Raha, Kaushik Roy, Anand Raghunathan:
Automatic Synthesis Techniques for Approximate Circuits. Approximate Circuits 2019: 123-140 - [i83]Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-Mei Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic:
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. CoRR abs/1901.10351 (2019) - [i82]Indranil Chakraborty, Deboleena Roy, Aayush Ankit, Kaushik Roy:
Efficient Hybrid Network Architectures for Extremely Quantized Neural Networks Enabling Intelligence at the Edge. CoRR abs/1902.00460 (2019) - [i81]Priyadarshini Panda, Indranil Chakraborty, Kaushik Roy:
Discretization based Solutions for Secure Machine Learning against Adversarial Attacks. CoRR abs/1902.03151 (2019) - [i80]Jason M. Allred, Kaushik Roy:
Stimulating STDP to Exploit Locality for Lifelong Learning without Catastrophic Forgetting. CoRR abs/1902.03187 (2019) - [i79]Gopalakrishnan Srinivasan, Kaushik Roy:
ReStoCNet: Residual Stochastic Binary Convolutional Spiking Neural Network for Memory-Efficient Neuromorphic Computing. CoRR abs/1902.04161 (2019) - [i78]Chankyu Lee, Syed Shakib Sarwar, Kaushik Roy:
Enabling Spike-based Backpropagation in State-of-the-art Deep Neural Network Architectures. CoRR abs/1903.06379 (2019) - [i77]Saima Sharmin, Priyadarshini Panda, Syed Shakib Sarwar, Chankyu Lee, Wachirawit Ponghiran, Kaushik Roy:
A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks. CoRR abs/1905.02704 (2019) - [i76]Priyadarshini Panda, Efstathia Soufleri, Kaushik Roy:
Evaluating the Stability of Recurrent Neural Models during Training with Eigenvalue Spectra Analysis. CoRR abs/1905.03219 (2019) - [i75]Indranil Chakraborty, Deboleena Roy, Isha Garg, Aayush Ankit, Kaushik Roy:
PCA-driven Hybrid network design for enabling Intelligence at the Edge. CoRR abs/1906.01493 (2019) - [i74]Wachirawit Ponghiran, Gopalakrishnan Srinivasan, Kaushik Roy:
Reinforcement Learning with Low-Complexity Liquid State Machines. CoRR abs/1906.01695 (2019) - [i73]Maryam Parsa, Aayush Ankit, Amirkoushyar Ziabari, Kaushik Roy:
PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design. CoRR abs/1906.08167 (2019) - [i72]Deboleena Roy, Priyadarshini Panda, Kaushik Roy:
Synthesizing Images from Spatio-Temporal Representations using Spike-based Backpropagation. CoRR abs/1906.08861 (2019) - [i71]Amogh Agrawal, Chankyu Lee, Kaushik Roy:
X-CHANGR: Changing Memristive Crossbar Mapping for Mitigating Line-Resistance Induced Accuracy Degradation in Deep Neural Networks. CoRR abs/1907.00285 (2019) - [i70]Priyadarshini Panda, Sai Aparna Aketi, Kaushik Roy:
Towards Scalable, Efficient and Accurate Deep Spiking Neural Networks with Backward Residual Connections, Stochastic Softmax and Hybridization. CoRR abs/1910.13931 (2019) - [i69]Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-Mei W. Hwu, Kaushik Roy:
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM. CoRR abs/1912.11516 (2019) - 2018
- [j210]Priyadarshini Panda, Jason M. Allred, Shriram Ramanathan, Kaushik Roy:
ASP: Learning to Forget With Adaptive Synaptic Plasticity in Spiking Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 51-64 (2018) - [j209]Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Bing Han, Parami Wijesinghe, Akhilesh Jaiswal, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy:
Energy Efficient Neural Computing: A Study of Cross-Layer Approximations. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(4): 796-809 (2018) - [j208]Syed Shakib Sarwar, Swagath Venkataramani, Aayush Ankit, Anand Raghunathan, Kaushik Roy:
Energy-Efficient Neural Computing with Approximate Multipliers. ACM J. Emerg. Technol. Comput. Syst. 14(2): 16:1-16:23 (2018) - [j207]Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy:
STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing. ACM J. Emerg. Technol. Comput. Syst. 14(4): 44:1-44:12 (2018) - [j206]Devyani Patra, Ahmed Kamal Reza, Mohammad Khaled Hassan, Mehdi Katoozi, Ethan H. Cannon, Kaushik Roy, Yu Cao:
Adaptive accelerated aging for 28 nm HKMG technology. Microelectron. Reliab. 80: 149-154 (2018) - [j205]Zoha Pajouhi, Kaushik Roy:
Image Edge Detection Based on Swarm Intelligence Using Memristive Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1774-1787 (2018) - [j204]Amogh Agrawal, Akhilesh Jaiswal, Chankyu Lee, Kaushik Roy:
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4219-4232 (2018) - [j203]Indranil Chakraborty, Deboleena Roy, Kaushik Roy:
Technology Aware Training in Memristive Neuromorphic Systems for Nonideal Synaptic Crossbars. IEEE Trans. Emerg. Top. Comput. Intell. 2(5): 335-344 (2018) - [j202]Parami Wijesinghe, Aayush Ankit, Abhronil Sengupta, Kaushik Roy:
An All-Memristor Deep Spiking Neural Computing System: A Step Toward Realizing the Low-Power Stochastic Brain. IEEE Trans. Emerg. Top. Comput. Intell. 2(5): 345-358 (2018) - [j201]Bing Han, Aayush Ankit, Abhronil Sengupta, Kaushik Roy:
Cross-Layer Design Exploration for Energy-Quality Tradeoffs in Spiking and Non-Spiking Deep Artificial Neural Networks. IEEE Trans. Multi Scale Comput. Syst. 4(4): 613-623 (2018) - [j200]Bing Han, Kaushik Roy:
DeltaFrame-BP: An Algorithm Using Frame Difference for Deep Convolutional Neural Networks Training and Inference on Video Data. IEEE Trans. Multi Scale Comput. Syst. 4(4): 624-634 (2018) - [j199]Arnab Raha, Akhilesh Jaiswal, Syed Shakib Sarwar, Hrishikesh Jayakumar, Vijay Raghunathan, Kaushik Roy:
Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 294-307 (2018) - [j198]Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan:
Computing in Memory With Spin-Transfer Torque Magnetic RAM. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 470-483 (2018) - [j197]Yeongkyo Seo, Kaushik Roy:
High-Density SOT-MRAM Based on Shared Bitline Structure. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1600-1603 (2018) - [c439]Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan:
Computing-in-memory with spintronics. DATE 2018: 1640-1645 - [c438]Joao Ambrosi, Aayush Ankit, Rodrigo Antunes, Sai Rahul Chalamalasetti, Soumitra Chatterjee, Izzat El Hajj, Guilherme Fachini, Paolo Faraboschi, Martin Foltin, Sitao Huang, Wen-Mei Hwu, Gustavo Knuppe, Sunil Vishwanathpur Lakshminarasimha, Dejan S. Milojicic, Mohan Parthasarathy, Filipe Ribeiro, Lucas Rosa, Kaushik Roy, Plínio Silveira, John Paul Strachan:
Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning. ICRC 2018: 1-13 - [c437]Devyani Patra, Ahmed Kamal Reza, Mehdi Katoozi, Ethan H. Cannon, Kaushik Roy, Yu Cao:
Accelerated BTI degradation under stochastic TDDB effect. IRPS 2018: 5 - [c436]Darya Mikhailenko, Chamika M. Liyanagedera, Alex Pappachen James, Kaushik Roy:
M2CA: Modular Memristive Crossbar Arrays. ISCAS 2018: 1-5 - [c435]Aayush Ankit, Abhronil Sengupta, Kaushik Roy:
Neuromorphic Computing Across the Stack: Devices, Circuits and Architectures. SiPS 2018: 1-6 - [c434]Amogh Agrawal, Kaushik Roy:
RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing. SiPS 2018: 19-24 - [c433]Andres F. Gomez, Freddy Forero, Kaushik Roy, Víctor H. Champac:
Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. VLSI-SoC 2018: 65-70 - [c432]Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy:
Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. VLSI-SoC (Selected Papers) 2018: 207-231 - [i68]Abhronil Sengupta, Yuting Ye, Robert Wang, Chiao Liu, Kaushik Roy:
Going Deeper in Spiking Neural Networks: VGG and Residual Architectures. CoRR abs/1802.02627 (2018) - [i67]Deboleena Roy, Priyadarshini Panda, Kaushik Roy:
Tree-CNN: A Deep Convolutional Neural Network for Lifelong Learning. CoRR abs/1802.05800 (2018) - [i66]Akhilesh Jaiswal, Indranil Chakraborty, Amogh Agrawal, Kaushik Roy:
8T SRAM Cell as a Multi-bit Dot Product Engine for Beyond von-Neumann Computing. CoRR abs/1802.08601 (2018) - [i65]Zubair Al Azim, Akhilesh Jaiswal, Indranil Chakraborty, Kaushik Roy:
Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency. CoRR abs/1802.10431 (2018) - [i64]Indranil Chakraborty, Amogh Agrawal, Kaushik Roy:
Proposal for a Low Voltage Analog-to-Digital Converter using Voltage Controlled Stochastic Switching of Low Barrier Nanomagnets. CoRR abs/1803.01431 (2018) - [i63]Indranil Chakraborty, Gobinda Saha, Abhronil Sengupta, Kaushik Roy:
All-Photonic Phase Change Spiking Neuron: Toward Fast Neural Computing using Light. CoRR abs/1804.00267 (2018) - [i62]Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Ayan Biswas, Kaushik Roy, Shreyas Sen:
Exploiting Inherent Error-Resiliency of Neuromorphic Computing to achieve Extreme Energy-Efficiency through Mixed-Signal Neurons. CoRR abs/1806.05141 (2018) - [i61]Amogh Agrawal, Akhilesh Jaiswal, Bing Han, Gopalakrishnan Srinivasan, Kaushik Roy:
Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays. CoRR abs/1807.00343 (2018) - [i60]Priyadarshini Panda, Kaushik Roy:
Explainable Learning: Implicit Generative Modelling during Training for Adversarial Robustness. CoRR abs/1807.02188 (2018) - [i59]Indranil Chakraborty, Gobinda Saha, Kaushik Roy:
Photonic Spiking Neural Networks - From Devices to Systems. CoRR abs/1808.01241 (2018) - [i58]Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan:
Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars. CoRR abs/1809.00072 (2018) - [i57]Isha Garg, Priyadarshini Panda, Kaushik Roy:
A Low Effort Approach to Structured CNN Design Using PCA. CoRR abs/1812.06224 (2018) - 2017
- [j196]Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy:
Energy-Efficient and Improved Image Recognition with Conditional Deep Learning. ACM J. Emerg. Technol. Comput. Syst. 13(3): 33:1-33:21 (2017) - [j195]Karthik Yogendra, Chamika M. Liyanagedera, Deliang Fan, Yong Shim, Kaushik Roy:
Coupled Spin-Torque Nano-Oscillator-Based Computation: A Simulation Study. ACM J. Emerg. Technol. Comput. Syst. 13(4): 56:1-56:24 (2017) - [j194]Mohammad Khaled Hassan, Kaushik Roy:
Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors. Microelectron. Reliab. 70: 22-31 (2017) - [j193]Priyadarshini Panda, Aayush Ankit, Parami Wijesinghe, Kaushik Roy:
FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2017-2029 (2017) - [j192]Yeongkyo Seo, Xuanyao Fong, Kaushik Roy:
Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1573-1577 (2017) - [j191]Priyadarshini Panda, Swagath Venkataramani, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy:
Energy-Efficient Object Detection Using Semantic Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2673-2677 (2017) - [c431]Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami:
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC 2017: 16:1-16:6 - [c430]Aayush Ankit, Abhronil Sengupta, Priyadarshini Panda, Kaushik Roy:
RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks. DAC 2017: 27:1-27:6 - [c429]Parami Wijesinghe, Chamika M. Liyanagedera, Kaushik Roy:
Fast, low power evaluation of elementary functions using radial basis function networks. DATE 2017: 208-213 - [c428]Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan:
STAxCache: An approximate, energy efficient STT-MRAM cache. DATE 2017: 356-361 - [c427]Gopalakrishnan Srinivasan, Abhronil Sengupta, Kaushik Roy:
Magnetic tunnel junction enabled all-spin stochastic spiking neural network. DATE 2017: 530-535 - [c426]Priyadarshini Panda, Kaushik Roy:
Semantic driven hierarchical learning for energy-efficient image classification. DATE 2017: 1582-1587 - [c425]Maryam Parsa, Priyadarshini Panda, Shreyas Sen, Kaushik Roy:
Staged Inference using Conditional Deep Learning for energy efficient real-time smart diagnosis. EMBC 2017: 78-81 - [c424]Aayush Ankit, Abhronil Sengupta, Kaushik Roy:
TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design. ICCAD 2017: 533-540 - [c423]Yong Shim, Akhilesh Jaiswal, Kaushik Roy:
Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization. ICCD 2017: 605-608 - [c422]Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Kaushik Roy, Shreyas Sen:
An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems. ICRC 2017: 1-2 - [c421]Gopalakrishnan Srinivasan, Sourjya Roy, Vijay Raghunathan, Kaushik Roy:
Spike timing dependent plasticity based enhanced self-learning for efficient pattern recognition in spiking neural networks. IJCNN 2017: 1847-1854 - [c420]Chamika M. Liyanagedera, Parami Wijesinghe, Akhilesh Jaiswal, Kaushik Roy:
Image segmentation with stochastic magnetic tunnel junctions and spiking neurons. IJCNN 2017: 2460-2468 - [c419]Priyadarshini Panda, Gopalakrishnan Srinivasan, Kaushik Roy:
EnsembleSNN: Distributed assistive STDP learning for energy-efficient recognition in spiking neural networks. IJCNN 2017: 2629-2635 - [c418]Jason M. Allred, Kaushik Roy:
Convolving over time via recurrent connections for sequential weight sharing in neural networks. IJCNN 2017: 4444-4450 - [c417]Abhronil Sengupta, Aayush Ankit, Kaushik Roy:
Performance analysis and benchmarking of all-spin spiking neural networks (Special session paper). IJCNN 2017: 4557-4563 - [c416]Zubair Azim, Kaushik Roy:
Spin-torque sensors with differential signaling for fast and energy efficient global interconnects. ISLPED 2017: 1-6 - [c415]Syed Shakib Sarwar, Priyadarshini Panda, Kaushik Roy:
Gabor filter assisted energy efficient fast learning Convolutional Neural Networks. ISLPED 2017: 1-6 - [c414]Karthik Yogendra, Minsuk Koo, Kaushik Roy:
Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal. NANOARCH 2017: 89-94 - [c413]Mesut Atasoyu, Mustafa Altun, Serdar Özoguz, Kaushik Roy:
Spin-torque memristor based offset cancellation technique for sense amplifiers. SMACD 2017: 1-4 - [i56]Akhilesh Jaiswal, Indranil Chakraborty, Kaushik Roy:
Energy-Efficient Memories using Magneto-Electric Switching of Ferromagnets. CoRR abs/1701.08208 (2017) - [i55]Aayush Ankit, Abhronil Sengupta, Priyadarshini Panda, Kaushik Roy:
RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks. CoRR abs/1702.06064 (2017) - [i54]Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan:
Computing in Memory with Spin-Transfer Torque Magnetic RAM. CoRR abs/1703.02118 (2017) - [i53]Priyadarshini Panda, Gopalakrishnan Srinivasan, Kaushik Roy:
Convolutional Spike Timing Dependent Plasticity based Feature Learning in Spiking Neural Networks. CoRR abs/1703.03854 (2017) - [i52]Priyadarshini Panda, Jason M. Allred, Shriram Ramanathan, Kaushik Roy:
ASP: Learning to Forget with Adaptive Synaptic Plasticity in Spiking Neural Networks. CoRR abs/1703.07655 (2017) - [i51]Syed Shakib Sarwar, Priyadarshini Panda, Kaushik Roy:
Gabor Filter Assisted Energy Efficient Fast Learning Convolutional Neural Networks. CoRR abs/1705.04748 (2017) - [i50]Akhilesh Jaiswal, Amogh Agrawal, Kaushik Roy:
Proposal for a Leaky Integrate Fire Spiking Neuron Using Voltage Driven Domain Wall Motion. CoRR abs/1705.06942 (2017) - [i49]Yong Shim, Shuhan Chen, Abhronil Sengupta, Kaushik Roy:
Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference. CoRR abs/1707.04687 (2017) - [i48]Aayush Ankit, Abhronil Sengupta, Kaushik Roy:
TraNNsformer: Neural Network Transformation for Memristive Crossbar based Neuromorphic System Design. CoRR abs/1708.07949 (2017) - [i47]Chamika M. Liyanagedera, Abhronil Sengupta, Akhilesh Jaiswal, Kaushik Roy:
Magnetic Tunnel Junction Enabled Stochastic Spiking Neural Networks: From Non-Telegraphic to Telegraphic Switching Regime. CoRR abs/1709.09247 (2017) - [i46]Nitin Rathi, Priyadarshini Panda, Kaushik Roy:
STDP Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy Efficient Recognition. CoRR abs/1710.04734 (2017) - [i45]Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Kaushik Roy, Shreyas Sen:
An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems. CoRR abs/1710.09012 (2017) - [i44]Abhronil Sengupta, Kaushik Roy:
Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing. CoRR abs/1711.02235 (2017) - [i43]Amogh Agrawal, Aayush Ankit, Kaushik Roy:
SPARE: Spiking Networks Acceleration Using CMOS ROM-Embedded RAM as an In-Memory-Computation Primitive. CoRR abs/1711.07546 (2017) - [i42]Indranil Chakraborty, Deboleena Roy, Kaushik Roy:
Technology Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic Crossbars. CoRR abs/1711.08889 (2017) - [i41]Parami Wijesinghe, Aayush Ankit, Abhronil Sengupta, Kaushik Roy:
An All-Memristor Deep Spiking Neural Network: A Step Towards Realizing the Low Power, Stochastic Brain. CoRR abs/1712.01472 (2017) - [i40]Syed Shakib Sarwar, Aayush Ankit, Kaushik Roy:
Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing. CoRR abs/1712.02719 (2017) - [i39]Amogh Agrawal, Akhilesh Jaiswal, Kaushik Roy:
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories. CoRR abs/1712.05096 (2017) - [i38]Priyadarshini Panda, Kaushik Roy:
Chaos-guided Input Structuring for Improved Learning in Recurrent Neural Networks. CoRR abs/1712.09206 (2017) - 2016
- [j190]Kaushik Roy, Byunghoo Jung, Dimitrios Peroulis, Anand Raghunathan:
Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. IEEE Des. Test 33(3): 56-65 (2016) - [j189]Akhilesh Jaiswal, Xuanyao Fong, Kaushik Roy:
Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 120-133 (2016) - [j188]Yeongkyo Seo, Kon-Woo Kwon, Xuanyao Fong, Kaushik Roy:
High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 293-304 (2016) - [j187]Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy:
Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC. ACM J. Emerg. Technol. Comput. Syst. 13(2): 20:1-20:20 (2016) - [j186]A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes. ACM J. Emerg. Technol. Comput. Syst. 13(2): 23:1-23:22 (2016) - [j185]Xuanyao Fong, Yusung Kim, Rangharajan Venkatesan, Sri Harsha Choday, Anand Raghunathan, Kaushik Roy:
Spin-Transfer Torque Memories: Devices, Circuits, and Systems. Proc. IEEE 104(7): 1449-1488 (2016) - [j184]Abhronil Sengupta, Yong Shim, Kaushik Roy:
Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets. IEEE Trans. Biomed. Circuits Syst. 10(6): 1152-1160 (2016) - [j183]Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
Cache Design with Domain Wall Memory. IEEE Trans. Computers 65(4): 1010-1024 (2016) - [j182]Xuanyao Fong, Yusung Kim, Karthik Yogendra, Deliang Fan, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy:
Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 1-22 (2016) - [j181]Abhronil Sengupta, Kaushik Roy:
A Vision for All-Spin Neural Networks: A Device to System Perspective. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(12): 2267-2277 (2016) - [j180]Deliang Fan, Mrigank Sharad, Abhronil Sengupta, Kaushik Roy:
Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing. IEEE Trans. Neural Networks Learn. Syst. 27(9): 1907-1919 (2016) - [j179]Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy:
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 992-1002 (2016) - [j178]Himanshu Markandeya, Kaushik Roy:
Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2679-2688 (2016) - [c412]Abhronil Sengupta, Karthik Yogendra, Deliang Fan, Kaushik Roy:
Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses. ASP-DAC 2016: 115-120 - [c411]Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Efficient embedded learning for IoT devices. ASP-DAC 2016: 308-311 - [c410]Karthik Yogendra, Deliang Fan, Yong Shim, Minsuk Koo, Kaushik Roy:
Computing with coupled Spin Torque Nano Oscillators. ASP-DAC 2016: 312-317 - [c409]Abhronil Sengupta, Bing Han, Kaushik Roy:
Toward a spintronic deep learning spiking neural processor. BioCAS 2016: 544-547 - [c408]Younghoon Kim, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Designing approximate circuits using clock overgating. DAC 2016: 15:1-15:6 - [c407]Yong Shim, Abhronil Sengupta, Kaushik Roy:
Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications. DAC 2016: 21:1-21:6 - [c406]Priyadarshini Panda, Abhronil Sengupta, Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems. DAC 2016: 98:1-98:6 - [c405]Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing. DATE 2016: 145-150 - [c404]Gopalakrishnan Srinivasan, Parami Wijesinghe, Syed Shakib Sarwar, Akhilesh Jaiswal, Kaushik Roy:
Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks. DATE 2016: 151-156 - [c403]Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy:
Conditional Deep Learning for energy-efficient and enhanced pattern recognition. DATE 2016: 475-480 - [c402]Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy:
Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD 2016: 81 - [c401]Priyadarshini Panda, Kaushik Roy:
Unsupervised regenerative learning of hierarchical features in Spiking Deep Networks for object recognition. IJCNN 2016: 299-306 - [c400]Bing Han, Abhronil Sengupta, Kaushik Roy:
On the energy benefits of spiking deep neural networks: A case study. IJCNN 2016: 971-976 - [c399]Chamika M. Liyanagedera, Karthik Yogendra, Kaushik Roy, Deliang Fan:
Spin torque nano-oscillator based Oscillatory Neural Network. IJCNN 2016: 1387-1394 - [c398]Jason M. Allred, Kaushik Roy:
Unsupervised incremental STDP learning using forced firing of dormant or idle neurons. IJCNN 2016: 2492-2499 - [c397]Govind Narasimman, Subhrajit Roy, Xuanyao Fong, Kaushik Roy, Chip-Hong Chang, Arindam Basu:
A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. ISCAS 2016: 914-917 - [c396]Abhronil Sengupta, Karthik Yogendra, Kaushik Roy:
Spintronic devices for ultra-low power neuromorphic computation (Special session paper). ISCAS 2016: 922-925 - [c395]Sohail Ahasan, Saurav Maji, Kaushik Roy, Mrigank Sharad:
Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple. ISVLSI 2016: 337-342 - [c394]Akhilesh Jaiswal, Kaushik Roy:
Spin transfer torque memories for on-chip caches: Prospects and perspectives. LATS 2016: 7 - [c393]Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Approximate Computing. VLSID 2016: 3-4 - [c392]Abhronil Sengupta, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy:
Neuromorphic Computing Enabled by Spin-Transfer Torque Devices. VLSID 2016: 32-37 - [i37]Priyadarshini Panda, Kaushik Roy:
Unsupervised Regenerative Learning of Hierarchical Features in Spiking Deep Networks for Object Recognition. CoRR abs/1602.01510 (2016) - [i36]Gopalakrishnan Srinivasan, Parami Wijesinghe, Syed Shakib Sarwar, Akhilesh Jaiswal, Kaushik Roy:
Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks. CoRR abs/1602.08556 (2016) - [i35]Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing. CoRR abs/1602.08557 (2016) - [i34]Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy:
Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction. CoRR abs/1605.04494 (2016) - [i33]Zoha Pajouhi, Kaushik Roy:
Image Edge Detection based on Swarm Intelligence using Memristive Networks. CoRR abs/1606.05387 (2016) - [i32]Priyadarshini Panda, Kaushik Roy:
Attention Tree: Learning Hierarchies of Visual Features for Large-Scale Image Recognition. CoRR abs/1608.00611 (2016) - [i31]Priyadarshini Panda, Aayush Ankit, Parami Wijesinghe, Kaushik Roy:
FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition. CoRR abs/1609.03396 (2016) - [i30]Yong Shim, Akhilesh Jaiswal, Kaushik Roy:
Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction. CoRR abs/1609.05926 (2016) - [i29]Akhilesh Jaiswal, Sourjya Roy, Gopalakrishnan Srinivasan, Kaushik Roy:
Proposal for a Leaky-Integrate-Fire Spiking Neuron based on Magneto-Electric Switching of Ferro-magnets. CoRR abs/1609.09158 (2016) - [i28]Akhilesh Jaiswal, Kaushik Roy:
MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic. CoRR abs/1611.07738 (2016) - 2015
- [j177]Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy:
Guest Editorial Computing in Emerging Technologies (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 1-4 (2015) - [j176]Kaushik Roy, Deliang Fan, Xuanyao Fong, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, Saibal Mukhopadhyay:
Exploring Spin Transfer Torque Devices for Unconventional Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 5-16 (2015) - [j175]Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage. ACM J. Emerg. Technol. Comput. Syst. 12(1): 4:1-4:27 (2015) - [j174]Chih-Hsiang Ho, Soo Youn Kim, Kaushik Roy:
Ultra-thin dielectric breakdown in devices and circuits: A brief review. Microelectron. Reliab. 55(2): 308-317 (2015) - [j173]Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy:
Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7): 1176-1187 (2015) - [j172]Zoha Pajouhi, Swagath Venkataramani, Karthik Yogendra, Anand Raghunathan, Kaushik Roy:
Exploring Spin-Transfer-Torque Devices for Logic Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1441-1454 (2015) - [j171]Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy:
Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell. IEEE Trans. Inf. Forensics Secur. 10(8): 1630-1642 (2015) - [j170]Himanshu Markandeya, Pedro P. Irazoqui, Kaushik Roy:
Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 208-212 (2015) - [c391]Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing and the quest for computing efficiency. DAC 2015: 120:1-120:6 - [c390]Ashish Ranjan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan:
Approximate storage for energy efficient spintronic memories. DAC 2015: 195:1-195:6 - [c389]Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan:
DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s. DATE 2015: 181-186 - [c388]A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Asymmetric underlapped FinFET based robust SRAM design at 7nm node. DATE 2015: 659-664 - [c387]Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Computing approximately, and efficiently. DATE 2015: 748-751 - [c386]Zoha Pajouhi, Xuanyao Fong, Kaushik Roy:
Device/circuit/architecture co-design of reliable STT-MRAM. DATE 2015: 1437-1442 - [c385]Ankit Sharma, A. Arun Goud, Kaushik Roy:
Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems. DATE 2015: 1443-1448 - [c384]Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan:
Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing. DATE 2015: 1575-1578 - [c383]Abhronil Sengupta, Kaushik Roy:
Spin-Transfer Torque Magnetic neuron for low power neuromorphic computing. IJCNN 2015: 1-7 - [c382]Karthik Yogendra, Mei-Chin Chen, Xuanyao Fong, Kaushik Roy:
Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter. ISQED 2015: 604-609 - [c381]Kaushik Roy, Anand Raghunathan:
Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications. ISVLSI 2015: 473-475 - [i27]Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy:
Yield, Area and Energy Optimization in Stt-MRAMs using failure aware ECC. CoRR abs/1509.08806 (2015) - [i26]Priyadarshini Panda, Abhronil Sengupta, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Object Detection using Semantic Decomposition for Energy-Efficient Neural Computing. CoRR abs/1509.08970 (2015) - [i25]Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy:
Conditional Deep Learning for Energy-Efficient and Enhanced Pattern Recognition. CoRR abs/1509.08971 (2015) - [i24]Abhronil Sengupta, Aparajita Banerjee, Kaushik Roy:
Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems. CoRR abs/1510.00432 (2015) - [i23]Abhronil Sengupta, Priyadarshini Panda, Parami Wijesinghe, Yusung Kim, Kaushik Roy:
Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons. CoRR abs/1510.00440 (2015) - [i22]Abhronil Sengupta, Yong Shim, Kaushik Roy:
Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets. CoRR abs/1510.00459 (2015) - [i21]Abhronil Sengupta, Kaushik Roy:
Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses. CoRR abs/1511.00051 (2015) - [i20]Tathagata Srimani, Bibhas Manna, Anand Kumar Mukhopadhyay, Kaushik Roy, Mrigank Sharad:
High Sensitivity Biosensor using Injection Locked Spin Torque Nano-Oscillators. CoRR abs/1511.09072 (2015) - [i19]Sohail Ahasan, Saurav Maji, Kaushik Roy, Mrigank Sharad:
Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple. CoRR abs/1511.09074 (2015) - [i18]Aranya Goswamy, Sagar Kumashi, Vikash Sehwag, Siddharth Singh, Manny Jain, Kaushik Roy, Mrigank Sharad:
Energy Efficient and High Performance Current-Mode Neural Network Circuit using Memristors and Digitally Assisted Analog CMOS Neurons. CoRR abs/1511.09085 (2015) - [i17]Zubair Al Azim, Abhronil Sengupta, Syed Shakib Sarwar, Kaushik Roy:
Spin-Torque Sensors for Energy Efficient High Speed Long Interconnects. CoRR abs/1512.00762 (2015) - 2014
- [j169]Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy:
Guest Editorial Computing in Emerging Technologies (First Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 377-379 (2014) - [j168]Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Hooman Farkhani, Dag T. Wisland, Jens Kargaard Madsen, Hamid Mahmoodi, Kaushik Roy:
Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology. Microelectron. J. 45(1): 23-34 (2014) - [j167]Xuanyao Fong, Yusung Kim, Sri Harsha Choday, Kaushik Roy:
Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 384-395 (2014) - [j166]Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim, Kaushik Roy:
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 712-720 (2014) - [j165]Vinay Kumar Chippa, Debabrata Mohapatra, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan:
Scalable Effort Hardware Design. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 2004-2016 (2014) - [j164]François Botman, David Bol, Jean-Didier Legat, Kaushik Roy:
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2561-2570 (2014) - [c380]Ivo Bolsens, Georges G. E. Gielen, Kaushik Roy, Ulf Schneider:
"All Programmable SOC FPGA for networking and computing in big data infrastructure". ASP-DAC 2014: 1-3 - [c379]Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
ASLAN: Synthesis of approximate sequential circuits. DATE 2014: 1-6 - [c378]Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra:
Brain-inspired computing with spin torque devices. DATE 2014: 1-6 - [c377]Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing for efficient information processing. ESTIMedia 2014: 9-10 - [c376]Sri Harsha Choday, Kon-Woo Kwon, Kaushik Roy:
Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting. ICCAD 2014: 535-541 - [c375]Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. ISCA 2014: 253-264 - [c374]Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy:
Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM. ISCAS 2014: 2169-2172 - [c373]Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing. ISLPED 2014: 15-20 - [c372]Swagath Venkataramani, Ashish Ranjan, Kaushik Roy, Anand Raghunathan:
AxNN: energy-efficient neuromorphic systems using approximate computing. ISLPED 2014: 27-32 - [c371]Vinay K. Chippa, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
StoRM: a stochastic recognition and mining processor. ISLPED 2014: 39-44 - [c370]Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra:
Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives. ISVLSI 2014: 398-402 - [i16]Deliang Fan, Mrigank Sharad, Kaushik Roy:
Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic. CoRR abs/1402.2648 (2014) - [i15]Deliang Fan, Mrigank Sharad, Abhronil Sengupta, Kaushik Roy:
Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing. CoRR abs/1402.2902 (2014) - [i14]Abhronil Sengupta, Sri Harsha Choday, Yusung Kim, Kaushik Roy:
Spin Orbit Torque Based Electronic Neuron. CoRR abs/1410.1257 (2014) - [i13]Zubair Al Azim, Xuanyao Fong, Thomas Ostler, Roy W. Chantrell, Kaushik Roy:
Laser Induced Magnetization Reversal for Detection in Optical Interconnects. CoRR abs/1410.2887 (2014) - [i12]Abhronil Sengupta, Zubair Al Azim, Xuanyao Fong, Kaushik Roy:
Spin-Orbit Torque Induced Spike-Timing Dependent Plasticity. CoRR abs/1412.6548 (2014) - [i11]Deliang Fan, Yong Shim, Anand Raghunathan, Kaushik Roy:
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks. CoRR abs/1412.8648 (2014) - 2013
- [j163]Sumeet Kumar Gupta, Kaushik Roy:
Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs. IEEE Des. Test 30(6): 29-39 (2013) - [j162]Niladri Narayan Mojumder, Xuanyao Fong, Charles Augustine, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy:
Dual pillar spin-transfer torque MRAMs for low power applications. ACM J. Emerg. Technol. Comput. Syst. 9(2): 14:1-14:17 (2013) - [j161]Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia:
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis. IEEE Trans. Computers 62(11): 2183-2195 (2013) - [j160]Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy:
Low-Power Digital Signal Processing Using Approximate Adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 124-137 (2013) - [j159]Vinay K. Chippa, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan:
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling. ACM Trans. Embed. Comput. Syst. 12(2s): 90:1-90:23 (2013) - [j158]Dongsoo Lee, Kaushik Roy:
Area Efficient ROM-Embedded SRAM Cache. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1583-1595 (2013) - [c369]Vinay K. Chippa, Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Approximate computing: An integrated hardware approach. ACSSC 2013: 111-117 - [c368]Vinay K. Chippa, Hrishikesh Jayakumar, Debabrata Mohapatra, Kaushik Roy, Anand Raghunathan:
Energy-efficient recognition and mining processor using scalable effort design. CICC 2013: 1-4 - [c367]Mrigank Sharad, Deliang Fan, Kaushik Roy:
Ultra low power associative computing with spin neurons and resistive crossbar memory. DAC 2013: 107:1-107:6 - [c366]Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Analysis and characterization of inherent application resilience for approximate computing. DAC 2013: 113:1-113:9 - [c365]Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits. DATE 2013: 1367-1372 - [c364]Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes. DATE 2013: 1825-1830 - [c363]Kaushik Roy:
Approximate computing for energy-efficient error-resilient multimedia systems. DDECS 2013: 5-6 - [c362]Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra:
Exploring Boolean and non-Boolean computing with spin torque devices. ICCAD 2013: 576-580 - [c361]Anand Raghunathan, Kaushik Roy:
Approximate computing: Energy-efficient computing with good-enough results. IOLTS 2013: 258 - [c360]Mrigank Sharad, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches. ISLPED 2013: 64-69 - [c359]Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra:
Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices. ISLPED 2013: 139-142 - [c358]Mrigank Sharad, Deliang Fan, Kaushik Roy:
Low power and compact mixed-mode signal processing hardware using spin-neurons. ISQED 2013: 189-195 - [c357]Mrigank Sharad, Karthik Yogendra, Kon-Woo Kwon, Kaushik Roy:
Design of ultra high density and low power computational blocks using nano-magnets. ISQED 2013: 223-230 - [c356]Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan:
Quality programmable vector processors for approximate computing. MICRO 2013: 1-12 - [c355]Mrigank Sharad, Karthik Yogendra, Kaushik Roy:
Energy efficient computing using coupled Dual-Pillar Spin Torque Nano Oscillators. NANOARCH 2013: 28-29 - [c354]Mrigank Sharad, Rangharajan Venkatesan, Xuanyao Fong, Anand Raghunathan, Kaushik Roy:
Reading spin-torque memory with spin-torque sensors. NANOARCH 2013: 40-41 - [i10]Mrigank Sharad, Kaushik Roy:
Spintronic Switches for Ultra Low Energy On-Chip and Inter-Chip Current-Mode Interconnects. CoRR abs/1304.2213 (2013) - [i9]Mrigank Sharad, Deliang Fan, Kaushik Roy:
Ultra Low Power Associative Computing with Spin Neurons and Resistive Crossbar Memory. CoRR abs/1304.2281 (2013) - [i8]Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra:
Exploring Boolean and Non-Boolean Computing Applications of Spin Torque Devices. CoRR abs/1308.2745 (2013) - [i7]Mrigank Sharad, Deliang Fan, Kaushik Roy:
Ultra-low Energy, High Performance and Programmable Magnetic Threshold Logic. CoRR abs/1308.4169 (2013) - [i6]Mrigank Sharad, Deliang Fan, Kaushik Roy:
Ultra-low Energy, High-Performance Dynamic Resistive Threshold Logic. CoRR abs/1308.4672 (2013) - [i5]Mrigank Sharad, Deliang Fan, Kaushik Roy:
Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers. CoRR abs/1309.3303 (2013) - 2012
- [j157]Jangjoon Lee, Srikar Bhagavatula, Swarup Bhunia, Kaushik Roy, Byunghoo Jung:
Self-Healing Design in Deep Scaled CMOS Technologies. J. Circuits Syst. Comput. 21(6) (2012) - [j156]Mrigank Sharad, Sumeet Kumar Gupta, Shriram Raghunathan, Pedro P. Irazoqui, Kaushik Roy:
Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT. ACM J. Emerg. Technol. Comput. Syst. 8(2): 10:1-10:14 (2012) - [j155]Dongsoo Lee, Kaushik Roy:
Viterbi-Based Efficient Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 610-619 (2012) - [j154]Sang Phill Park, Dongsoo Lee, Kaushik Roy:
Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 248-256 (2012) - [j153]Jaydeep P. Kulkarni, Kaushik Roy:
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 319-332 (2012) - [j152]W. Paul Griffin, Anand Raghunathan, Kaushik Roy:
CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 791-803 (2012) - [j151]Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy:
Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems. J. Signal Process. Syst. 68(3): 415-431 (2012) - [c353]Sang Phill Park, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Anand Raghunathan, Kaushik Roy:
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture. DAC 2012: 492-497 - [c352]Swagath Venkataramani, Amit Sabne, Vivek Joy Kozhikkottu, Kaushik Roy, Anand Raghunathan:
SALSA: systematic logic synthesis of approximate circuits. DAC 2012: 796-801 - [c351]Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Cognitive computing with spin-based neural networks. DAC 2012: 1262-1263 - [c350]Georgios Panagopoulos, Charles Augustine, Kaushik Roy:
A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach. DATE 2012: 1443-1446 - [c349]Sumeet Kumar Gupta, Sang Phill Park, Niladri Narayan Mojumder, Kaushik Roy:
Layout-aware optimization of stt mrams. DATE 2012: 1455-1458 - [c348]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD 2012: 431-436 - [c347]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
Functional analysis of circuits under timing variations. ETS 2012: 1 - [c346]Soo Youn Kim, Wing-Fai Loke, Sang Phill Park, Byunghoo Jung, Kaushik Roy:
Poly-Si Thin Film Transistors: Opportunities for low-cost RF applications. ICICDT 2012: 1-4 - [c345]Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Spin based neuron-synapse module for ultra low power programmable computational networks. IJCNN 2012: 1-7 - [c344]Yusung Kim, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy:
Write-optimized reliable design of STT MRAM. ISLPED 2012: 3-8 - [c343]Dongsoo Lee, Sumeet Kumar Gupta, Kaushik Roy:
High-performance low-energy STT MRAM based on balanced write scheme. ISLPED 2012: 9-14 - [c342]Elif S. Mungan, Chao Lu, Vijay Raghunathan, Kaushik Roy:
Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems. ISLPED 2012: 123-128 - [c341]Kaushik Roy:
Spin as state variable for computation: prospects and perspectives. ISLPED 2012: 147-148 - [c340]Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED 2012: 185-190 - [c339]Himanshu Markandeya, Shriram Raghunathan, Pedro P. Irazoqui, Kaushik Roy:
A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability. ISLPED 2012: 285-290 - [c338]Jangjoon Lee, Srikar Bhagavatula, Kaushik Roy, Byunghoo Jung:
Variation-aware and self-healing design methodology for a system-on-chip. LATW 2012: 1-4 - [c337]Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Ultra low energy analog image processing using spin based neurons. NANOARCH 2012: 211-217 - [c336]Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy:
Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems. VLSI Design 2012: 215-220 - [c335]Mayur Bubna, Kaushik Roy, Ashish Goel:
HBIST: An approach towards zero external test cost. VTS 2012: 13-18 - [i4]Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Proposal For Neuromorphic Hardware Using Spin Devices. CoRR abs/1206.3227 (2012) - [i3]Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda:
Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports 2(8): 57-73 (2012) - 2011
- [j150]Georgios Karakonstantis, Abhijit Chatterjee, Kaushik Roy:
Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(1): 19-29 (2011) - [j149]Enrico Macii, Vijaykrishnan Narayanan, Kaushik Roy:
Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 205-207 (2011) - [j148]Chao Lu, Vijay Raghunathan, Kaushik Roy:
Efficient Design of Micro-Scale Energy Harvesting Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 254-266 (2011) - [j147]Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy:
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications. IEEE Trans. Circuits Syst. Video Technol. 21(2): 101-112 (2011) - [j146]Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy:
Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1429-1437 (2011) - [j145]Swaroop Ghosh, Kaushik Roy:
Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1504-1507 (2011) - [j144]Jaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy:
A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1727-1730 (2011) - [c334]Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy:
Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays. ASP-DAC 2011: 695-700 - [c333]Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy:
Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost. Asian Test Symposium 2011: 486-491 - [c332]Georgios Karakonstantis, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Tziantzioulis, Vaibhav Gupta, Kaushik Roy:
Significance driven computation on next-generation unreliable platforms. DAC 2011: 290-291 - [c331]Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
Dynamic effort scaling: managing the quality-efficiency tradeoff. DAC 2011: 603-608 - [c330]Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy:
Stage number optimization for switched capacitor power converters in micro-scale energy harvesting. DATE 2011: 770-775 - [c329]Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy:
Design of voltage-scalable meta-functions for approximate computing. DATE 2011: 950-955 - [c328]Georgios Karakonstantis, Kaushik Roy:
Voltage over-scaling: A cross-layer design perspective for energy efficient systems. ECCTD 2011: 548-551 - [c327]Dongsoo Lee, Kaushik Roy:
Viterbi-Based Efficient Test Data Compression. ETS 2011: 204 - [c326]Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan:
MACACO: Modeling and analysis of circuits for approximate computing. ICCAD 2011: 667-673 - [c325]Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy:
Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. ICCD 2011: 326-331 - [c324]Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy:
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. ISLPED 2011: 303-308 - [c323]Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy:
IMPACT: imprecise adders for low-power approximate computing. ISLPED 2011: 409-414 - [c322]Soo Youn Kim, Selin Baytok, Kaushik Roy:
Scaled LTPS TFTs for low-cost low-power applications. ISQED 2011: 745-750 - [c321]Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan:
Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH 2011: 122-128 - [c320]Charles Augustine, Georgios Panagopoulos, Behtash Behin-Aein, Srikant Srinivasan, Angik Sarkar, Kaushik Roy:
Low-power functionality enhanced computation architecture using spin-based devices. NANOARCH 2011: 129-136 - [c319]Dongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy:
Memory-based embedded digital ATE. VTS 2011: 266-271 - [p2]Georgios Karakonstantis, Kaushik Roy:
Low-Power and Variation-Tolerant Application-Specific System Design. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 249-292 - 2010
- [j143]Ik Joon Chang, Jongsun Park, Kunhyuk Kang, Kaushik Roy:
Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling. IET Circuits Devices Syst. 4(6): 469-478 (2010) - [j142]Ik Joon Chang, Sang Phill Park, Kaushik Roy:
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. IEEE J. Solid State Circuits 45(2): 401-410 (2010) - [j141]Sumeet Kumar Gupta, Arijit Raychowdhury, Kaushik Roy:
Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective. Proc. IEEE 98(2): 160-190 (2010) - [j140]Swaroop Ghosh, Kaushik Roy:
Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era. Proc. IEEE 98(10): 1718-1751 (2010) - [j139]Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy:
Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 2-13 (2010) - [j138]Seung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy:
Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 497-502 (2010) - [j137]Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy:
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 1838-1847 (2010) - [j136]Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 53-65 (2010) - [j135]Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy:
Self-Repairing SRAM Using On-Chip Detection and Compensation. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 75-84 (2010) - [j134]Kunhyuk Kang, Sang Phill Park, Keejong Kim, Kaushik Roy:
On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 270-280 (2010) - [j133]Myeong-Eun Hwang, Kaushik Roy:
ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 281-290 (2010) - [j132]Jongsun Park, Jung Hwan Choi, Kaushik Roy:
Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 787-793 (2010) - [j131]Patrick Ndai, Ashish Goel, Kaushik Roy:
A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1209-1219 (2010) - [j130]Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy:
Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking. IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1301-1309 (2010) - [j129]Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy:
Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing. IEEE Trans. Very Large Scale Integr. Syst. 18(10): 1461-1470 (2010) - [j128]Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy:
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1621-1624 (2010) - [j127]Jing Li, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy:
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1710-1723 (2010) - [j126]Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy:
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. J. Signal Process. Syst. 58(2): 125-137 (2010) - [c318]Chao Lu, Vijay Raghunathan, Kaushik Roy:
Micro-scale energy harvesting: a system design perspective. ASP-DAC 2010: 89-94 - [c317]Jung Hwan Choi, Byung Guk Kim, Aurobindo Dasgupta, Kaushik Roy:
Improved clock-gating control scheme for transparent pipeline. ASP-DAC 2010: 401-406 - [c316]Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy:
Data-dependant sense-amplifier flip-flop for low power applications. CICC 2010: 1-4 - [c315]Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. DAC 2010: 555-560 - [c314]Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy:
Efficient power conversion for ultra low voltage micro scale energy transducers. DATE 2010: 1602-1607 - [c313]Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras:
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. ETS 2010: 69-74 - [c312]Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia:
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. HOST 2010: 13-18 - [c311]Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy:
VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture. ICCD 2010: 260-265 - [c310]Georgios Karakonstantis, Charles Augustine, Kaushik Roy:
A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique. IOLTS 2010: 3-8 - [c309]Chao Lu, Vijay Raghunathan, Kaushik Roy:
Maximum power point considerations in micro-scale solar energy harvesting systems. ISCAS 2010: 273-276 - [c308]Georgios Karakonstantis, Georgios Panagopoulos, Kaushik Roy:
HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs. ISLPED 2010: 117-122 - [c307]Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy:
Analysis and design of ultra low power thermoelectric energy harvesting systems. ISLPED 2010: 183-188 - [c306]Himanshu Markandeya, Georgios Karakonstantis, Shriram Raghunathan, Pedro P. Irazoqui, Kaushik Roy:
Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection. ISLPED 2010: 301-306 - [c305]Mesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy:
Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit. ISSCC 2010: 186-187 - [c304]Kaushik Roy, Byunghoo Jung, Anand Raghunathan:
Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. VLSI Design 2010: 464-469
2000 – 2009
- 2009
- [j125]Sang Phill Park, Kunhyuk Kang, Kaushik Roy:
Reliability Implications of Bias-Temperature Instability in Digital ICs. IEEE Des. Test Comput. 26(6): 8-17 (2009) - [j124]Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. IEEE J. Solid State Circuits 44(2): 650-658 (2009) - [j123]Jing Li, Kunhyuk Kang, Kaushik Roy:
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 46-59 (2009) - [j122]Jung Hwan Choi, Nilanjan Banerjee, Kaushik Roy:
Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 87-97 (2009) - [j121]Nilanjan Banerjee, Georgios Karakonstantis, Jung Hwan Choi, Chaitali Chakrabarti, Kaushik Roy:
Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1127-1137 (2009) - [j120]Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy:
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(7): 1428-1441 (2009) - [j119]Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy:
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 33-44 (2009) - [j118]Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Trans. Very Large Scale Integr. Syst. 17(12): 1749-1752 (2009) - [c303]Mesut Meterelliyoz, Kaushik Roy:
Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations. ASP-DAC 2009: 787-792 - [c302]Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy:
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. ASP-DAC 2009: 841-846 - [c301]Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy:
A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. ASP-DAC 2009: 847-852 - [c300]Ashish Goel, Patrick Ndai, Jaydeep P. Kulkarni, Kaushik Roy:
REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN. CICC 2009: 503-506 - [c299]Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta:
Device/circuit interactions at 22nm technology node. DAC 2009: 97-102 - [c298]Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy:
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. DAC 2009: 670-675 - [c297]Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy:
Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator. ISLPED 2009: 195-200 - [c296]Kaushik Roy:
Ultra low voltage CMOS. ISLPED 2009: 425-426 - [c295]Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy:
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. ISQED 2009: 80-85 - [c294]Bhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d'Abreu:
Impact of SoC power management techniques on verification and testing. ISQED 2009: 692-695 - [c293]Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy:
System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning. SiPS 2009: 133-138 - [c292]Kaushik Roy:
Design in the nano-scale Era: Low-power, reliability, and error resiliency. SoCC 2009: 445 - [c291]Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy:
Coping with Variations through System-Level Design. VLSI Design 2009: 581-586 - 2008
- [j117]Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy:
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electron. Test. 24(6): 577-590 (2008) - [j116]Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy:
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. ACM J. Emerg. Technol. Comput. Syst. 4(3): 13:1-13:19 (2008) - [j115]Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
A Low-Power SRAM Using Bit-Line Charge-Recycling. IEEE J. Solid State Circuits 43(2): 446-459 (2008) - [j114]Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy:
An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process. IEEE J. Solid State Circuits 43(9): 1951-1963 (2008) - [j113]Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy:
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput. IEEE Trans. Computers 57(7): 940-951 (2008) - [j112]Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 174-183 (2008) - [j111]Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy:
Profit Aware Circuit Design Under Process Variations Considering Speed Binning. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 806-815 (2008) - [j110]Jongsun Park, Kaushik Roy:
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption. J. Signal Process. Syst. 53(3): 399-410 (2008) - [c290]Swaroop Ghosh, Kaushik Roy:
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. ASP-DAC 2008: 635-640 - [c289]Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy:
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? ASP-DAC 2008: 726-731 - [c288]Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy:
A high sensitivity process variation sensor utilizing sub-threshold operation. CICC 2008: 125-128 - [c287]Jing Li, Haixin Liu, Sayeef S. Salahuddin, Kaushik Roy:
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. CICC 2008: 193-196 - [c286]Myeong-Eun Hwang, Kaushik Roy:
A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology. CICC 2008: 419-422 - [c285]Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy:
Process variation tolerant SRAM array for ultra low voltage applications. DAC 2008: 108-113 - [c284]Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy:
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. DAC 2008: 278-283 - [c283]Swaroop Ghosh, Patrick Ndai, Kaushik Roy:
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. DATE 2008: 366-371 - [c282]Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen:
Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008 - [c281]Dimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia N. Sanda:
Soft Errors: System Effects, Protection Techniques and Case Studies. DATE 2008 - [c280]Nilanjan Banerjee, Charles Augustine, Kaushik Roy:
Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. DFT 2008: 323-331 - [c279]Bhanu Kapoor, John Goodenough, Shankar Hemmady, Shireesh Verma, Manuel A. d'Abreu, Kaushik Roy:
Panel: SoC power management implications on validation and testing. HLDVT 2008: 135-137 - [c278]Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy:
Thermal analysis of 8-T SRAM for nano-scaled technologies. ISLPED 2008: 123-128 - [c277]Swarup Bhunia, Kaushik Roy:
Low power design under parameter variations. ISLPED 2008: 137-138 - [c276]Swaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy:
O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors. ISLPED 2008: 189-192 - [c275]Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS. ISSCC 2008: 388-389 - [c274]Bhanu Kapoor, J. Marc Edwards, Shankar Hemmady, Shireesh Verma, Kaushik Roy:
Tutorial: SoC Power Management Verification and Testing Issues. MTV 2008: 67-72 - [c273]Swarup Bhunia, Kaushik Roy:
Low power design under parameter variations. SoCC 2008: 389-390 - [c272]Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy:
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130 - [c271]Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy:
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS 2008: 101-106 - 2007
- [j109]Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy:
Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders. IEICE Trans. Electron. 90-C(4): 865-876 (2007) - [j108]Nilanjan Banerjee, Kaushik Roy:
Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing. J. Low Power Electron. 3(3): 254-270 (2007) - [j107]Saibal Mukhopadhyay, Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS. IEEE J. Solid State Circuits 42(6): 1370-1382 (2007) - [j106]Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy:
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM. IEEE J. Solid State Circuits 42(10): 2303-2313 (2007) - [j105]Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy:
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectron. J. 38(8-9): 931-941 (2007) - [j104]Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 743-751 (2007) - [j103]Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, Muhammad Ashraful Alam:
Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1770-1781 (2007) - [j102]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1947-1956 (2007) - [j101]Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, Dheepa Lekshmanan, Kaushik Roy:
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1957-1966 (2007) - [j100]Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy:
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2059-2068 (2007) - [j99]Hiroaki Suzuki, Chris H. Kim, Kaushik Roy:
Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(2): 322-328 (2007) - [j98]Clifford Lau, Alex Orailoglu, Kaushik Roy:
Guest Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2342-2344 (2007) - [j97]Arijit Raychowdhury, Kaushik Roy:
Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2391-2401 (2007) - [j96]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Low-Power and testable circuit synthesis using Shannon decomposition. ACM Trans. Design Autom. Electr. Syst. 12(4): 47 (2007) - [j95]Yongtao Wang, Khurram Muhammad, Kaushik Roy:
Design of Sigma-Delta Modulators With Arbitrary Transfer Functions. IEEE Trans. Signal Process. 55(2): 677-683 (2007) - [j94]Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy:
Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 660-671 (2007) - [c270]Dheepa Lekshmanan, Aditya Bansal, Kaushik Roy:
FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area. CICC 2007: 623-626 - [c269]Swaroop Ghosh, Pooja Batra, Keejong Kim, Kaushik Roy:
Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd. CICC 2007: 733-736 - [c268]Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy:
High Performance and Low Power Electronics on Flexible Substrate. DAC 2007: 274-275 - [c267]Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy:
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. DAC 2007: 358-363 - [c266]Kunhyuk Kang, Keejong Kim, Kaushik Roy:
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop. DAC 2007: 934-939 - [c265]Nilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy:
Process variation tolerant low power DCT architecture. DATE 2007: 630-635 - [c264]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. DATE 2007: 1532-1537 - [c263]Myeong-Eun Hwang, Tamer Cakici, Kaushik Roy:
Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling. DATE 2007: 1550-1555 - [c262]Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy:
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. DDECS 2007: 69-74 - [c261]Amit Agarwal, Nilanjan Banerjee, Steven K. Hsu, Ram K. Krishnamurthy, Kaushik Roy:
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS. ESSCIRC 2007: 316-319 - [c260]Georgios Karakonstantis, Kaushik Roy:
An Optimal Algorithm for Low Power Multiplierless FIR Filter Design using Chebychev Criterion. ICASSP (2) 2007: 49-52 - [c259]Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti:
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. ICCAD 2007: 199-204 - [c258]Kunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam:
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. ICCAD 2007: 730-734 - [c257]Jung Hwan Choi, Jayathi Murthy, Kaushik Roy:
The effect of process variation on device temperature in FinFET circuits. ICCAD 2007: 747-751 - [c256]Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy:
Tolerance to Small Delay Defects by Adaptive Clock Stretching. IOLTS 2007: 244-252 - [c255]Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy:
Low-power process-variation tolerant arithmetic units using input-based elastic clocking. ISLPED 2007: 74-79 - [c254]Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy:
A process variation aware low power synthesis methodology for fixed-point FIR filters. ISLPED 2007: 147-152 - [c253]Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy:
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. ISLPED 2007: 171-176 - [c252]Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
A low-power SRAM using bit-line charge-recycling technique. ISLPED 2007: 177-182 - [c251]Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy:
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. ISLPED 2007: 387-390 - [c250]Tamer Cakici, Keejong Kim, Kaushik Roy:
FinFET Based SRAM Design for Low Standby Power Applications. ISQED 2007: 127-132 - [c249]Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy:
Fine-Grained Redundancy in Adders. ISQED 2007: 317-321 - [c248]Jaydeep P. Kulkarni, Kaushik Roy:
A High Performance, Scalable Multiplexed Keeper Technique. ISQED 2007: 545-549 - [c247]Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy:
Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure. ISSCC 2007: 400-611 - [c246]Swarup Bhunia, Kaushik Roy:
Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions. ITC 2007: 1-10 - [c245]Kunhyuk Kang, Muhammad Ashraful Alam, Kaushik Roy:
Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ. ITC 2007: 1-10 - [c244]Jing Li, Swaroop Ghosh, Kaushik Roy:
A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs. ITC 2007: 1-10 - [c243]Qikai Chen, Arjun Guha, Kaushik Roy:
An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. VLSI Design 2007: 615-620 - [c242]Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy:
Process Variations and Process-Tolerant Design. VLSI Design 2007: 699-704 - [i2]Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy:
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. CoRR abs/0710.4663 (2007) - [i1]Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy:
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. CoRR abs/0710.4729 (2007) - 2006
- [j93]Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng:
Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Des. Test Comput. 23(2): 128-136 (2006) - [j92]Bipul C. Paul, Kaushik Roy:
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. J. Electron. Test. 22(2): 115-124 (2006) - [j91]Kaushik Roy:
Guest Editorial. Integr. 39(2): 63 (2006) - [j90]Bipul Chandra Paul, Amit Agarwal, Kaushik Roy:
Low-power design techniques for scaled technologies. Integr. 39(2): 64-89 (2006) - [j89]Chris Hyung-Il Kim, Jae-Joon Kim, Ik-Joon Chang, Kaushik Roy:
PVT-aware leakage reduction for on-die caches with improved read stability. IEEE J. Solid State Circuits 41(1): 170-178 (2006) - [j88]Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim:
Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro 26(2): 68-80 (2006) - [j87]Arijit Raychowdhury, Kaushik Roy:
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 58-65 (2006) - [j86]Jongsun Park, Khurram Muhammad, Kaushik Roy:
Efficient modeling of 1/falpha/ noise using multirate process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1247-1256 (2006) - [j85]Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy:
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1486-1495 (2006) - [j84]Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy:
Modeling and Analysis of Leakage Currents in Double-Gate Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2052-2061 (2006) - [j83]Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy:
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2427-2436 (2006) - [j82]Aditya Bansal, Bipul Chandra Paul, Kaushik Roy:
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2765-2774 (2006) - [j81]Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2934-2943 (2006) - [j80]Kunhyuk Kang, Bipul C. Paul, Kaushik Roy:
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. ACM Trans. Design Autom. Electr. Syst. 11(4): 848-879 (2006) - [j79]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 183-192 (2006) - [j78]Dongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy:
Layout-driven architecture synthesis for high-speed digital filters. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 203-207 (2006) - [j77]Jae-Joon Kim, Kaushik Roy:
A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 549-552 (2006) - [j76]Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 646-649 (2006) - [j75]Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 1034-1039 (2006) - [j74]Mark M. Budnik, Kaushik Roy:
A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1336-1346 (2006) - [c241]Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163 - [c240]Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy:
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. ASP-DAC 2006: 237-242 - [c239]Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy:
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC 2006: 665-670 - [c238]Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy:
Speed binning aware design methodology to improve profit under parameter variations. ASP-DAC 2006: 712-717 - [c237]Saakshi Gangwal, Saibal Mukhopadhyay, Kaushik Roy:
Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM. CICC 2006: 433-436 - [c236]Arijit Raychowdhury, Jeong-Il Kim, Dimitrios Peroulis, Kaushik Roy:
Integrated MEMS Switches for Leakage Control of Battery Operated Systems. CICC 2006: 457-460 - [c235]Saibal Mukhopadhyay, Amit Agarwal, Qikai Chen, Kaushik Roy:
SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design. CICC 2006: 547-554 - [c234]Hari Ananthan, Kaushik Roy:
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. DAC 2006: 413-418 - [c233]Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy:
A high density, carbon nanotube capacitor for decoupling applications. DAC 2006: 935-938 - [c232]Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy:
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. DAC 2006: 971-976 - [c231]Jongsun Park, Jung Hwan Choi, Kaushik Roy:
Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. DATE 2006: 520-521 - [c230]Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. DATE 2006: 780-785 - [c229]Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy:
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. DATE 2006: 856-861 - [c228]Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia:
Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867 - [c227]Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy:
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. DATE 2006: 983-988 - [c226]Mark M. Budnik, Kaushik Roy:
Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network. DATE 2006: 1116-1121 - [c225]Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy:
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. ICCAD 2006: 583-586 - [c224]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. ICCAD 2006: 619-624 - [c223]Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. ICCD 2006: 216-221 - [c222]Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. IOLTS 2006: 31-36 - [c221]Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy:
Analysis of super cut-off transistors for ultralow power digital logic circuits. ISLPED 2006: 2-7 - [c220]Ik Joon Chang, Jae-Joon Kim, Kaushik Roy:
Robust level converter design for sub-threshold logic. ISLPED 2006: 14-19 - [c219]Qikai Chen, Mesut Meterelliyoz, Kaushik Roy:
A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design. ISQED 2006: 243-248 - [c218]Mark M. Budnik, Kaushik Roy:
Minimizing Ohmic Loss in Future Processor IR Events. ISQED 2006: 650-658 - [c217]Kaushik Roy:
Process Variation: Its Impact on the Design and Test of CMOS Circuits. LATW 2006: 123 - [c216]Saibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim, Kaushik Roy:
Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies. SoCC 2006: 155-159 - [c215]Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici:
Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452 - 2005
- [j73]Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. J. Electron. Test. 21(2): 147-159 (2005) - [j72]Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. J. Electron. Test. 21(3): 243-255 (2005) - [j71]Woopyo Jeong, Kaushik Roy:
High-performance low-power dual transition preferentially sized (DTPS) logic. IEEE J. Solid State Circuits 40(2): 480-484 (2005) - [j70]Hamid Mahmoodi, Saibal Mukhopadhyay, Kaushik Roy:
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits. IEEE J. Solid State Circuits 40(9): 1787-1796 (2005) - [j69]Amit Agarwal, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy:
Process variation in embedded memories: failure analysis and variation aware architecture. IEEE J. Solid State Circuits 40(9): 1804-1814 (2005) - [j68]Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy:
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. IEEE Trans. Computers 54(6): 752-766 (2005) - [j67]Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy:
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 363-381 (2005) - [j66]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1859-1880 (2005) - [j65]Yongtao Wang, Kaushik Roy:
CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(9): 1845-1853 (2005) - [j64]Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy:
Synthesis of application-specific highly efficient multi-mode cores for embedded systems. ACM Trans. Embed. Comput. Syst. 4(1): 168-188 (2005) - [j63]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005) - [j62]Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy:
A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 27-38 (2005) - [j61]Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 75-85 (2005) - [j60]Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 349-357 (2005) - [j59]Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy:
Low-power scan design using first-level supply gating. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 384-395 (2005) - [j58]Swarup Bhunia, Kaushik Roy:
A novel wavelet transform-based transient current analysis for fault detection and localization. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 503-507 (2005) - [j57]Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar:
Combined circuit and architectural level variable supply-voltage scaling for low power. IEEE Trans. Very Large Scale Integr. Syst. 13(5): 564-576 (2005) - [j56]Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy:
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1213-1224 (2005) - [j55]Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy:
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1286-1295 (2005) - [c214]Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy:
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Asian Test Symposium 2005: 170-175 - [c213]Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy:
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium 2005: 176-181 - [c212]Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Asian Test Symposium 2005: 404-409 - [c211]Ik Joon Chang, Kunhyuk Kang, Saibal Mukhopadhyay, Chris H. Kim, Kaushik Roy:
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling. CICC 2005: 439-442 - [c210]Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies. CICC 2005: 775-778 - [c209]Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC 2005: 479-484 - [c208]Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy:
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. DATE 2005: 224-229 - [c207]Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy:
Statistical Timing Analysis using Levelized Covariance Propagation. DATE 2005: 764-769 - [c206]Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy:
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. DATE 2005: 926-931 - [c205]Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy:
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE 2005: 1136-1141 - [c204]Arijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy:
A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points. ETS 2005: 108-113 - [c203]Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy:
Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI 2005: 468-471 - [c202]Yongtao Wang, Khurram Muhammad, Kaushik Roy:
Design of sigma-delta modulators with arbitrary transfer functions. ICASSP (5) 2005: 53-56 - [c201]Hunsoo Choo, Kaushik Roy:
Joint control of communication subsystems for low-energy image transmission. ICASSP (3) 2005: 529-532 - [c200]Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici:
Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224 - [c199]Amit Agarwal, Kunhyuk Kang, Kaushik Roy:
Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. ICCAD 2005: 736-741 - [c198]Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy:
A Soft Error Monitor Using Switching Current Detection. ICCD 2005: 185-192 - [c197]Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD 2005: 206-214 - [c196]Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy:
A Feasibility Study of Subthreshold SRAM Across Technology Generations. ICCD 2005: 417-424 - [c195]Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy:
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105 - [c194]Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
Process Variation Tolerant Online Current Monitor for Robust Systems. IOLTS 2005: 171-176 - [c193]Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy:
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. IOLTS 2005: 275-280 - [c192]Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy:
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. IOLTS 2005: 287-292 - [c191]Aditya Bansal, Kaushik Roy:
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. ISCAS (1) 2005: 1-4 - [c190]Yongtao Wang, Kaushik Roy:
A novel low-complexity method for parallel multiplierless implementation of digital FIR filters. ISCAS (3) 2005: 2020-2023 - [c189]Yongtao Wang, Kaushik Roy:
A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems. ISCAS (5) 2005: 4963-4966 - [c188]Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy:
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. ISLPED 2005: 8-13 - [c187]Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy:
Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. ISLPED 2005: 14-19 - [c186]Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Borkar:
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED 2005: 103-106 - [c185]Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ISLPED 2005: 115-118 - [c184]Dongku Kang, Yiran Chen, Kaushik Roy:
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. ISQED 2005: 48-53 - [c183]Keejong Kim, Chris H. Kim, Kaushik Roy:
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. ISQED 2005: 59-64 - [c182]Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy:
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. ISQED 2005: 358-363 - [c181]Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy:
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415 - [c180]Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy:
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458 - [c179]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED 2005: 490-495 - [c178]Mesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy:
A leakage control system for thermal stability during burn-in test. ITC 2005: 10 - [c177]Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy:
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring. ITC 2005: 10 - [c176]Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy:
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS 2005: 292-297 - [e4]Kaushik Roy, Vivek Tiwari:
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005. ACM 2005, ISBN 1-59593-137-6 [contents] - 2004
- [j54]Naran Sirisantana, Kaushik Roy:
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. IEEE Des. Test Comput. 21(1): 56-63 (2004) - [j53]Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy:
Enhancing Yield at the End of the Technology Roadmap. IEEE Des. Test Comput. 21(6): 563-571 (2004) - [j52]Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy:
Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid State Circuits 39(2): 348-357 (2004) - [j51]Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy:
A circuit-compatible model of ballistic carbon nanotube field-effect transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10): 1411-1420 (2004) - [j50]Hamid Mahmoodi-Meimand, Kaushik Roy:
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(3): 495-503 (2004) - [j49]Hunsoo Choo, Khurram Muhammad, Kaushik Roy:
Complexity reduction of digital filters using shift inclusive differential coefficients. IEEE Trans. Signal Process. 52(6): 1760-1772 (2004) - [j48]Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar:
DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 245-254 (2004) - [c175]Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy:
Adaptive supply voltage technique for low swing interconnects. ASP-DAC 2004: 284-287 - [c174]Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898 - [c173]Cheng-Yi Chen, Soonkeon Kwon, Kaushik Roy:
Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array. Communications in Computing 2004: 167-176 - [c172]Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Kaushik Roy:
Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits. CICC 2004: 17-20 - [c171]Amit Agarwal, Bipul C. Paul, Kaushik Roy:
Process variation in nano-scale memories: failure analysis and process tolerant architecture. CICC 2004: 353-356 - [c170]Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy:
Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC 2004: 6-11 - [c169]Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy:
Novel sizing algorithm for yield improvement under process variation in nanometer technology. DAC 2004: 454-459 - [c168]Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. DATE 2004: 704-705 - [c167]Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy:
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT 2004: 314-315 - [c166]Jongsun Park, Kaushik Roy:
A low power reconfigurable DCT architecture to trade off image quality for computational complexity. ICASSP (5) 2004: 17-20 - [c165]Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy:
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. ICASSP (5) 2004: 97-100 - [c164]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Statistical design and optimization of SRAM cell for yield enhancement. ICCAD 2004: 10-13 - [c163]Arijit Raychowdhury, Kaushik Roy:
A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies. ICCAD 2004: 237-240 - [c162]Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy:
A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65 - [c161]Dongku Kang, Hunsoo Choo, Kaushik Roy:
Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed. ICCD 2004: 354-357 - [c160]Xiaowei Ding, Kaushik Roy:
A Novel Bitstream Level Joint Channel Error Concealment Scheme for Realtime Video over Wireless Networks. INFOCOM 2004: 2163-2173 - [c159]Amit Agarwal, Bipul Chandra Paul, Kaushik Roy:
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. IOLTS 2004: 149-154 - [c158]Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy:
A Technique to Reduce Power and Test Application Time in BIST. IOLTS 2004: 182-183 - [c157]Hamid Mahmoodi-Meimand, Kaushik Roy:
Dual-edge triggered level converting flip-flops. ISCAS (2) 2004: 661-664 - [c156]Hamid Mahmoodi-Meimand, Kaushik Roy:
Data-retention flip-flops for power-down applications. ISCAS (2) 2004: 677-680 - [c155]Myeong-Eun Hwang, Arijit Raychowdhury, Kaushik Roy:
Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies. ISCAS (3) 2004: 709-712 - [c154]Hari Ananthan, Chris H. Kim, Kaushik Roy:
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ISLPED 2004: 8-13 - [c153]Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy:
Device optimization for ultra-low power digital sub-threshold operation. ISLPED 2004: 96-101 - [c152]Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy:
Low-power carry-select adder using adaptive supply voltage based on input vector patterns. ISLPED 2004: 313-318 - [c151]Arijit Raychowdhury, Kaushik Roy:
A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. ISMVL 2004: 14-19 - [c150]Kaushik Roy:
Low-Power Design. ISQED 2004: 8 - [c149]Dongku Kang, Mark C. Johnson, Kaushik Roy:
Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan. ISQED 2004: 98-103 - [c148]Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. ISQED 2004: 389-394 - [c147]Hari Ananthan, Aditya Bansal, Kaushik Roy:
FinFET SRAM - Device and Circuit Design Considerations. ISQED 2004: 511-516 - [c146]Bipul Chandra Paul, Cassondra Neau, Kaushik Roy:
Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. ITC 2004: 1269-1275 - [c145]Amit Agarwal, Kaushik Roy, Ram K. Krishnamurthy:
A leakage-tolerant low-leakage register file with conditional sleep transistor. SoCC 2004: 241-244 - [c144]Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy:
Modeling and Estimation of Leakage in Sub-90nm Devices. VLSI Design 2004: 65- - [e3]Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy:
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004. ACM 2004 [contents] - 2003
- [j47]Amit Agarwal, Hai Li, Kaushik Roy:
A single-Vt low-leakage gated-ground cache for deep submicron. IEEE J. Solid State Circuits 38(2): 319-328 (2003) - [j46]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
On-chip interconnect modeling by wire duplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1521-1532 (2003) - [j45]Hunsoo Choo, Khurram Muhammad, Kaushik Roy:
Two's complement computation sharing multiplier and its applications to high performance DFE. IEEE Trans. Signal Process. 51(2): 458-469 (2003) - [j44]Jongsun Park, Khurram Muhammad, Kaushik Roy:
High-performance FIR filter design based on sharing multiplication. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 244-253 (2003) - [j43]Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy:
Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 716-730 (2003) - [j42]Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 863-870 (2003) - [j41]Chris Hyung-Il Kim, Hendrawan Soeleman, Kaushik Roy:
Ultra-low-power DLMS adaptive filter for hearing aid applications. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1058-1067 (2003) - [c143]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
A metric for analyzing effective on-chip inductive coupling. ASP-DAC 2003: 156-161 - [c142]Woopyo Jeong, Kaushik Roy:
Robust high-performance low-power carry select adder. ASP-DAC 2003: 503-506 - [c141]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Integer linear programming-based synthesis of skewed logic circuits. ASP-DAC 2003: 820-823 - [c140]Jongsun Park, Khurram Muhammad, Kaushik Roy:
Efficient generation of 1/fα noise using a multi-rate filter bank. CICC 2003: 707-710 - [c139]Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy:
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. DAC 2003: 169-174 - [c138]Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy:
An adaptive window-based susceptance extraction and its efficient implementation. DAC 2003: 728-731 - [c137]Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy:
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. DATE 2003: 10096-10103 - [c136]Hunsoo Choo, Khurram Muhammad, Kaushik Roy:
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters. DATE 2003: 10700-10705 - [c135]Amit Agarwal, Kaushik Roy, T. N. Vijaykumar:
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. DATE 2003: 10778-10783 - [c134]Seung Hoon Choi, Kaushik Roy:
A New Crosstalk Noise Model for DOMINO Logic Circuits. DATE 2003: 11112-11113 - [c133]Naran Sirisantana, Kaushik Roy:
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. DATE 2003: 11160-11161 - [c132]Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy:
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. DFT 2003: 191-198 - [c131]Naran Sirisantana, Kaushik Roy:
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies. ESSCIRC 2003: 181-184 - [c130]Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy:
Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-122 - [c129]Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy:
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. ICCAD 2003: 487-490 - [c128]Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy:
Low Power Adder with Adaptive Supply Voltage. ICCD 2003: 103-106 - [c127]Dongku Kang, Mark C. Johnson, Kaushik Roy:
Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. ICCD 2003: 412-418 - [c126]Yonghee Im, Kaushik Roy:
A logic-aware layout methodology to enhance the noise immunity of domino circuits. ISCAS (5) 2003: 637-640 - [c125]Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED 2003: 6-9 - [c124]Amit Agarwal, Kaushik Roy:
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. ISLPED 2003: 18-21 - [c123]Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy:
Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED 2003: 54-59 - [c122]Cassondra Neau, Kaushik Roy:
Optimal body bias selection for leakage improvement and process compensation over different technology generations. ISLPED 2003: 116-121 - [c121]Saibal Mukhopadhyay, Kaushik Roy:
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. ISLPED 2003: 172-175 - [c120]Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234 - [c119]Yonghee Im, Kaushik Roy:
LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits. ISVLSI 2003: 45-54 - [c118]Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy:
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. MICRO 2003: 19-28 - [c117]Rajiv V. Joshi, Kaushik Roy:
Design of Deep Sub-Micron CMOS Circuits. VLSI Design 2003: 15-16 - [c116]Kaushik Roy, T. M. Mak, Kwang-Ting Cheng:
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS 2003: 313-318 - [p1]Amit Agarwal, Kaushik Roy, T. N. Vijaykumar:
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. Embedded Software for SoC 2003: 345-358 - 2002
- [j40]Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy:
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. IEEE Des. Test Comput. 19(2): 24-33 (2002) - [j39]Ali Keshavarzi, James W. Tschanz, Siva G. Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Des. Test Comput. 19(5): 36-43 (2002) - [j38]Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand:
Leakage Current in Deep-Submicron CMOS Circuits. J. Circuits Syst. Comput. 11(6): 575-600 (2002) - [j37]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 81-92 (2002) - [j36]Khurram Muhammad, Kaushik Roy:
A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 204-216 (2002) - [j35]Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy:
Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. Very Large Scale Integr. Syst. 10(1): 1-5 (2002) - [j34]Yonghee Im, Kaushik Roy:
O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 221-229 (2002) - [j33]Khurram Muhammad, Kaushik Roy:
Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 292-300 (2002) - [j32]Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes:
Vertically integrated SOI circuits for low-power and high-performance applications. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 351-362 (2002) - [j31]Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy:
Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 469-476 (2002) - [c115]Swarup Bhunia, Hai Li, Kaushik Roy:
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. Asian Test Symposium 2002: 157- - [c114]Swarup Bhunia, Kaushik Roy, Jaume Segura:
A novel wavelet transform based transient current analysis for fault detection and localization. DAC 2002: 361-366 - [c113]Amit Agarwal, Hai Li, Kaushik Roy:
DRG-cache: a data retention gated-ground cache for low power. DAC 2002: 473-478 - [c112]Seung Hoon Choi, Kaushik Roy, Florentin Dartu:
Timed pattern generation for noise-on-delay calculation. DAC 2002: 870-873 - [c111]Chris H. Kim, Kaushik Roy:
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. DATE 2002: 163-167 - [c110]Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy:
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-935 - [c109]Swarup Bhunia, Kaushik Roy:
Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. DATE 2002: 1118 - [c108]Seung Hoon Choi, Kaushik Roy:
Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits. DELTA 2002: 365-369 - [c107]Jongsun Park, Soonkeon Kwon, Kaushik Roy:
Low power reconfigurable DCT design based on sharing multiplication. ICASSP 2002: 3116-3119 - [c106]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
On-chip interconnect modeling by wire duplication. ICCAD 2002: 341-346 - [c105]Chris H. Kim, Kaushik Roy:
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. ISLPED 2002: 251-254 - [c104]Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy:
High performance and low power FIR filter design based on sharing multiplication. ISLPED 2002: 295-300 - [c103]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234 - [c102]Bipul Chandra Paul, Kaushik Roy:
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. ITC 2002: 384-390 - [c101]Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy:
IDDQ Testing for Deep Submicron ICs: Challenges and Solutions. LATW 2002: 186-192 - [c100]Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy:
Dynamic Noise Analysis with Capacitive and Inductive Coupling. ASP-DAC/VLSI Design 2002: 65-70 - [c99]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. ASP-DAC/VLSI Design 2002: 489- - [c98]Swarup Bhunia, Kaushik Roy:
Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. VTS 2002: 302-310 - 2001
- [j30]Khurram Muhammad, Kaushik Roy:
Fault Detection and Location Using IDD Waveform Analysis. IEEE Des. Test Comput. 18(1): 42-49 (2001) - [j29]Yibin Ye, Kaushik Roy:
QSERL: quasi-static energy recovery logic. IEEE J. Solid State Circuits 36(2): 239-248 (2001) - [j28]Magnus Lundberg, Khurram Muhammad, Kaushik Roy, Sarah Kate Wilson:
A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis. IEEE Trans. Signal Process. 49(12): 3157-3167 (2001) - [j27]Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar:
Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 77-89 (2001) - [j26]Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
Robust subthreshold logic for ultra-low power operation. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 90-99 (2001) - [j25]Zhanping Chen, Liqiong Wei, Kaushik Roy:
On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 718-725 (2001) - [j24]Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy:
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications. VLSI Design 12(2): 233-243 (2001) - [c97]Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy:
Design Verification and Robust Design Technique for Cross-Talk Faults. Asian Test Symposium 2001: 449- - [c96]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. DAC 2001: 846-851 - [c95]Cassondra Neau, Khurram Muhammad, Kaushik Roy:
Low complexity FIR filters using factorization of perturbed coefficients. DATE 2001: 268-272 - [c94]Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar:
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. HPCA 2001: 147-157 - [c93]Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy:
DSP data path synthesis for low-power applications. ICASSP 2001: 1165-1168 - [c92]Hunsoo Choo, Khurram Muhammad, Kaushik Roy:
Decision feedback equalizer with two's complement computation sharing multiplication. ICASSP 2001: 1245-1248 - [c91]Yonghee Im, Kaushik Roy:
CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic. ICCAD 2001: 337- - [c90]Xiaodong Zhang, Kaushik Roy:
Power Constrained Test Scheduling with Low Power Weighted Random Testing. IOLTW 2001: 136 - [c89]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power trends and performance characterization of 3-dimensional integration. ISCAS (4) 2001: 414-417 - [c88]Rui Wang, Kaushik Roy, Cheng-Kok Koh:
Short-circuit power analysis of an inverter driving an RLC load. ISCAS (4) 2001: 886-889 - [c87]Rongtian Zhang, Kaushik Roy, David B. Janes:
Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design. ISLPED 2001: 213-218 - [c86]Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy:
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270 - [c85]Chris Hyung-Il Kim, Kaushik Roy:
Ultra-low power DLMS adaptive filter for hearing aid applications. ISLPED 2001: 352-357 - [c84]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Decoupling capacitance allocation for power supply noise suppression. ISPD 2001: 66-71 - [c83]Kaushik Roy, Ali Keshavarzi:
Design and Test of Low Voltage CMOS Circuits. ISQED 2001: 7 - [c82]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. ISQED 2001: 217-222 - [c81]Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy:
Reducing set-associative cache energy via way-prediction and selective direct-mapping. MICRO 2001: 54-65 - [c80]Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. VLSI Design 2001: 211-214 - [e2]Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh:
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001. ACM 2001, ISBN 1-58113-351-0 [contents] - 2000
- [b1]Kaushik Roy, Sharat Prasad:
Low-Power CMOS VLSI Circuit Design. Wiley 2000, ISBN 978-0-471-11488-8, pp. I-XV, 1-359 - [j23]Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou:
Estimating Circuit Activity in Combinational CMOS Digital Circuits. IEEE Des. Test Comput. 17(2): 112-119 (2000) - [j22]Zhanping Chen, Kaushik Roy, Edwin K. P. Chong:
Estimation of power dissipation using a novel power macromodelingtechnique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1363-1369 (2000) - [j21]Xiaodong Zhang, Wenlei Shan, Kaushik Roy:
Low-power weighted random pattern testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1389-1398 (2000) - [j20]Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins:
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 717-723 (2000) - [c79]Liqiong Wei, Kaushik Roy, Cheng-Kok Koh:
Power minimization by simultaneous dual-Vth assignment and gate-sizing. CICC 2000: 413-416 - [c78]Yonghee Im, Kaushik Roy:
A novel high-performance predictable circuit architecture for the deep sub-micron era. CICC 2000: 503-506 - [c77]Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy:
Test challenges for deep sub-micron technologies. DAC 2000: 142-149 - [c76]Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De:
Dynamic noise analysis in precharge-evaluate circuits. DAC 2000: 243 - [c75]Hendrawan Soeleman, Kaushik Roy:
Digital CMOS logic operation in the sub-threshold region. ACM Great Lakes Symposium on VLSI 2000: 107-112 - [c74]Jongsun Park, Hunsoo Choo, Khurram Muhammad, Seung Hoon Choi, Yonghee Im, Kaushik Roy:
Non-adaptive and adaptive filter implementation based on sharing multiplication. ICASSP 2000: 460-463 - [c73]Khurram Muhammad, Kaushik Roy:
Minimally redundant parallel implementation of digital filters and vector scaling. ICASSP 2000: 3295-3298 - [c72]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. ICCAD 2000: 208-213 - [c71]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. ICCAD 2000: 406-411 - [c70]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Frequency Domain Analysis of Switching Noise on Power Supply Network. ICCAD 2000: 487-492 - [c69]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. ICCD 2000: 65-72 - [c68]Naran Sirisantana, Liqiong Wei, Kaushik Roy:
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. ICCD 2000: 227-232 - [c67]Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar:
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD 2000: 241-246 - [c66]Xiaodong Zhang, Kaushik Roy:
Power Reduction in Test-Per-Scan BIST. IOLTW 2000: 133- - [c65]Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
Robust ultra-low power sub-threshold DTMOS logic. ISLPED 2000: 25-30 - [c64]Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar:
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories. ISLPED 2000: 90-95 - [c63]Zhanping Chen, Liqiong Wei, Kaushik Roy:
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. ISQED 2000: 181-188 - [c62]Xiaodong Zhang, Kaushik Roy:
Peak Power Reduction in Low Power BIST. ISQED 2000: 425-432 - [c61]Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. ITC 2000: 1051-1059 - [c60]Kaushik Roy, Khurram Muhammad:
Low Power VLSI Signal Processing. VLSI Design 2000: 12 - [c59]Liqiong Wei, Kaushik Roy, Vivek De:
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. VLSI Design 2000: 24-29 - [c58]Shiyou Zhao, Kaushik Roy:
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits. VLSI Design 2000: 168- - [e1]Majid Sarrafzadeh, Prithviraj Banerjee, Kaushik Roy:
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000. ACM 2000, ISBN 1-58113-251-4 [contents]
1990 – 1999
- 1999
- [j19]Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy:
Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 714-725 (1999) - [j18]Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De:
Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 16-24 (1999) - [c57]Yibin Ye, Kaushik Roy, Rolf Drechsler:
Power Consumption in XOR-Based Circuits. ASP-DAC 1999: 299-302 - [c56]Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De:
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC 1999: 430-435 - [c55]Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy:
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. DAC 1999: 442-445 - [c54]Xiaodong Zhang, Kaushik Roy:
Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. DFT 1999: 148- - [c53]Magnus Lundberg, Khurram Muhammad, Kaushik Roy, Sarah Kate Wilson:
High-level modeling of switching activity with application to low-power DSP system synthesis. ICASSP 1999: 1877-1880 - [c52]Khurram Muhammad, Kaushik Roy:
A novel design methodology for high performance and low power digital filters. ICCAD 1999: 80-83 - [c51]Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy:
Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. ICCD 1999: 230-235 - [c50]Kaushik Roy, Liqiong Wei, Zhanping Chen:
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ISCAS (1) 1999: 366-370 - [c49]Hendrawan Soeleman, Kaushik Roy:
Ultra-low power digital subthreshold logic circuits. ISLPED 1999: 94-96 - [c48]Ali Keshavarzi, Siva G. Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De:
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED 1999: 252-254 - [c47]Khurram Muhammad, Kaushik Roy:
A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters. ISSS 1999: 94-99 - [c46]Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik:
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. VLSI Design 1999: 416-422 - [c45]Sudip Nag, H. K. Verma, Kaushik Roy:
VLSI Signal Processing in FPGAs. VLSI Design 1999: 609 - [c44]Kaushik Roy, Anand Raghunathan, Sujit Dey:
Low Power Design Methodologies for Systems-on-Chips. VLSI Design 1999: 609 - 1998
- [j17]Tan-Li Chou, Kaushik Roy:
Power Estimation Under Uncertain Delays. Integr. Comput. Aided Eng. 5(2): 107-116 (1998) - [j16]Chuan-Yu Wang, Kaushik Roy:
Maximum power estimation for CMOS circuits using deterministic and statistical approaches. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 134-140 (1998) - [j15]Zhanping Chen, Kaushik Roy, Tan-Li Chou:
Efficient statistical approach to estimate power considering uncertain properties of primary inputs. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 484-492 (1998) - [j14]Dinesh Somasekhar, Kaushik Roy:
LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 573-577 (1998) - [j13]Sudip Nag, Kaushik Roy:
Performance and Wirability Driven Layout for Row-Based FPGAs. VLSI Design 7(4): 353-364 (1998) - [c43]Zhanping Chen, Kaushik Roy, Yibin Ye:
Estimation of average switching power under accurate modeling of signal correlations. CICC 1998: 507-510 - [c42]Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De:
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. DAC 1998: 489-494 - [c41]Zhanping Chen, Kaushik Roy:
A Power Macromodeling Technique Based on Power Sensitivity. DAC 1998: 678-683 - [c40]James R. Anderson, Siddharth Sheth, Kaushik Roy:
A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering. FPGA 1998: 234-244 - [c39]Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy:
IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. Great Lakes Symposium on VLSI 1998: 243-248 - [c38]Zhanping Chen, Kaushik Roy, Edwin K. P. Chong:
Estimation of power sensitivity in sequential circuits with power macromodeling application. ICCAD 1998: 468-472 - [c37]Kaushik Roy:
Leakage power reduction in low-voltage CMOS designs. ICECS 1998: 167-173 - [c36]Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy:
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ISLPED 1998: 239-244 - 1997
- [j12]Mark C. Johnson, Kaushik Roy:
Datapath scheduling with multiple supply voltages and level converters. ACM Trans. Design Autom. Electr. Syst. 2(3): 227-248 (1997) - [c35]Yibin Ye, Kaushik Roy:
Efficient synthesis of AND/XOR networks. ASP-DAC 1997: 539-544 - [c34]Yibin Ye, Kaushik Roy:
A Graph-Based Synthesis Algorithm for AND/XOR Networks. DAC 1997: 107-112 - [c33]Zhanping Chen, Kaushik Roy, Tan-Li Chou:
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. ICCAD 1997: 40-44 - [c32]Chuan-Yu Wang, Kaushik Roy:
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. ICCAD 1997: 52-55 - [c31]Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya:
Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. ICCAD 1997: 120-125 - [c30]Khurram Muhammad, Kaushik Roy:
On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution. ICCD 1997: 196-201 - [c29]Chuan-Yu Wang, Kaushik Roy:
Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions. ICCD 1997: 746-751 - [c28]Dinesh Somasekhar, Kaushik Roy:
LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. ISLPED 1997: 18-23 - [c27]Yibin Ye, Kaushik Roy, Georgios I. Stamoulis:
Quasi-static energy recovery logic and supply-clock generation circuits. ISLPED 1997: 96-99 - [c26]Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins:
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs. ITC 1997: 146-155 - [c25]Nirav H. Kapadia, Mark S. Lundstrom, José A. B. Fortes, Kaushik Roy:
Network-based simulation laboratories for microelectronics systems design and education. MSE 1997: 23-24 - [c24]Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya:
Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. VLSI Design 1997: 174-178 - [c23]Priya Patil, Tan-Li Chou, Kaushik Roy, Rabindra Roy:
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. VLSI Design 1997: 179-184 - 1996
- [j11]Dinesh Somasekhar, Kaushik Roy:
Differential current switch logic: a low power DCVS logic family. IEEE J. Solid State Circuits 31(7): 981-991 (1996) - [j10]Tan-Li Chou, Kaushik Roy:
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1257-1265 (1996) - [j9]S. C. Prasad, Kaushik Roy:
Transistor reordering for power minimization under delay constraint. ACM Trans. Design Autom. Electr. Syst. 1(2): 280-300 (1996) - [j8]Tan-Li Chou, Kaushik Roy:
Accurate power estimation of CMOS sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 4(3): 369-380 (1996) - [c22]Mark C. Johnson, Kaushik Roy:
Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints. ICCD 1996: 72-77 - [c21]Chuan-Yu Wang, Kaushik Roy:
Maximum power estimation for CMOS circuits using deterministic and statistic approaches. VLSI Design 1996: 364-369 - 1995
- [j7]Kaushik Roy, Sudip Nag:
On Routability for FPGAs under Faulty Conditions. IEEE Trans. Computers 44(11): 1296-1305 (1995) - [c20]Tan-Li Chou, Kaushik Roy:
Statistical estimation of sequential circuit activity. ICCAD 1995: 34-37 - [c19]Chuan-Yu Wang, Kaushik Roy:
Control unit synthesis targeting low-power processors. ICCD 1995: 454-459 - [c18]Tan-Li Chou, Kaushik Roy:
Estimation of sequential circuit activity considering spatial and temporal correlations. ICCD 1995: 577-582 - [c17]Kevin T. Kornegay, Kaushik Roy:
Integrated Test Solutions and Test Economics for MCMs. ITC 1995: 193-201 - [c16]S. C. Prasad, Kaushik Roy:
Circuit optimization for minimisation of power consumption under delay constraint. VLSI Design 1995: 305-309 - 1994
- [j6]Kaushik Roy, Abhijit Chatterjee:
Guest Editors' Introduction: Low-Power VLSI Design. IEEE Des. Test Comput. 11(4): 6-7 (1994) - [j5]Marc E. Levitt, Kaushik Roy, Jacob A. Abraham:
BiCMOS logic testing. IEEE Trans. Very Large Scale Integr. Syst. 2(2): 241-248 (1994) - [j4]Kaushik Roy, Sudip Nag:
Automatic synthesis of FPGA channel architecture for routability and performance. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 508-511 (1994) - [c15]Kaushik Roy, Sharat Prasad:
Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects. EURO-DAC 1994: 136-141 - [c14]Kaushik Roy, Sharat Prasad:
Power Dissipation Driven FPGA Place and Route Under Delay Constraints. FPL 1994: 57-65 - [c13]Kaushik Roy, Sudip Nag:
On Channel Architecture and Routability for FPGAs Under Faulty Conditions. FPL 1994: 361-372 - [c12]Tan-Li Chou, Kaushik Roy, Sharat Prasad:
Estimation of circuit activity considering signal correlations and simultaneous switching. ICCAD 1994: 300-303 - [c11]Santanu Dutta, Sudip Nag, Kaushik Roy:
ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits. ISCAS 1994: 61-64 - 1993
- [j3]Kaushik Roy:
A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(11): 1695-1705 (1993) - [j2]Kaushik Roy, S. C. Prasad:
Circuit activity based logic synthesis for low power reliable operations. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 503-513 (1993) - [c10]Sudip Nag, Kaushik Roy:
Iterative Wirability and Performance Improvement for FPGAs. DAC 1993: 321-325 - [c9]Kaushik Roy, Sudip Nag, Santanu Dutta:
Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. ICCD 1993: 220-223 - [c8]Kaushik Roy:
On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs. ISCAS 1993: 1623-1626 - [c7]Mahesh Mehendale, Kaushik Roy:
Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. VLSI Design 1993: 100-103 - 1992
- [c6]Kaushik Roy, Sharat Prasad:
SYCLOP: Synthesis of CMOS Logic for Low Power Applications. ICCD 1992: 464-467 - 1990
- [j1]Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham:
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. IEEE Trans. Computers 39(9): 1132-1145 (1990) - [c5]Kaushik Roy, Jacob A. Abraham:
High level test generation using data flow descriptions. EURO-DAC 1990: 480-484 - [c4]Marc E. Levitt, Kaushik Roy, Jacob A. Abraham:
BiCMOS fault models: is stuck-at adequate? ICCD 1990: 294-297
1980 – 1989
- 1989
- [c3]Kaushik Roy, Jacob A. Abraham:
A Novel Approach to Accurate Timing Verification Using RTL Descriptions. DAC 1989: 638-641 - [c2]Kaushik Roy, Jacob A. Abraham, Kaushik De, Stephen L. Lusky:
Synthesis of delay fault testable combinational logic. ICCAD 1989: 418-421 - 1988
- [c1]Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Jacob A. Abraham:
An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor. FTCS 1988: 362-367
Coauthor Index
[j261] [j258] [c486] [c484] [c477] [j248] [c476] [i114] [j238] [j234] [j233] [j231] [j230] [j229] [c463] [c462] [c452] [i102] [i95] [j218] [j216] [j214] [j212] [c450] [c447] [i83] [i82] [i75] [i73] [i69] [j208] [j202] [j201] [c438] [c435] [j193] [c430] [c424] [c417] [i55] [i48] [i43] [i41] [i40] [i31]
[j177] [j176] [j169] [j161] [j157] [j136] [c312] [j117] [j113] [j111] [c277] [c273] [j102] [j96] [j94] [c264] [c256] [c246] [c242] [i2] [i1] [j85] [j83] [j81] [j75] [c239] [c238] [c229] [c228] [c224] [c222] [j73] [j72] [j68] [j64] [j59] [j58] [j56] [j55] [c214] [c212] [c209] [c208] [c206] [c205] [c204] [c197] [c193] [c187] [c182] [c180] [c176] [j48] [c168] [c167] [c162] [c158] [c148] [c137] [c132] [c130] [c115] [c114] [c109] [c98]
Ik Joon Chang
aka: Ik-Joon Chang
aka: Ik-Joon Chang
Vinay K. Chippa
aka: Vinay Kumar Chippa
aka: Vinay Kumar Chippa
Adarsh Kosta
aka: Adarsh Kumar Kosta
aka: Adarsh Kumar Kosta
Chamika M. Liyanagedera
aka: Chamika Mihiranga Liyanagedera
aka: Chamika Mihiranga Liyanagedera
Hamid Mahmoodi
aka: Hamid Mahmoodi-Meimand
aka: Hamid Mahmoodi-Meimand
[j168] [c325] [j126] [c316] [j119] [j117] [j115] [j112] [j107] [j101] [c252] [j79] [j75] [c239] [c228] [c215] [j70] [j66] [j62] [j59] [j55] [c213] [c209] [c205] [c203] [c200] [c197] [c194] [c180] [c179] [c178] [c177] [c176] [j52] [j50] [c172] [c167] [c165] [c164] [c162] [c157] [c156] [c123] [j38] [c104]
[i144] [j177] [j176] [j169] [j135] [j114] [j112] [j111] [c272] [c271] [j107] [j105] [c262] [c247] [c242] [i2] [i1] [j88] [j85] [j84] [j83] [j79] [c238] [c237] [c235] [c232] [c227] [c216] [c215] [j70] [j69] [j67] [j66] [j60] [j59] [c214] [c213] [c211] [c208] [c206] [c200] [c196] [c194] [c193] [c188] [c181] [c179] [c177] [j51] [c172] [c170] [c164] [c162] [c144] [j43] [c139] [c129] [c125] [c121] [j38]
[j275] [j261] [c478] [j243] [i110] [j239] [j232] [c459] [c458] [c457] [c456] [c451] [i100] [i94] [i92] [j220] [j219] [j217] [j215] [j213] [c443] [c442] [c440] [i81] [i77] [i76] [i72] [i70] [j210] [j209] [j207] [i67] [i62] [i60] [i57] [j196] [j193] [j191] [c430] [c426] [c425] [c422] [c419] [c415] [i55] [i53] [i52] [i51] [i46] [i45] [i38] [c406] [c403] [c401] [c392] [i37] [i32] [i31] [i26] [i25] [i23]
Bipul Chandra Paul
aka: Bipul C. Paul
aka: Bipul C. Paul
[c516] [i162] [i145] [j255] [i142] [j250] [c487] [c485] [p4] [i126] [j242] [j237] [j231] [j228] [i101] [j218] [p3] [j209] [j208] [j198] [c439] [i58] [j191] [c431] [c428] [i54] [j190] [j187] [j186] [j185] [j183] [j182] [j179] [c411] [c408] [c406] [c405] [c393] [c392] [i35] [j175] [j172] [c391] [c390] [c389] [c388] [c387] [c384] [c381] [i27] [i26] [j165] [c379] [c377] [c375] [c373] [c372] [c371] [i11] [j160] [j159] [c369] [c368] [c366] [c365] [c364] [c361] [c360] [c356] [c354] [j152] [c353] [c352] [c348] [c347] [c340] [c331] [c329] [c326] [c323] [c321] [c315] [c304] [c291] [c44]
[j261] [j254] [j242] [j229] [j221] [c458] [j202] [j201] [c435] [i68] [i63] [i58] [j196] [j191] [c430] [c427] [c424] [c417] [i55] [i49] [i48] [i47] [i44] [i41] [j184] [j182] [j181] [j180] [c412] [c409] [c407] [c406] [c403] [c400] [c396] [c392] [i34] [c383] [i26] [i25] [i24] [i23] [i22] [i21] [i17] [i15] [i14] [i12]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-19 23:09 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
