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ORCIDYusung Kim 0002
Person information
- affiliation: Intel Corporation, Hillsboro, OR, USA
- affiliation (former): Purdue University, School of Electrical and Computer Engineering, West Lafayette, IN, USA
- affiliation (PhD 2015): Purdue University, West Lafayette, IN, USA
Other persons with the same name
- Yusung Kim 0001
![[0000-0002-9306-8738]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-9306-8738")
— Sungkyunkwan University, Department of Computer Engineering, Suwon, South Korea (and 1 more) - Yusung Kim 0003 — University of Iowa, Department of Radiation Oncology, Iowa City, IA, USA (and 1 more)
- Yusung Kim 0004 — Korea Advanced Institute of Science and Technology, Department of Mechanical Engineering, Daejeon, South Korea
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2020 – today
- 2024
[c4]Daeyeon Kim, Yusung Kim, Ayush Shrivastava, Gyusung Park, Anandkumar Mahadevan Pillai, Kunal Bannore, Tri Doan, Muktadir Rahman, Gwanghyeon Baek, Clifford Ong, Xiaofei Wang, Zheng Guo, Eric Karl:
15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia. ISSCC 2024: 278-280- 2023
- [j6]Yusung Kim, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl:
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology. IEEE J. Solid State Circuits 58(4): 1087-1093 (2023) - 2022
- [c3]Yusung Kim, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl:
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology. VLSI Technology and Circuits 2022: 212-213 - 2020
- [c2]Zheng Guo, Jami Wiedemer, Yusung Kim, Prithvee Sundararajan Ramamoorthy, Prateeksha Bindiganavile Sathyaprasad, Smita Shridharan, Daeyeon Kim, Eric Karl:
A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead. VLSI Circuits 2020: 1-2
2010 – 2019
- 2016
- [j5]Xuanyao Fong, Yusung Kim, Rangharajan Venkatesan, Sri Harsha Choday, Anand Raghunathan, Kaushik Roy:
Spin-Transfer Torque Memories: Devices, Circuits, and Systems. Proc. IEEE 104(7): 1449-1488 (2016) - [j4]Xuanyao Fong, Yusung Kim, Karthik Yogendra, Deliang Fan, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy:
Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 1-22 (2016) - 2015
- [j3]Kaushik Roy, Deliang Fan, Xuanyao Fong, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, Saibal Mukhopadhyay:
Exploring Spin Transfer Torque Devices for Unconventional Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 5-16 (2015) - [i2]Abhronil Sengupta, Priyadarshini Panda, Parami Wijesinghe, Yusung Kim, Kaushik Roy:
Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons. CoRR abs/1510.00440 (2015) - 2014
- [j2]Xuanyao Fong, Yusung Kim, Sri Harsha Choday, Kaushik Roy:
Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 384-395 (2014) - [j1]Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim, Kaushik Roy:
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 712-720 (2014) - [i1]Abhronil Sengupta, Sri Harsha Choday, Yusung Kim, Kaushik Roy:
Spin Orbit Torque Based Electronic Neuron. CoRR abs/1410.1257 (2014) - 2012
- [c1]Yusung Kim, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy:
Write-optimized reliable design of STT MRAM. ISLPED 2012: 3-8
Coauthor Index
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