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2020 – today
- 2024
[j61]Xiaoxuan Yang
, Zhangyang Wang, X. Sharon Hu, Chris H. Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, Hai Helen Li:
Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1683-1689 (2024)- [c105]Ameya Khot, Taesic Kim, Alve Rahman Akash, Chris H. Kim, William Moy:
Quantum-Inspired Machine Learning Framework using a Physics-based Ising Solver Chip. ICPS 2024: 1-6 - [c104]Yong Hyeon Yi, Chris H. Kim, Armen Kteyan, Alexander Volkov, Stéphane Moreau, Valeriy Sukharev:
Electromigration Test Chip Experiments from Realistic Power Grid Structures: Failure Trend Comparison and Statistical Analysis. IRPS 2024: 1-6 - [d1]Hüsrev Cilasun, William Moy, Ziqing Zeng, Tahmida Islam, Hao Lo, Alex Vanasse, Megan Tan, Mohammad Anees, Ramprasath S, Abhimanyu Kumar, Sachin S. Sapatnekar, Chris H. Kim, Ulya R. Karpuzcu:
COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization. Zenodo, 2024
- 2023
- [c103]Yong Hyeon Yi, Chris H. Kim, Chen Zhou, Armen Kteyan, Valeriy Sukharev:
Studying the Impact of Temperature Gradient on Electromigration Lifetime Using a Power Grid Test Structure with On-Chip Heaters. IRPS 2023: 1-5 - [c102]Armen Kteyan, Valeriy Sukharev, Alexander Volkov, Jun-Ho Choy, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Stéphane Moreau:
Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution. ISPD 2023: 124-132 - [i4]M. Hüsrev Cilasun, Ziqing Zeng, Ramprasath S, Abhimanyu Kumar, Hao Lo, William Cho, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar:
3SAT on an All-to-All-Connected CMOS Ising Solver Chip. CoRR abs/2309.11017 (2023) - 2022
- [j60]Minsu Kim, Muqing Liu, Luke R. Everson, Chris H. Kim:
An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process. IEEE J. Solid State Circuits 57(2): 625-638 (2022) - [j59]Valeriy Sukharev, Armen Kteyan, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Jun-Ho Choy, Sofya Torosyan, Yu Zhu:
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4837-4850 (2022) - [j58]Po-Wei Chiu, Chris H. Kim:
A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 1943-1951 (2022) - [j57]S. Karen Khatamifard, Zamshed I. Chowdhury, Nakul Pande, Meisam Razaviyayn, Chris H. Kim, Ulya R. Karpuzcu:
GeNVoM: Read Mapping Near Non-Volatile Memory. IEEE ACM Trans. Comput. Biol. Bioinform. 19(6): 3482-3496 (2022) - [c101]Tahmida Islam, Junkyu Kim, Chris H. Kim, David Tipple, Michael Nelson, Robert Jin, Anis Jarrar:
A Calibration-Free Synthesizable Odometer Featuring Automatic Frequency Dead Zone Escape and Start-up Glitch Removal. IRPS 2022: 2-1 - [c100]Armen Kteyan, Valeriy Sukharev, Y. Yi, Chris H. Kim:
Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation (Invited). IRPS 2022: 8 - 2021
- [j56]Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim:
A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control. IEEE J. Solid State Circuits 56(7): 2281-2290 (2021) - [j55]Ibrahim Ahmed, Po-Wei Chiu, William Moy, Chris H. Kim:
A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. IEEE J. Solid State Circuits 56(9): 2870-2880 (2021) - [j54]Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim:
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 843-856 (2021) - [j53]Saurabh Kumar, Minki Cho, Luke R. Everson, Andres Malavasi, Dan Lake, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De, Chris H. Kim:
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2086-2097 (2021) - [c99]Hanzhao Yu, Gyusung Park, Chris H. Kim:
Extreme Temperature Characterization of Amplifier Response up to 300 Degrees Celsius Using Integrated Heaters and On-chip Samplers. ESSCIRC 2021: 411-414 - [c98]Gyusung Park, Hanzhao Yu, Minsu Kim, Chris H. Kim:
An All BTI (N-PBTI, N-NBTI, P-PBTI, P-NBTI) Odometer based on a Dual Power Rail Ring Oscillator Array. IRPS 2021: 1-5 - 2020
- [c97]Minsu Kim, Jeehwan Song, Chris H. Kim:
Reliability Characterization of Logic-Compatible NAND Flash Memory based Synapses with 3-bit per Cell Weights and 1μA Current Steps. IRPS 2020: 1-4 - [c96]Po-Wei Chiu, Chris H. Kim:
22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor. ISSCC 2020: 336-338 - [c95]Ibrahim Ahmed, Po-Wei Chiu, Chris H. Kim:
A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j52]Somnath Kundu, Muqing Liu, Shi-Jie Wen, Richard Wong, Chris H. Kim:
A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer. IEEE J. Solid State Circuits 54(1): 109-120 (2019) - [j51]Luke R. Everson, Muqing Liu, Nakul Pande, Chris H. Kim:
An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm. IEEE J. Solid State Circuits 54(10): 2777-2785 (2019) - [j50]Dwaipayan Biswas, Luke R. Everson, Muqing Liu, Madhuri Panwar, Bram-Ernst Verhoef, Shrishail Patki, Chris H. Kim, Amit Acharyya, Chris Van Hoof, Mario Konijnenburg, Nick Van Helleputte:
CorNET: Deep Learning Framework for PPG-Based Heart Rate Estimation and Biometric Identification in Ambulant Environment. IEEE Trans. Biomed. Circuits Syst. 13(2): 282-291 (2019) - [c94]Leandro Mateus Giacomini Rocha, Nick Van Helleputte, Muqing Liu, Dwaipayan Biswas, Bram-Ernst Verhoef, Sergio Bampi, Chris H. Kim, Chris Van Hoof, Mario Konijnenburg, Marian Verhelst:
Real-time HR Estimation from wrist PPG using Binary LSTMs. BioCAS 2019: 1-4 - [c93]Gyusung Park, Minsu Kim, Nakul Pande, Po-Wei Chiu, Jeehwan Song, Chris H. Kim:
A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing. CICC 2019: 1-4 - [c92]Luke R. Everson, Dwaipayan Biswas, Bram-Ernst Verhoef, Chris H. Kim, Chris Van Hoof, Mario Konijnenburg, Nick Van Helleputte:
BioTranslator: Inferring R-Peaks from Ambulatory Wrist-Worn PPG Signal. EMBC 2019: 4241-4245 - [c91]Nakul Pande, Gyusung Park, Chris H. Kim, Srikanth Krishnan, Vijay Reddy:
Investigating the Aging Dynamics of Diode-Connected MOS Devices Using an Array-Based Characterization Vehicle in a 65nm Process. IRPS 2019: 1-6 - [c90]Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim:
A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control. ISSCC 2019: 50-52 - 2018
- [j49]Po-Wei Chiu, Somnath Kundu, Qianying Tang, Chris H. Kim:
A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer. IEEE J. Solid State Circuits 53(4): 1203-1213 (2018) - [j48]Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi:
Key-Based Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered Mode-Based Design. IEEE Trans. Inf. Forensics Secur. 13(1): 79-93 (2018) - [c89]Anoop Koyily, Satya Venkata Sandeep Avvaru, Chen Zhou, Chris H. Kim, Keshab K. Parhi:
Effect of aging on linear and nonlinear MUX PUFs by statistical modeling. ASP-DAC 2018: 76-83 - [c88]Po-Wei Chiu, Muqing Liu, Qianying Tang, Chris H. Kim:
A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. A-SSCC 2018: 187-190 - [c87]Luke R. Everson, Muqing Liu, Nakul Pande, Chris H. Kim:
A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm. A-SSCC 2018: 273-276 - [c86]Luke R. Everson, Somnath Kundu, Gang Chen, Zhi Yang, Timothy J. Ebner, Chris H. Kim:
A 0.0094mm2/Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording. BioCAS 2018: 1-4 - [c85]Ramtin Zand, Kerem Yunus Çamsari, Steven D. Pyle, Ibrahim Ahmed, Chris H. Kim, Ronald F. DeMara:
Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons. ACM Great Lakes Symposium on VLSI 2018: 15-20 - [c84]Gyusung Park, Minsu Kim, Chris H. Kim, Bongjin Kim, Vijay Reddy:
All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. IRPS 2018: 5 - [c83]Luke R. Everson, Dwaipayan Biswas, Madhuri Panwar, Dimitrios Rodopoulos, Amit Acharyya, Chris H. Kim, Chris Van Hoof, Mario Konijnenburg, Nick Van Helleputte:
BiometricNet: Deep Learning based Biometric Identification using Wrist-Worn PPG. ISCAS 2018: 1-5 - [c82]Anoop Koyily, Chen Zhou, Chris H. Kim, Keshab K. Parhi:
Predicting Soft-Response of MUX PUFs via Logistic Regression of Total Delay Difference. ISCAS 2018: 1-5 - [c81]Qianying Tang, Won Ho Choi, Luke R. Everson, Keshab K. Parhi, Chris H. Kim:
A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC. ISCAS 2018: 1-5 - [c80]Somnath Kundu, Muqing Liu, Richard Wong, Shi-Jie Wen, Chris H. Kim:
A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning. ISSCC 2018: 308-310 - 2017
- [j47]Somnath Kundu, Bongjin Kim, Chris H. Kim:
A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection. IEEE J. Solid State Circuits 52(3): 799-811 (2017) - [j46]Qianying Tang, Chris H. Kim:
Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit. IEEE J. Solid State Circuits 52(6): 1655-1663 (2017) - [j45]Yingjie Lao, Bo Yuan, Chris H. Kim, Keshab K. Parhi:
Reliable PUF-Based Local Authentication With Self-Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 201-213 (2017) - [c79]Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi:
Functional encryption of integrated circuits by key-based hybrid obfuscation. ACSSC 2017: 484-488 - [c78]Muqing Liu, Luke R. Everson, Chris H. Kim:
A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities. CICC 2017: 1-4 - [c77]Qianying Tang, Chen Zhou, Woong Choi, Gyuseong Kang, Jongsun Park, Keshab K. Parhi, Chris H. Kim:
A DRAM based physical unclonable function capable of generating >1032 Challenge Response Pairs per 1Kbit array for secure chip authentication. CICC 2017: 1-4 - [c76]Chen Zhou, Keshab K. Parhi, Chris H. Kim:
Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements. DAC 2017: 10:1-10:6 - [c75]Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami:
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC 2017: 16:1-16:6 - [c74]Robert Perricone, Ibrahim Ahmed, Zhaoxin Liang, Meghna G. Mankalale, Xiaobo Sharon Hu, Chris H. Kim, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang:
Advanced spintronic memory and logic for non-volatile processors. DATE 2017: 972-977 - [c73]Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi:
Hierarchical functional obfuscation of integratec circuits using a mode-based approach. ISCAS 2017: 1-4 - [c72]Anoop Koyily, Chen Zhou, Chris H. Kim, Keshab K. Parhi:
An entropy test for determining whether a MUX PUF is linear or nonlinear. ISCAS 2017: 1-4 - [c71]Somnath Kundu, Chris H. Kim:
A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology. ISCAS 2017: 1-4 - [c70]Muqing Liu, Chen Zhou, Qianying Tang, Keshab K. Parhi, Chris H. Kim:
A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function. ISLPED 2017: 1-6 - [c69]S. V. Sandeep Avvaru, Chen Zhou, Chris H. Kim, Keshab K. Parhi:
Predicting hard and soft-responses and identifying stable challenges of MUX PUFs using ANNs. MWSCAS 2017: 934-937 - [i3]S. Karen Khatamifard, Zamshed I. Chowdhury, Nakul Pande, Meisam Razaviyayn, Chris H. Kim, Ulya R. Karpuzcu:
A Non-volatile Near-Memory Read Mapping Accelerator. CoRR abs/1709.02381 (2017) - [i2]Ramtin Zand, Kerem Yunus Çamsari, Ibrahim Ahmed, Steven D. Pyle, Chris H. Kim, Supriyo Datta, Ronald F. DeMara:
R-DBN: A Resistive Deep Belief Network Architecture Leveraging the Intrinsic Behavior of Probabilistic Devices. CoRR abs/1710.00249 (2017) - 2016
- [j44]Yingjie Lao, Qianying Tang, Chris H. Kim, Keshab K. Parhi:
Beat Frequency Detector-Based High-Speed True Random Number Generators: Statistical Modeling and Analysis. ACM J. Emerg. Technol. Comput. Syst. 13(1): 9:1-9:25 (2016) - [j43]Somnath Kundu, Chris H. Kim:
A 0.0054-mm2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor. IEEE Trans. Circuits Syst. II Express Briefs 63-II(5): 413-417 (2016) - [j42]Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim:
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3468-3476 (2016) - [c68]S. V. Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris H. Kim, Keshab K. Parhi:
Estimating delay differences of arbiter PUFs using silicon data. DATE 2016: 543-546 - [c67]Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi:
Mode-based Obfuscation using Control-Flow Modifications. CS2@HiPEAC 2016: 19-24 - [c66]Chen Zhou, Saroj Satapathy, Yingjie Lao, Keshab K. Parhi, Chris H. Kim:
Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs. ISLPED 2016: 124-129 - [c65]Somnath Kundu, Bongjin Kim, Chris H. Kim:
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection. ISSCC 2016: 326-327 - [i1]Meghna G. Mankalale, Zhaoxin Liang, Zhengyang Zhao, Chris H. Kim, Jianping Wang, Sachin S. Sapatnekar:
CoMET: Composite-Input Magnetoelectric-based Logic Technology. CoRR abs/1611.09714 (2016) - 2015
- [j41]Jongyeon Kim, Ayan Paul, Paul A. Crowell, Steven J. Koester, Sachin S. Sapatnekar, Jianping Wang, Chris H. Kim:
Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor. Proc. IEEE 103(1): 106-130 (2015) - [j40]Xiaofei Wang, Qianying Tang, Pulkit Jain, Dong Jiao, Chris H. Kim:
The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 280-291 (2015) - [j39]Tony Tae-Hyoung Kim, Pong-Fei Lu, Keith A. Jenkins, Chris H. Kim:
A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1360-1364 (2015) - [c64]Won Ho Choi, Hoon Ki Kim, Chris H. Kim:
Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs. CICC 2015: 1-4 - [c63]Jongyeon Kim, An Chen, Behtash Behin-Aein, Saurabh Kumar, Jianping Wang, Chris H. Kim:
A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies. CICC 2015: 1-4 - [c62]Bongjin Kim, Hoon Ki Kim, Chris H. Kim:
An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier. CICC 2015: 1-4 - [c61]Somnath Kundu, Bongjin Kim, Chris H. Kim:
Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals. CICC 2015: 1-4 - [c60]Saroj Satapathy, Won Ho Choi, Xiaofei Wang, Chris H. Kim:
A revolving reference odometer circuit for BTI-induced frequency fluctuation measurements under fast DVFS transients. IRPS 2015: 6 - [c59]Rahul Parhi, Chris H. Kim, Keshab K. Parhi:
Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR). ISCAS 2015: 41-44 - [c58]Somnath Kundu, Vassili Kireev, Chris H. Kim:
A 8-14 GHz varactorless current controlled LC oscillator in 16nm CMOS technology. MWSCAS 2015: 1-4 - [c57]Bongjin Kim, Somnath Kundu, Chris H. Kim:
A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit. VLSIC 2015: 140- - 2014
- [j38]Bongjin Kim, Weichao Xu, Chris H. Kim:
A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter. IEEE J. Solid State Circuits 49(4): 1017-1026 (2014) - [j37]Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications. IEEE J. Solid State Circuits 49(8): 1861-1871 (2014) - [j36]Xiaofei Wang, John Keane, Tony Tae-Hyoung Kim, Pulkit Jain, Qianying Tang, Chris H. Kim:
Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design. IEEE Micro 34(6): 74-85 (2014) - [j35]Pingqiang Zhou, Ayan Paul, Chris H. Kim, Sachin S. Sapatnekar:
Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 1954-1967 (2014) - [c56]Won Ho Choi, Saroj Satapathy, John Keane, Chris H. Kim:
A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage. CICC 2014: 1-4 - [c55]Bongjin Kim, Somnath Kundu, Seokkyun Ko, Chris H. Kim:
A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals. CICC 2014: 1-4 - [c54]Qianying Tang, Bongjin Kim, Yingjie Lao, Keshab K. Parhi, Chris H. Kim:
True Random Number Generator circuits based on single- and multi-phase beat frequency detection. CICC 2014: 1-4 - [c53]Xiaofei Wang, Weichao Xu, Chris H. Kim:
SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data. CICC 2014: 1-4 - [c52]Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar:
Improving STT-MRAM density through multibit error correction. DATE 2014: 1-6 - [c51]Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim:
Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. VLSID 2014: 399-404 - 2013
- [j34]Ki Chul Chun, Hui Zhao, Jonathan D. Harms, Tony Tae-Hyoung Kim, Jianping Wang, Chris H. Kim:
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory. IEEE J. Solid State Circuits 48(2): 598-610 (2013) - [j33]Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme. IEEE J. Solid State Circuits 48(5): 1302-1314 (2013) - [j32]Wei Zhang, Ki Chul Chun, Chris H. Kim:
A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2030-2038 (2013) - [c50]Bongjin Kim, Weichao Xu, Chris H. Kim:
A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal. CICC 2013: 1-4 - [c49]Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications. CICC 2013: 1-4 - 2012
- [j31]John Keane, Chris H. Kim, Qunzeng Liu, Sachin S. Sapatnekar:
Process and Reliability Sensors for Nanoscale CMOS. IEEE Des. Test Comput. 29(5): 8-17 (2012) - [j30]Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, Chris H. Kim:
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. IEEE J. Solid State Circuits 47(2): 547-559 (2012) - [j29]Dong Jiao, Bongjin Kim, Chris H. Kim:
Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation. IEEE J. Solid State Circuits 47(10): 2505-2516 (2012) - [j28]Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim:
A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor. IEEE J. Solid State Circuits 47(10): 2517-2526 (2012) - [j27]Tony Tae-Hyoung Kim, Wei Zhang, Chris H. Kim:
An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of VMIN Degradation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(3): 584-593 (2012) - [c48]Wei Zhang, Ki Chul Chun, Chris H. Kim:
A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode. CICC 2012: 1-4 - [c47]Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim:
Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. CICC 2012: 1-4 - [c46]Pulkit Jain, John Keane, Chris H. Kim:
An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs. ESSDERC 2012: 262-265 - [c45]Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar:
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. ICCAD 2012: 263-270 - [c44]Tony T. Kim, Pong-Fei Lu, Chris H. Kim:
Design of ring oscillator structures for measuring isolated NBTI and PBTI. ISCAS 2012: 1580-1583 - [c43]Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme. VLSIC 2012: 130-131 - 2011
- [j26]Chris H. Kim, Leland Chang:
Guest editors' introduction: Nanoscale Memories Pose Unique Challenges. IEEE Des. Test Comput. 28(1): 6-8 (2011) - [j25]Ki Chul Chun, Pulkit Jain, Jung-Hwa Lee, Chris H. Kim:
A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches. IEEE J. Solid State Circuits 46(6): 1495-1505 (2011) - [j24]John Keane, Wei Zhang, Chris H. Kim:
An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization. IEEE J. Solid State Circuits 46(10): 2374-2385 (2011) - [j23]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 603-614 (2011) - [j22]John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim:
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 787-795 (2011) - [c42]Pingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar:
Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. CICC 2011: 1-4 - [c41]Dong Jiao, Chris H. Kim:
A programmable adaptive phase-shifting PLL for clock data compensation under resonant supply noise. ISSCC 2011: 272-274 - [c40]Wei Zhang, Mingjing Ha, Daniele Braga, Michael J. Renn, C. Daniel Frisbie, Chris H. Kim:
A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell Refresh Power. ISSCC 2011: 326-328 - [c39]Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim:
A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. ISSCC 2011: 506-507 - 2010
- [j21]John Keane, Xiaofei Wang, Devin Persaud, Chris H. Kim:
An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB. IEEE J. Solid State Circuits 45(4): 817-829 (2010) - [j20]Dong Jiao, Jie Gu, Chris H. Kim:
Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise. IEEE J. Solid State Circuits 45(10): 2130-2141 (2010) - [j19]John Keane, Tony Tae-Hyoung Kim, Xiaofei Wang, Chris H. Kim:
On-chip reliability monitors for measuring circuit degradation. Microelectron. Reliab. 50(8): 1039-1053 (2010) - [j18]John Keane, Tony Tae-Hyoung Kim, Chris H. Kim:
An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 947-956 (2010) - [c38]Ki Chul Chun, Pulkit Jain, Chris H. Kim:
Logic-compatible embedded DRAM design for memory intensive low power systems. ISCAS 2010: 277-280 - [c37]Wei Zhang, Ki Chul Chun, Chris H. Kim:
Variation aware performance analysis of gain cell embedded DRAMs. ISLPED 2010: 19-24 - [e1]Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim:
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. ACM 2010, ISBN 978-1-4503-0146-6 [contents]
2000 – 2009
- 2009
- [j17]Jie Gu, Hanyong Eom, Chris H. Kim:
On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit. IEEE J. Solid State Circuits 44(6): 1765-1775 (2009) - [j16]Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim:
A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode. IEEE J. Solid State Circuits 44(6): 1785-1795 (2009) - [j15]Jie Gu, John Keane, Chris H. Kim:
Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 128-136 (2009) - [j14]Jie Gu, Ramesh Harjani, Chris H. Kim:
Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 292-301 (2009) - [j13]Jie Gu, Hanyong Eom, John Keane, Chris H. Kim:
Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1203-1211 (2009) - [c36]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Adaptive techniques for overcoming performance degradation due to aging in digital circuits. ASP-DAC 2009: 284-289 - [c35]Dong Jiao, Jie Gu, Chris H. Kim:
Circuit techniques for enhancing the clock data compensation effect under resonant supply noise. CICC 2009: 29-32 - [c34]Tony Tae-Hyoung Kim, Wei Zhang, Chris H. Kim:
An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation. CICC 2009: 231-234 - [c33]Ki Chul Chun, Pulkit Jain, Chris H. Kim:
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. ISLPED 2009: 119-120 - 2008
- [j12]Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim:
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing. IEEE J. Solid State Circuits 43(2): 518-529 (2008) - [j11]Tony Tae-Hyoung Kim, Randy Persaud, Chris H. Kim:
Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits. IEEE J. Solid State Circuits 43(4): 874-880 (2008) - [j10]Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim:
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 206-209 (2008) - [j9]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Body Bias Voltage Computations for Process and Temperature Compensation. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 249-262 (2008) - [j8]Jonggab Kil, Jie Gu, Chris H. Kim:
A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 456-465 (2008) - [j7]John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim:
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 598-602 (2008) - [c32]John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim:
An array-based test circuit for fully automated gate dielectric breakdown characterization. CICC 2008: 121-124 - [c31]Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim:
A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode. CICC 2008: 407-410 - [c30]Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim:
Circuit techniques for ultra-low power subthreshold SRAMs. ISCAS 2008: 2574-2577 - [c29]Dong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim:
Enhancing beneficial jitter using phase-shifted clock distribution. ISLPED 2008: 21-26 - [c28]Pulkit Jain, Tony Tae-Hyoung Kim, John Keane, Chris H. Kim:
A multi-story power delivery technique for 3D integrated circuits. ISLPED 2008: 57-62 - [c27]Chris H. Kim:
Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies. ISQED 2008: 4 - 2007
- [j6]Hiroaki Suzuki, Chris H. Kim, Kaushik Roy:
Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(2): 322-328 (2007) - [j5]Tony Tae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim:
Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 821-829 (2007) - [c26]Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim:
An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement. CICC 2007: 241-244 - [c25]Jie Gu, Sachin S. Sapatnekar, Chris H. Kim:
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. DAC 2007: 87-92 - [c24]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
NBTI-Aware Synthesis of Digital Circuits. DAC 2007: 370-375 - [c23]Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI 2007: 269-274 - [c22]Jie Gu, Hanyong Eom, Chris H. Kim:
Sleep transistor sizing and control for resonant supply noise damping. ISLPED 2007: 80-85 - [c21]John Keane, Tony Tae-Hyoung Kim, Chris H. Kim:
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. ISLPED 2007: 189-194 - [c20]Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim:
A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme. ISSCC 2007: 330-606 - [c19]Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI 2007: 512-513 - [c18]Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS 2007: 474-484 - 2006
- [j4]Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim:
Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro 26(2): 68-80 (2006) - [j3]Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 646-649 (2006) - [c17]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. ASP-DAC 2006: 559-564 - [c16]Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim:
Width Quantization Aware FinFET Circuit Design. CICC 2006: 337-340 - [c15]John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim:
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. DAC 2006: 425-428 - [c14]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
An analytical model for negative bias temperature instability. ICCAD 2006: 493-496 - [c13]Jonggab Kil, Jie Gu, Chris H. Kim:
A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting. ISLPED 2006: 67-72 - [c12]Tony Tae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim:
Utilizing reverse short channel effect for optimal subthreshold circuit design. ISLPED 2006: 127-130 - [c11]Jie Gu, John Keane, Chris H. Kim:
Modeling and analysis of leakage induced damping effect in low voltage LSIs. ISLPED 2006: 382-387 - [c10]Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Impact of NBTI on SRAM Read Stability and Design for Reliability. ISQED 2006: 210-218 - 2005
- [j2]Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 349-357 (2005) - [c9]Ik Joon Chang, Kunhyuk Kang, Saibal Mukhopadhyay, Chris H. Kim, Kaushik Roy:
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling. CICC 2005: 439-442 - [c8]Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy:
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105 - [c7]Jie Gu, Chris H. Kim:
Multi-story power delivery for supply noise reduction and low voltage operation. ISLPED 2005: 192-197 - [c6]Keejong Kim, Chris H. Kim, Kaushik Roy:
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. ISQED 2005: 59-64 - 2004
- [c5]Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy:
Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC 2004: 6-11 - [c4]Hari Ananthan, Chris H. Kim, Kaushik Roy:
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ISLPED 2004: 8-13 - 2003
- [j1]Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy:
Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 716-730 (2003) - [c3]Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED 2003: 6-9 - 2002
- [c2]Chris H. Kim, Kaushik Roy:
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. DATE 2002: 163-167 - [c1]Chris H. Kim, Kaushik Roy:
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. ISLPED 2002: 251-254
Coauthor Index
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