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ORCIDDATE 2017: Lausanne, Switzerland
- David Atienza, Giorgio Di Natale:
Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017. IEEE 2017, ISBN 978-3-9815370-8-6 - Florian Neugebauer, Ilia Polian, John P. Hayes:
Framework for quantifying and managing accuracy in stochastic circuit design. 1-6 - Issa Qiqieh
, Rishad A. Shafik, Ghaith Tarawneh, Danil Sokolov, Alex Yakovlev:
Energy-efficient approximate multiplier design using bit significance-driven logic compression. 7-12 - Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze:
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing. 13-18 - Lerong Chen, Jiawen Li, Yiran Chen, Qiuping Deng, Jiyuan Shen, Xiaoyao Liang, Li Jiang:
Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar. 19-24 - Guan Wang, Xiaojun Cai, Lei Ju, Chuanqi Zang, Mengying Zhao, Zhiping Jia:
Shared last-level cache management for GPGPUs with hybrid main memory. 25-30 - Mohammad Sadrosadati, Amirhossein Mirhosseini, Shahin Roozkhosh, Hazhir Bakhishi, Hamid Sarbazi-Azad:
Effective cache bank placement for GPUs. 31-36 - Arun Subramaniyan, Semeen Rehman, Muhammad Shafique, Akash Kumar, Jörg Henkel:
Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores. 37-42 - Kishore Punniyamurthy, Behzad Boroujerdian, Andreas Gerstlauer:
GATSim: Abstract timing simulation of GPUs. 43-48 - Sandeep Poddar, Rik Jongerius, Leandro Fiorin, Giovanni Mariani, Gero Dittmann, Andreea Anghel, Henk Corporaal:
MeSAP: A fast analytic power model for DRAM memories. 49-54 - Kecheng Ji, Ming Ling, Qin Wang, Longxing Shi, Jianping Pan:
AFEC: An analytical framework for evaluating cache performance in out-of-order processors. 55-60 - Sadia Moriam, Gerhard P. Fettweis:
Reliability assessment of fault tolerant routing algorithms in networks-on-chip: An analytic approach. 61-66 - Zana Ghaderi, Ayed Alqahtani, Nader Bagherzadeh:
Online monitoring and adaptive routing for aging mitigation in NoCs. 67-72 - Siddhartha, Nachiket Kapre:
eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processor. 73-78 - Manuel J. Barragán, Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda:
On the limits of machine learning-based test: A calibrated mixed-signal system case study. 79-84 - Sebastien Cliquennois:
An extension of Cohn's sensitivity theorem to mismatch analysis of 1-port resistor networks. 85-90 - Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Testing microfluidic Fully Programmable Valve Arrays (FPVAs). 91-96 - Nikolaos Zompakis, Michail Noltsis, Lorena Ndreu, Zacharias Hadjilambrou, Panayiotis Englezakis, Panagiota Nikolaou, Antoni Portero, Simone Libutti, Giuseppe Massari, Federico Sassi, Alessandro Bacchini, Chrysostomos Nicopoulos, Yiannakis Sazeides, Radim Vavrík, Martin Golasowski, Jiri Sevcík, Vít Vondrák, Francky Catthoor, William Fornaciari, Dimitrios Soudris:
HARPA: Tackling physically induced performance variability. 97-102 - Fabrice Cros, Leonidas Kosmidis, Franck Wartel, David Morales, Jaume Abella, Ian Broster, Francisco J. Cazorla:
Dynamic software randomisation: Lessons learnec from an aerospace case study. 103-108 - Per Gunnar Kjeldsberg, Andreas Gocht, Michael Gerndt, Lubomir Riha, Joseph Schuchart, Umbreen Sabir Mian:
READEX: Linking two ends of the computing continuum to improve energy-efficiency in dynamic applications. 109-114 - Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke:
BASTION: Board and SoC test instrumentation for ageing and no failure found. 115-120 - Gina Alioto, Paul M. Carpenter, Adrián Cristal, Osman S. Unsal, Marcus Leich, Christophe Avare:
RETHINK big: European roadmap for hardware anc networking optimizations for big data. 121-126 - Massimo Alioto:
Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing. 127-132 - Chenyun Pan, Azad Naeemi:
Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. 133-138 - Hsin-Pai Cheng, Wei Wen, Chunpeng Wu, Sicheng Li, Hai Helen Li, Yiran Chen:
Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective. 139-144 - András Horváth, Michael Hillmer, Qiuwen Lou, Xiaobo Sharon Hu, Michael T. Niemier:
Cellular neural network friendly convolutional neural networks - CNNs with CNNs. 145-150 - Pei Luo, Konstantinos Athanasiou, Yunsi Fei, Thomas Wahl:
Algebraic fault analysis of SHA-3. 151-156 - Minsu Kim, Sunhee Kong, Boeui Hong, Lei Xu, Weidong Shi, Taeweon Suh:
Evaluating coherence-exploiting hardware Trojan. 157-162 - Fatma Nur Esirci, Alp Arslan Bayrakci:
Hardware Trojan detection based on correlated path delays in defiance of variations with spatial correlations. 163-168 - Zhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik:
Malware detection using machine learning based analysis of virtual memory access patterns. 169-174 - Hussam Amrouch, Behnam Khaleghi, Jörg Henkel:
Optimizing temperature guardbands. 175-180 - Benjamin Barrois, Olivier Sentieys, Daniel Ménard:
The hidden cost of functional approximation against careful data sizing - A case study. 181-186 - Seogoo Lee, Lizy K. John, Andreas Gerstlauer:
High-level synthesis of approximate hardware under joint precision and voltage scaling. 187-192 - Sanchari Sen, Swagath Venkataramani, Anand Raghunathan:
Approximate computing for spiking neural networks. 193-198 - Jong Hwan Ko, Duckhwan Kim, Taesik Na, Jaeha Kung, Saibal Mukhopadhyay:
Adaptive weight compression for memory-efficient neural networks. 199-204 - Qiuwen Chen, Qinru Qiu:
Real-time anomaly detection for streaming data using burst code on a neurosynaptic processor. 205-207 - Parami Wijesinghe, Chamika M. Liyanagedera, Kaushik Roy:
Fast, low power evaluation of elementary functions using radial basis function networks. 208-213 - Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs. 214-219 - Shengcheng Wang, Hengyang Zhao, Sheldon X.-D. Tan, Mehdi Baradaran Tahoori:
Recovery-aware proactive TSV repair for electromigration in 3D ICs. 220-225 - Johannes Bund, Christoph Lenzen, Moti Medina:
Near-optimal metastability-containing sorting networks. 226-231 - Yecheng Zhao, Haibo Zeng:
The concept of unschedulability core for optimizing priority assignment in real-time systems. 232-237 - Saravanan Ramanathan, Arvind Easwaran:
Utilization difference based partitioned scheduling of mixed-criticality systems. 238-243 - Leo Hatvani, Reinder J. Bril, Sebastian Altmeyer:
Schedulability using native non-preemptive groups on an AUTOSAR/OSEK platform with caches. 244-249 - Zhe Li, Ao Ren, Ji Li, Qinru Qiu, Bo Yuan, Jeffrey Draper, Yanzhi Wang:
Structural design optimization for deep convolutional neural networks using stochastic computing. 250-253 - Ting Wang, Qian Zhang, Qiang Xu:
ApproxQA: A unified quality assurance framework for approximate computing. 254-257 - Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina:
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. 258-261 - Radha Krishna Aluru, Swaroop Ghosh:
Droop mitigating last level cache architecture for STTRAM. 262-265 - Omayma Matoussi, Frédéric Pétrot:
Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation. 266-269 - Enrico Fraccaroli, Franco Fummi:
Analog fault testing through abstraction. 270-273 - Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee:
BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking. 274-277 - Mustafa Altun, Valentina Ciriani, Mehdi Baradaran Tahoori:
Computing with nano-crossbar arrays: Logic synthesis and fault tolerance. 278-281 - Florian Kelbert, Franz Gregor, Rafael Pires, Stefan Köpsell, Marcelo Pasin, Aurelien Havet, Valerio Schiavoni, Pascal Felber, Christof Fetzer, Peter R. Pietzuch:
SecureCloud: Secure big data processing in untrusted clouds. 282-285 - Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker:
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. 286-289 - Martin Andraud, Gönenç Berkol, Jaro De Roose, Santosh Gannavarapu, Haoming Xin, Eugenio Cantatore, Pieter J. A. Harpe, Marian Verhelst, Peter G. M. Baltus:
Exploring the unknown through successive generations of low power and low resource versatile agents. 290-293 - Faiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah R. Awwad:
Power profiling of microcontroller's instruction set for runtime hardware Trojans detection without golden circuit models. 294-297 - Martin Bruestel, Akash Kumar:
Accounting for systematic errors in approximate computing. 298-301 - Amin Ghasemazar, Mieszko Lis:
Gaussian mixture error estimation for approximate circuits. 302-305 - Kai Neubauer, Philipp Wanko, Torsten Schaub, Christian Haubelt:
Enhancing symbolic system synthesis through ASPmT with partial assignment evaluation. 306-309 - Javad Bagherzadeh, Valeria Bertacco:
3DFAR: A three-dimensional fabric for reliable multi-core processors. 310-313 - Mostafa Kishani, Reza Eftekhari, Hossein Asadi:
Evaluating impact of human errors on the availability of data storage systems. 314-317 - Björn Forsberg, Andrea Marongiu, Luca Benini:
GPUguard: Towards supporting a predictable execution model for heterogeneous SoC. 318-321 - Lin Li, Philipp Wagner, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf:
A non-intrusive, operating system independent spinlock profiler for embedded multicore systems. 322-325 - Meisam Bahadori, Sébastien Rumley, Robert P. Polster, Alexander Gazman, Matt Traverso, Mark Webster, Kaushik Patel, Keren Bergman:
Energy-performance optimized design of silicon photonic interconnection networks for high-performance computing. 326-331 - Kaushik Patel:
Rapid growth of IP traffic is driving adoption of silicon photonics in data centers. 332-335 - Christian Reimer, Michael Kues, Piotr Roztocki, Benjamin Wetzel, Brent E. Little, Sai T. Chu, Lucia Caspani, David J. Moss, Roberto Morandotti:
Generation of complex quantum states via integrated frequency combs. 336-337 - Michael Raitza, Akash Kumar, Marcus Völp, Dennis Walter, Jens Trommer, Thomas Mikolajick, Walter M. Weber:
Exploiting transistor-level reconfiguration to optimize combinational circuits. 338-343 - Tushar Krishna, Arya Balachandran, Siau Ben Chiah, Li Zhang, Bing Wang, Cong Wang, Kenneth Eng-Kian Lee, Jürgen Michel, Li-Shiuan Peh:
Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V process. 344-349 - Zhezhi He, Deliang Fan:
A tunable magnetic skyrmion neuron cluster for energy efficient artificial neural network. 350-355 - Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan:
STAxCache: An approximate, energy efficient STT-MRAM cache. 356-361 - Fazal Hameed, Jerónimo Castrillón:
Rethinking on-chip DRAM cache for simultaneous performance and energy optimization. 362-367 - Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
An energy-efficient memory hierarchy for multi-issue processors. 368-373 - Yazhi Feng, Dan Feng, Chenye Yu, Wei Tong, Jingning Liu:
Mapping granularity adaptive FTL based on flash page re-programming. 374-379 - Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler:
Data flow testing for virtual prototypes. 380-385 - Alper Sen, Etem Deniz, Brian Kahne:
MINIME-validator: Validating hardware with synthetic parallel testcases. 386-391 - Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, Prabhat Mishra:
Cost-effective analysis of post-silicon functional coverage events. 392-397 - Kenneth O'Brien, Lorenzo Di Tucci, Gianluca Durelli, Michaela Blott:
Towards exascale computing with heterogeneous architectures. 398-403 - Tobias Becker, Pavel Burovskiy, Anna Maria Nestorov, Hristina Palikareva, Enrico Reggiani, Georgi Gaydadjiev:
From exaflop to exaflow. 404-409 - Marco Rabozzi, Giuseppe Natale, Emanuele Del Sozzo, Alberto Scolari, Luca Stornaiuolo, Marco D. Santambrogio:
Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project. 410-415 - Dirk Stroobandt, Catalin Bogdan Ciobanu, Marco D. Santambrogio, Gabriel Figueiredo, Andreas Brokalakis, Dionisios N. Pnevmatikatos, Michael Hübner, Tobias Becker, Alex J. W. Thom:
An open reconfigurable research platform as stepping stone to exascale high-performance computing. 416-421 - Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker:
Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. 422-427 - Jing Ye, Qingli Quo, Yu Hu, Xiaowei Li:
Fault diagnosis of arbiter physical unclonable function. 428-433 - Meng Zhang, Fei Wu, He Huang, Qian Xia, Jian Zhou, Changsheng Xie:
FPGA-based failure mode testing and analysis for MLC NAND flash memory. 434-439 - Ali BanaGozar, Mohammad Ali Maleki, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
Robust neuromorphic computing in the presence of process variation. 440-445 - Yue Ma, Thidapat Chantem, Robert P. Dick, Shige Wang, Xiaobo Sharon Hu:
An on-line framework for improving reliability of real-time systems on "big-little" type MPSoCs. 446-451 - Konstantinos Maragos, George Lentaris, Dimitrios Soudris, Kostas Siozios, Vasilis F. Pavlidis:
Application performance improvement by exploiting process variability on FPGA devices. 452-457 - Alwin Zulehner, Robert Wille:
Make it reversible: Efficient embedding of non-reversible functions. 458-463 - Nader Khammassi, Imran Ashraf, Xiang Fu, Carmen G. Almudéver, Koen Bertels:
QX: A high-performance quantum computer simulation platform. 464-469 - Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli:
Design automation and design space exploration for quantum computers. 470-475 - Rengarajan Ragavan, Benjamin Barrois, Cédric Killian, Olivier Sentieys:
Pushing the limits of voltage over-scaling for error-resilient applications. 476-481 - Xun Jiao, Vincent Camus, Mattia Cacciotti, Yu Jiang, Christian C. Enz, Rajesh K. Gupta:
Combining structural and timing errors in overclocked inexact speculative adders. 482-487 - Bert Moons, Roel Uytterhoeven, Wim Dehaene, Marian Verhelst:
DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling. 488-493 - Alexandre Mercat, Justine Bonnot, Maxime Pelcat, Wassim Hamidouche, Daniel Ménard:
Exploiting computation skip to reduce energy consumption by approximate computing, an HEVC encoder case study. 494-499 - E. J. Jose Gonzalez, Chen Luo, Anshumali Shrivastava, Krishna V. Palem, Yongshik Moon, Soonhyun Noh, Daedong Park, Seongsoo Hong:
Location detection for navigation using IMUs with a map through coarse-grained machine learning. 500-505 - Nicholas C. Doyle, Eric Matthews, Graham M. Holland, Alexandra Fedorova, Lesley Shannon:
Performance impacts and limitations of hardware memory access trace collection. 506-511 - Sebastian Ottlik, Christoph Gerum, Alexander Viehl, Wolfgang Rosenstiel, Oliver Bringmann:
Context-sensitive timing automata for fast source level simulation. 512-517 - Raphael Eidenbenz, Alexandra Moga, Thanikesavan Sivanthi, Carsten Franke:
MARS: A flexible real-time streaming platform for testing automation systems. 518-523 - Saurav Kumar Ghosh, Soumyajit Dey:
SERD: A simulation framework for estimation of system level reliability degradation. 524-529 - Gopalakrishnan Srinivasan, Abhronil Sengupta, Kaushik Roy:
Magnetic tunnel junction enabled all-spin stochastic spiking neural network. 530-535 - Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Peneau, Lionel Torres, Abdoulaye Gamatié, Pascal Benoit, Gilles Sassatelli:
Embedded systems to high performance computing using STT-MRAM. 536-541 - Wang Kang, Liang Chang, Youguang Zhang, Weisheng Zhao:
Voltage-controlled MRAM for working memory: Perspectives and challenges. 542-547 - Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui:
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. 548-553 - Nour Sayed, Mojtaba Ebrahimi, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Opportunistic write for fast and reliable STT-MRAM. 554-559 - Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee, Li Jiang:
Fault clustering technique for 3D memory BISR. 560-565 - Yen-Hao Chen, Chien-Pang Chiu, Russell Barnes, TingTing Hwang:
Architectural evaluations on TSV redundancy for reliability enhancement. 566-571 - Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi:
Reusing trace buffers to enhance cache performance. 572-577 - Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler:
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. 578-583 - Zain Alabedin Haj Hammadeh, Rolf Ernst, Sophie Quinton, Rafik Henia, Laurent Rioux:
Bounding deadline misses in weakly-hard real-time systems with task dependencies. 584-589 - Sebastian Tobuschat, Rolf Ernst:
Real-time communication analysis for Networks-on-Chip with backpressure. 590-595 - Yasmina Abdeddaïm, Dorin Maxim:
Probabilistic schedulability analysis for fixed priority mixed criticality real-time systems. 596-601 - Rui Wu, Yuyang Wang, Zeyu Zhang, Chong Zhang, Clint L. Schow, John E. Bowers, Kwang-Ting Cheng:
Compact modeling and circuit-level simulation of silicon nanophotonic interconnects. 602-605 - Yuanzhuo Qu, Jie Han, Bruce F. Cockburn, Witold Pedrycz, Yue Zhang, Weisheng Zhao:
A true random number generator based on parallel STT-MTJs. 606-609 - Panagiotis Chaourani, Per-Erik Hellström, Saul Rodriguez, Raul Onet, Ana Rusu:
Enabling area efficient RF ICs through monolithic 3D integration. 610-613 - Ragh Kuttappa, Lunal Khuon, Bahram Nabet, Baris Taskin:
Reconfigurable threshold logic gates using optoelectronic capacitors. 614-617 - Yuanchao Xu, Zeyi Hou, Junfeng Yan, Lu Yang, Hu Wan:
i-BEP: A non-redundant and high-concurrency memory persistency model. 618-621 - Shuo Li, Peng Wang, Nong Xiao, Guangyu Sun, Fang Liu:
SPMS: Strand based persistent memory system. 622-625 - Leonardo Ecco, Rolf Ernst:
Architecting high-speed command schedulers for open-row real-time SDRAM controllers. 626-629 - Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. 630-633 - Yuchao Ma, Hassan Ghasemzadeh:
Head-mounted sensors and wearable computing for automatic tunnel vision assessment. 634-637 - Ting Wang, Yannan Liu, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, Xinli Gu:
RetroDMR: Troubleshooting non-deterministic faults with retrospective DMR. 638-641 - Fotios Vartziotis, Xrysovalantis Kavousianos:
Critical path - Oriented & thermal aware X-filling for high un-modeled defect coverage. 642-645 - Davide Appello, Paolo Bernardi, G. Giacopelli, Alessandro Motta, Alberto Pagani, Giorgio Pollaccia, C. Rabbi, Marco Restifo, P. Ruberg, Ernesto Sánchez, C. M. Villa, Federico Venini:
A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC. 646-649 - Siting Liu, Jie Han:
Energy efficient stochastic computing with Sobol sequences. 650-653 - Hasan Baig, Jan Madsen:
Logic analysis and verification of n-input genetic logic circuits. 654-657 - Nikolaos Tampouratzis, Konstantinos Georgopoulos, Yannis Papaefstathiou:
A novel way to efficiently simulate complex full systems incorporating hardware accelerators. 658-661 - Enrico Fraccaroli, Michele Lora, Franco Fummi:
Automatic abstraction of multi-discipline analog models for efficient functional simulation. 662-665 - Mohammad Nasim Imtiaz Khan, Anirudh Srikant Iyengar, Swaroop Ghosh:
Novel magnetic burn-in for retention testing of STTRAM. 666-669 - Seyed-Hosein Attarzadeh-Niaki, Ingo Sander:
Automatic construction of models for analytic system-level design space exploration problems. 670-673 - Patrick Schaumont:
Security in the Internet of Things: A challenge of scale. 674-679 - Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian:
Sensitized path PUF: A lightweight embedded physical unclonable function. 680-685 - Sha Tao, Elena Dubrova:
Temperature aware phase/frequency detector-basec RO-PUFs exploiting bulk-controlled oscillators. 686-691 - Fabrizio De Santis, Andreas Schauer, Georg Sigl:
ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applications. 692-697 - Oscar M. Guillen, Thomas Pöppelmann, Jose Maria Bermudo Mera, Elena Fuentes Bongenaar, Georg Sigl, Johanna Sepúlveda:
Towards post-quantum security for IoT endpoints with NTRU. 698-703 - Matei Istoan, Florent de Dinechin:
Automating the pipeline of arithmetic datapaths. 704-709 - Paulo C. Santos, Geraldo F. Oliveira, Diego G. Tomé, Marco A. Z. Alves, Eduardo C. de Almeida, Luigi Carro:
Operand size reconfiguration for big data processing in memory. 710-715 - Lorenzo Di Tucci, Kenneth O'Brien, Michaela Blott, Marco D. Santambrogio:
Architectural optimizations for high performance and energy efficient Smith-Waterman implementation on FPGAs using OpenCL. 716-721 - Said Hamdioui, Shahar Kvatinsky, Gert Cauwenberghs, Lei Xie, Nimrod Wald, Siddharth Joshi, Hesham Mostafa Elsayed, Henk Corporaal, Koen Bertels:
Memristor for computing: Myth or reality? 722-731 - Weiwei Jiang, Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, Wayne P. Burleson, Greg Sadowski:
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart. 732-733 - Menbere Tekleyohannes, MohammadSadegh Sadri, Christian Weis, Norbert Wehn, Martin Klein, Michael Siegrist:
An advanced embedded architecture for connected component analysis in industrial applications. 734-735 - Ajith Sivadasan, Armelle Notin, Vincent Huard, Etienne Maurin, Souhir Mhira, Florian Cacho, Lorena Anghel:
Workload dependent reliability timing analysis flow. 736-737 - Mikel Fernández, David Morales, Leonidas Kosmidis, Alen Bardizbanyan, Ian Broster, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Paulo Machado, Luca Fossati:
Probabilistic timing analysis on time-randomized platforms for the space domain. 738-739 - Michael Masin, Francesca Palumbo, Hans Myrhaug, J. A. de Oliveira Filho, M. Pastena, Maxime Pelcat, Luigi Raffo, Francesco Regazzoni, A. A. Sanchez, Antonella Toffetti, Eduardo de la Torre, Katiuscia Zedda:
Cross-layer design of reconfigurable cyber-physical systems. 740-745 - Suzanne Lesecq, Julie Foucault, Francois Birot, Hugues de Chaumont, Carl Jackson, Marc Correvon, P. Heck, Richard Banach, Andrea Di Matteo, Vincenza Di Palma, John Barrett, Susan Rea, Jean-Marc Van Gyseghem, Cian O'Murchu, Alan Mathewson:
INSPEX: Design and integration of a portable/wearable smart spatial exploration system. 746-751 - Stefanos Skalistis, Alena Simalatsar:
Near-optimal deployment of dataflow applications on many-core platforms with real-time guarantees. 752-757 - Andreas Naderlinger:
Simulating preemptive scheduling with timing-aware blocks in Simulink. 758-763 - Biao Hu, Kai Huang, Gang Chen, Long Cheng, Alois C. Knoll:
Online workload monitoring with the feedback of actual execution time for real-time systems. 764-769 - Dwaipayan Chakraborty, Sumit Kumar Jha:
Automated synthesis of compact crossbars for sneak-path based in-memory computing. 770-775 - Amr M. Hassan, Chaofei Yang, Chenchen Liu, Hai Helen Li, Yiran Chen:
Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays. 776-781 - Debjyoti Bhattacharjee, Rajeswari Devadoss, Anupam Chattopadhyay:
ReVAMP: ReRAM based VLIW architecture for in-memory computing. 782-787 - Nam Ho, Ishraq Ibne Ashraf, Paul Kaufmann, Marco Platzner:
Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor. 788-793 - Dipanjan Bhadra, Kenneth S. Stevens:
Design of a low power, relative timing based asynchronous MSP430 microprocessor. 794-799 - Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney:
A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. 800-805 - Zhe Jiang, Neil C. Audsley:
GPIOCP: Timing-accurate general purpose I/O controller for many-core real-time systems. 806-811 - Tsutomu Sasao, Kyu Matsuura, Yukihiro Iguchi:
An algorithm to find optimum support-reducing decompositions for index generation functions. 812-817 - Alwin Zulehner, Robert Wille:
Taking one-to-one mappings for granted: Advanced logic design of encoder circuits. 818-823 - João Afonso, José Monteiro:
Analysis of short-circuit conditions in logic circuits. 824-829 - Mathias Soeken, Giovanni De Micheli, Alan Mishchenko:
Busy man's synthesis: Combinational delay optimization with SAT. 830-835 - Carmen G. Almudéver, Lingling Lao, Xiang Fu, Nader Khammassi, Imran Ashraf, Dan Iorga, Savvas Varsamopoulos, Christopher Eichler, Andreas Wallraff, Lotte Geck, Andre Kruth, Joachim Knoch, Hendrik Bluhm, Koen Bertels:
The engineering challenges in quantum computing. 836-845 - Seung-Yeob Lee, Joon-Sung Yang:
MVP ECC : Manufacturing process variation aware unequal protection ECC for memory reliability. 846-851 - Josef Kinseher, Leonhard Heis, Ilia Polian:
Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. 852-857 - Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene:
Mitigation of sense amplifier degradation using input switching. 858-863 - Anuj Pathania, Heba Khdr, Muhammad Shafique, Tulika Mitra, Jörg Henkel:
Scalable probabilistic power budgeting for many-cores. 864-869 - Matthias Beckert, Kai Bjorn Gemlau, Rolf Ernst:
Exploiting sporadic servers to provide budget scheduling for ARINC653 based real-time virtualization environments. 870-875 - Reinier van Kampenhout, Sander Stuijk, Kees Goossens:
Programming and analysing scenario-aware dataflow on a multi-processor platform. 876-881 - Saman Kiamehr, Mohammad Saber Golanbari, Mehdi Baradaran Tahoori:
Leveraging aging effect to improve SRAM-based true random number generators. 882-885 - Shahrzad Keshavarz, Christof Paar, Daniel E. Holcomb:
Design automation for obfuscated circuits with multiple viable functions. 886-889 - Dong Nguyen, Daewoo Kim, Jongeun Lee:
Double MAC: Doubling the performance of convolutional neural networks on modern FPGAs. 890-893 - Khoa Dang Pham, Edson L. Horta, Dirk Koch:
BITMAN: A tool and API for FPGA bitstream manipulations. 894-897 - Andreas Gerlach, Jürgen Scheible, Thoralf Rosahl, Frank-Thomas Eitrich:
A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example. 898-901 - Guus Kuiper, Marco Jan Gerrit Bekooij:
Latency analysis of homogeneous synchronous dataflow graphs using timed automata. 902-905 - Shivam Swami, Kartik Mohanram:
COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memories. 906-909 - Fangting Huang, Dan Feng, Yu Hua, Wen Zhou:
A wear-leveling-aware counter mode for data encryption in non-volatile memories. 910-913 - Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
Tunnel FET based refresh-free-DRAM. 914-917 - Srishty Patel, Rajshekar Kalayappan, Ishani Mahajan, Smruti R. Sarangi:
A hardware implementation of the MCAS synchronization primitive. 918-921 - Jeff Jun Zhang, Siddharth Garg:
BandiTS: Dynamic timing speculation using multi-armed bandit based optimization. 922-925 - Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Design and implementation of a fair credit-based bandwidth sharing scheme for buses. 926-929 - Boyu Zhang, Azadeh Davoodi:
Technology mapping with all spin logic. 930-933 - Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
A new method to identify threshold logic functions. 934-937 - Irith Pomeranz:
A bridging fault model for line coverage in the presence of undetected transition faults. 938-941 - Myeonggyun Han, Jinsu Park, Woongki Baek:
CHRT: A criticality- and heterogeneity-aware runtime system for task-parallel applications. 942-945 - Yaozu Dong, Jianguo Yao, Haibing Guan, R. Ananth Krishna, Yunhong Jiang:
MobiXen: Porting Xen on Android devices for mobile virtualization. 946-949 - Matina Maria Trompouki, Leonidas Kosmidis:
Optimisation opportunities and evaluation for GPGPU applications on low-end mobile GPUs. 950-953 - Jörg Henkel, Santiago Pagani, Hussam Amrouch, Lars Bauer, Farzad Samie:
Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies). 954-959 - Geoff V. Merrett, Bashir M. Al-Hashimi:
Energy-driven computing: Rethinking the design of energy harvesting systems. 960-965 - Fang Su, Kaisheng Ma, Xueqing Li, Tongda Wu, Yongpan Liu, Vijaykrishnan Narayanan:
Nonvolatile processors: Why is it trending? 966-971 - Robert Perricone, Ibrahim Ahmed, Zhaoxin Liang, Meghna G. Mankalale, Xiaobo Sharon Hu, Chris H. Kim, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang:
Advanced spintronic memory and logic for non-volatile processors. 972-977 - Rei Ueno, Naofumi Homma, Sumio Morioka, Takafumi Aoki:
Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme. 978-983 - Song Bian, Masayuki Hiromoto, Takashi Sato:
SCAM: Secured content addressable memory based on homomorphic encryption. 984-989 - Florian Bache, Tobias Schneider, Amir Moradi, Tim Güneysu:
SPARX - A side-channel protected processor for ARX-based cryptography. 990-995 - Ramin Fallahzadeh, Josué Pagán Ortiz, Hassan Ghasemzadeh:
Adaptive compressed sensing at the fingertip of Internet-of-Things sensors: An ultra-low power activity recognition. 996-1001 - Alexander Boschmann, Georg Thombansen, Linus Witschen, Alex Wiens, Marco Platzner:
A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. 1002-1007 - Zhewei Jiang, Chisung Bae, Joonseong Kang, Sang Joon Kim, Mingoo Seok:
Microwatt end-to-End digital neural signal processing systems for motor intention decoding. 1008-1013 - Daniela De Venuto, Valerio F. Annese, Giovanni Mezzina:
An embedded system remotely driving mechanical devices by P300 brain activity. 1014-1019 - Aatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty:
Revamping timing error resilience to tackle choke points at NTC systems. 1020-1025 - Mohsen Imani, Daniel Peroni, Yeseong Kim, Abbas Rahimi, Tajana Rosing:
Efficient neural network acceleration on GPGPU using content addressable memory. 1026-1031 - Shihao Wang, Dajiang Zhou, Xushen Han, Takeshi Yoshimura:
Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks. 1032-1037 - Francesco Beneventi, Andrea Bartolini, Carlo Cavazzoni, Luca Benini:
Continuous learning of HPC infrastructure models using big data analytics and in-memory processing tools. 1038-1043 - Peter R. Lewis:
Self-aware computing systems: From psychology to engineering. 1044-1049 - Johannes Schlatow, Mischa Möstl, Rolf Ernst, Marcus Nolte, Inga Jatzkowski, Markus Maurer, Christian Herber, Andreas Herkersdorf:
Self-awareness in autonomous automotive systems. 1050-1055 - Arman Anzanpour, Iman Azimi, Maximilian Gotzinger, Amir M. Rahmani, Nima Taherinejad, Pasi Liljeberg, Axel Jantsch, Nikil D. Dutt:
Self-awareness in remote health monitoring systems using wearable electronics. 1056-1061 - Simon Rokicki, Erven Rohou, Steven Derrien:
Hardware-accelerated dynamic binary translation. 1062-1067 - Ali Hassan El Moussawi, Steven Derrien:
Superword level parallelism aware word length optimization. 1068-1073 - Arno Luppold, Heiko Falk:
Schedulability-aware SPM Allocation for preemptive hard real-time systems with arbitrary activation patterns. 1074-1079 - Chu Li, Dan Feng, Yu Hua, Fang Wang, Chuntao Jiang, Wei Zhou:
A Log-aware Synergized scheme for page-level FTL design. 1080-1085 - Di Chen, Hai Jin, Xiaofei Liao, Haikun Liu, Rentong Guo, Dong Liu:
MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems. 1086-1091 - Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler:
Endurance management for resistive Logic-In-Memory computing architectures. 1092-1097 - Mohammad Khavari Tavana, Amir Kavyan Ziabari, David R. Kaeli:
Live together or Die Alone: Block cooperation to extend lifetime of resistive memories. 1098-1103 - Anupam Chattopadhyay, Alok Prakash, Muhammad Shafique:
Secure Cyber-Physical Systems: Current trends, tools and open research problems. 1104-1109 - Bernhard Jungk, Shivam Bhasin:
Don't fall into a trap: Physical side-channel analysis of ChaCha20-Poly1305. 1110-1115 - Onur Mutlu:
The RowHammer problem and other issues we may face as memory becomes denser. 1116-1121 - Nisha Jacob, Carsten Rolfes, Andreas Zankl, Johann Heyszl, Georg Sigl:
Compromising FPGA SoCs using malicious hardware blocks. 1122-1127 - Siddharth Garg:
Inspiring trust in outsourced integrated circuit fabrication. 1128 - Jean-Luc Danger, Sylvain Guilley, Philippe Nguyen, Robert Nguyen, Youssef Souissi:
Analyzing security breaches of countermeasures throughout the refinement process in hardware design flow. 1129-1134 - Behnaz Pourmohseni, Michael Glaß, Jürgen Teich:
Automatic operating point distillation for hybrid mapping methodologies. 1135-1140 - Guanwen Zhong, Alok Prakash, Siqi Wang, Yun Liang, Tulika Mitra, Smaïl Niar:
Design Space exploration of FPGA-based accelerators with multi-level parallelism. 1141-1146 - Atul Rahman, Sangyun Oh, Jongeun Lee, Kiyoung Choi:
Design space exploration of FPGA accelerators for convolutional neural networks. 1147-1152 - Alberto A. Del Barrio, Román Hermida:
A slack-based approach to efficiently deploy radix 8 booth multipliers. 1153-1158 - Lukas Sigrist, Andres Gomez, Roman Lim, Stefan Lippuner, Matthias Leubin, Lothar Thiele:
Measurement and validation of energy harvesting IoT devices. 1159-1164 - Daniele Jahier Pagliari, Yves Durand, David Coriat, Anca Molnos, Edith Beigné, Enrico Macii, Massimo Poncino:
A methodology for the design of dynamic accuracy operators by runtime back bias. 1165-1170 - Pascal Alexander Hager, Hamed Fatemi, José Pineda de Gyvez, Luca Benini:
A scan-chain based state retention methodology for IoT processors operating on intermittent energy. 1171-1176 - Yukai Chen, Enrico Macii, Massimo Poncino:
A circuit-equivalent battery model accounting for the dependency on load frequency. 1177-1182 - Xun Jiao, Yu Jiang, Abbas Rahimi, Rajesh K. Gupta:
SLoT: A supervised learning model to predict dynamic timing errors of functional units. 1183-1188 - Vikas Chandra, Liangzhen Lai:
Exploiting data-dependence and Flip-Flop asymmetry for zero-overhead system soft error mitigation. 1189-1194 - Wenlong Lv, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits. 1195-1200 - António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta:
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing. 1201-1206 - Chao Yan, Hengliang Zhu, Dian Zhou, Xuan Zeng:
An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid. 1207-1212 - Soheil Nazar Shahsavani, Alireza Shafaei, Shahin Nazarian, Massoud Pedram:
A thermally-aware energy minimization methodology for global interconnects. 1213-1218 - Chang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang, Kai-Chiang Wu:
Analysis and optimization of variable-latency designs in the presence of timing variability. 1219-1224 - Federico Angiolini, Aya Ibrahim, William Andrew Simon, Ahmet Caner Yuzuguler, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli:
1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA. 1225-1228 - Arthur Francisco Lorenzon, Jeckson Dellagostin Souza, Antonio Carlos Schneider Beck:
LAANT: A library to automatically optimize EDP for OpenMP applications. 1229-1232 - Ting-Wu Chin, Shiao-Li Tsao, Kuo-Wei Hung, Pei-Shu Huang:
Improving the accuracy of the leakage power estimation of embedded CPUs. 1233-1236 - Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias, Liam Fitzpatrick:
Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack. 1237-1240 - Jian Cai, Yooseong Kim, Youngbin Kim, Aviral Shrivastava, Kyoungwoo Lee:
Reducing code management overhead in software-managed multicores. 1241-1244 - Maohua Zhu, Youwei Zhuo, Chao Wang, Wenguang Chen, Yuan Xie:
Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications. 1245-1248 - Jisung Park, Sungjin Lee, Jihong Kim:
DAC: Dedup-assisted compression scheme for improving lifetime of NAND storage systems. 1249-1252 - Shunzhuo Wang, Fei Wu, Zhonghai Lu, You Zhou, Qin Xiong, Meng Zhang, Changsheng Xie:
Lifetime adaptive ECC in NAND flash page management. 1253-1556 - Miguel Angel Lastras-Montaño, Bhaswar Chakrabarti, Dmitri B. Strukov, Kwang-Ting Cheng:
3D-DPE: A 3D high-bandwidth dot-product engine for high-performance neuromorphic computing. 1257-1260 - Jung-Eun Kim, Richard M. Bradford, Tarek F. Abdelzaher, Lui Sha:
A schedulability test for software migration on multicore system. 1261-1264 - Haoran Li, Jiang Xu, Zhe Wang, Peng Yang, Rafael K. V. Maeda, Zhongyuan Tian:
Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators. 1265-1268 - Xiaoyang Mi, Hesam Fathi Moghadam, Jae-sun Seo:
Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators. 1269-1272 - Ons Lahiouel, Mohamed H. Zaki, Sofiène Tahar:
Enhancing analog yield optimization for variation-aware circuits sizing. 1273-1276 - Hiwa Mahmoudi, Horst Zimmermann:
A new sampling technique for Monte Carlo-based statistical circuit analysis. 1277-1280 - Jose Cachaco, Nuno Machado, Nuno Lourenço, Jorge Guilherme, Nuno Horta:
Automatic technology migration of analog IC designs using generic cell libraries. 1281-1284 - Ang Li, Peng Li, Tingwen Huang, Edgar Sánchez-Sinencio:
Noise-sensitive feedback loop identification in linear time-varying analog circuits. 1285-1288 - Syed Ali Asadullah Bukhari, Faiq Khalid Lodhi, Osman Hasan, Muhammad Shafique, Jörg Henkel:
CAnDy-TM: Comparative analysis of dynamic thermal management in many-cores using model checking. 1289-1292 - Shohdy Abdelkader, Alaa ELRouby, Mohamed Dessouky:
Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuits. 1293-1296 - Josué Pagán, Ramin Fallahzadeh, Hassan Ghasemzadeh, José Manuel Moya, José Luis Risco-Martín, José L. Ayala:
An optimal approach for low-power migraine prediction models in the state-of-the-art wireless monitoring devices. 1297-1302 - Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Janet Olson:
Logic optimization and synthesis: Trends and directions in industry. 1303-1305 - Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins:
Wave pipelining for majority-based beyond-CMOS technologies. 1306-1311 - Martin Rötteler, Krysta M. Svore, Dave Wecker, Nathan Wiebe:
Design automation for quantum architectures. 1312-1317 - Thomas Unterluggauer, Mario Werner, Stefan Mangard:
Side-channel plaintext-recovery attacks on leakage-resilient encryption. 1318-1323 - Thorben Moos, Amir Moradi, Bastian Richter:
Static power side-channel analysis of a threshold implementation prototype chip. 1324-1329 - Chao Luo, Yunsi Fei, A. Adam Ding:
Side-channel power analysis of XTS-AES. 1330-1335 - Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz, Yiorgos Makris, Carl Sechen:
A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration. 1336-1341 - Zeinab Seifoori, Behnam Khaleghi, Hossein Asadi:
A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era. 1342-1347 - Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li:
A static-placement, dynamic-issue framework for CGRA loop accelerator. 1348-1353 - Dominic DiTomaso, Md. Ashif I. Sikder, Avinash Karanth Kodi, Ahmed Louri:
Machine learning enabled power-aware Network-on-Chip design. 1354-1359 - Karthi Duraisamy, Partha Pratim Pande:
Performance evaluation and design trade-offs for wireless-enabled SMART NoC. 1360-1365 - Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise. 1366-1371 - Dionisio de Niz, Björn Andersson, Hyoseung Kim, Mark H. Klein, Linh Thi Xuan Phan, Raj Rajkumar:
Mixed-criticality processing pipelines. 1372-1375 - Jiating Luo, A. Elantably, Van-Dung Pham, Cédric Killian, Daniel Chillet, Sébastien Le Beux, Olivier Sentieys, Ian O'Connor:
Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC. 1372-1377 - Jochen Rust, Steffen Paul:
Exploiting special-purpose function approximation for hardware-efficient QR-decomposition. 1378-1383 - Walaa El-Harouni, Semeen Rehman, Bharath Srinivas Prabakaran, Akash Kumar, Rehan Hafiz, Muhammad Shafique:
Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding. 1384-1389 - Vladimir Rybalkin, Norbert Wehn, Mohammad Reza Yousefi, Didier Stricker:
Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition. 1390-1395 - Jiachen Mao, Xiang Chen, Kent W. Nixon, Christopher D. Krieger, Yiran Chen:
MoDNN: Local distributed mobile computing system for Deep Neural Network. 1396-1401 - Junlong Zhou, Jianming Yan, Tongquan Wei, Mingsong Chen, Xiaobo Sharon Hu:
Energy-adaptive scheduling of imprecise computation tasks for QoS optimization in real-Time MPSoC systems. 1402-1407 - Sujit Rokka Chhetri, Sina Faezi, Mohammad Abdullah Al Faruque:
Fix the leak! an information leakage aware secured cyber-physical manufacturing system. 1408-1413 - Zhiwei Feng, Nan Guan, Mingsong Lv, Weichen Liu, Qingxu Deng, Xue Liu, Wang Yi:
Efficient drone hijacking detection using onboard motion sensors. 1414-1419 - Luca Cerina, Marco D. Santambrogio:
Reconfigurable embedded systems applications for versatile biomedical measurements. 1420-1425 - Pierre-François Rüedi, A. Bishof, Marcin K. Augustyniak, Pascal Persechini, Jean-Luc Nagel, Marc Pons, Stéphane Emery, Olivier Chételat:
Ultra low power microelectronics for wearable and medical devices. 1426-1431 - Bojan Milosevic, Simone Benatti, Elisabetta Farella:
Design challenges for wearable EMG applications. 1432-1437 - Shaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Puneet Gupta:
Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing. 1438-1443 - Xunzhao Yin, Michael T. Niemier, Xiaobo Sharon Hu:
Design and benchmarking of ferroelectric FET based TCAM. 1444-1449 - Hoda Aghaei Khouzani, Pouya Fotouhi, Chengmo Yang, Guang R. Gao:
Leveraging access port positions to accelerate page table walk in DWM-based main memory. 1450-1455 - Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori:
VAET-STT: A variation aware estimator tool for STT-MRAM based memories. 1456-1461 - Dongyoung Kim, Junwhan Ahn, Sungjoo Yoo:
A novel zero weight/activation-aware hardware architecture of convolutional neural network. 1462-1467 - Marcelo Brandalero, Antonio Carlos Schneider Beck:
A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streams. 1468-1473 - Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Understanding the impact of precision quantization on the accuracy and energy of neural networks. 1474-1479 - Maria Malik, Katayoun Neshatpour, Tinoosh Mohsenin, Avesta Sasan, Houman Homayoun:
Big vs little core for energy-efficient Hadoop computing. 1480-1485 - Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides:
Quantifying error: Extending static timing analysis with probabilistic transitions. 1486-1491 - Ye-Hong Chen, Sheng-He Wang, Ting-Chi Wang:
On refining standard cell placement for self-aligned double patterning. 1492-1497 - Wachirawit Ponghiran, Seongbo Shim, Youngsoo Shin:
Cut mask optimization for multi-patterning directed self-assembly lithography. 1498-1503 - Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay:
Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation. 1504-1509 - Robert Hoettger, Burkhard Igel, Olaf Spinczyk:
On reducing busy waiting in autosar via task-release-delta-based runnable reordering. 1510-1515 - Benjamin J. Fletcher, Domenico Balsamo, Geoff V. Merrett:
Power neutral performance scaling for energy harvesting MP-SoCs. 1516-1521 - Nitin Shivaraman, Arvind Easwaran, Sebastian Steinhorst:
Efficient decentralized active balancing strategy for smart battery cells. 1522-1527 - Michele Magno, Fayçal Ait Aoudia, Matthieu Gautier, Olivier Berder, Luca Benini:
WULoRa: An energy efficient IoT end-node for energy harvesting and heterogeneous communication. 1528-1533 - Junchi Ma, Yun Wang:
Characterization of stack behavior under soft errors. 1534-1539 - Calvin Ma, Aditya Mahajan, Brett H. Meyer:
Multi-armed bandits for efficient lifetime estimation in MPSoC design. 1540-1545 - Liwei Zhou, Yiorgos Makris:
Hardware-based on-line intrusion detection via system call routine fingerprinting. 1546-1551 - Christoph Jäschke, Ulla Herter, Claudia Wolkober, Carsten Schmitt, Christian G. Zoellin:
Static netlist verification for IBM high-frequency processors using a tree-grammar. 1552-1557 - Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski:
Reverse engineering of irreducible polynomials in GF(2m) arithmetic. 1558-1563 - Umair Siddique, Khaza Anuarul Hoque, Taylor T. Johnson:
Formal specification and dependability analysis of optical communication networks. 1564-1569 - Simon J. Bale, Pedro B. Campos, Martin A. Trefzer, James Alfred Walker, Andy M. Tyrrell:
An evolutionary approach to runtime variability mapping and mitigation on a multi-reconfigurable architecture. 1570-1575 - Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Towards low power approximate DCT architecture for HEVC standard. 1576-1581 - Priyadarshini Panda, Kaushik Roy:
Semantic driven hierarchical learning for energy-efficient image classification. 1582-1587 - Dwaipayan Biswas, Vibishna Balagopal, Rishad A. Shafik, Bashir M. Al-Hashimi, Geoff V. Merrett:
Machine learning for run-time energy optimisation in many-core systems. 1588-1592 - Andrea Marcelli, Marco Restifo, Ernesto Sánchez, Giovanni Squillero:
An evolutionary approach to hardware encryption and Trojan-horse mitigation. 1593-1598 - Mirela Simonovic, Vojin Zivojnovic, Lazar Saranovac:
Formal model for system-level power management design. 1599-1602 - Tianchan Guan, Xiaoyang Zeng, Mingoo Seok:
Extending memory capacity of neural associative memory based on recursive synaptic bit reuse. 1603-1606 - Amir Aminifar, Enrico Bini:
Anomalies in scheduling control applications and design complexity. 1607-1610 - Tobias Sehnke, Matthias Schultalbers, Rolf Ernst:
Contract-based integration of automotive control software. 1611-1614 - Zhicheng Fu, Chunhui Guo, Shangping Ren, Yu Jiang, Lui Sha:
Modeling and integrating physical environment assumptions in medical cyber-physical system design. 1615-1618 - Soumi Chattopadhyay, Ansuman Banerjee, Bei Yu:
A utility-driven data transmission optimization strategy in large scale cyber-physical systems. 1619-1622 - Haiyu Mao, Xian Zhang, Guangyu Sun, Jiwu Shu:
Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/miss. 1623-1626 - Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler:
Effects of cell shapes on the routability of Digital Microfluidic Biochips. 1627-1630 - Amey M. Kulkarni, Colin Shea, Houman Homayoun, Tinoosh Mohsenin:
LESS: Big data sketching and Encryption on low power platform. 1631-1634 - Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Zainalabedin Navabi:
TruncApp: A truncation-based approximate divider for energy efficient DSP applications. 1635-1638 - Youngsoo Song, Sangmin Kim, Youngsoo Shin:
Timing-aware wire width optimization for SADP process. 1639-1642 - Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich:
Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networks. 1643-1646 - Daniele Palossi, Andrea Marongiu, Luca Benini:
Ultra low-power visual odometry for nano-scale unmanned aerial vehicles. 1647-1650 - Maurizio Rossi, Pietro Tosato, Luca Gemma, Luca Torquati, Cristian Catania, Sergio Camalo, Davide Brunelli:
Long range wireless sensing powered by plant-microbial fuel cell. 1651-1654 - Alexandre Lombard, Florent Perronnet, Abdeljalil Abbas-Turki, Abdellah El Moudni:
On the cooperative automatic lane change: Speed synchronization and automatic "courtesy". 1655-1658 - Pareesa Ameneh Golnari, Sharad Malik:
Evaluating matrix representations for error-tolerant computing. 1659-1662 - Dmitry Osipov, Steffen Paul:
Simulation-based design procedure for sub 1V CMOS current reference. 1663-1666 - Wei-Lun Huang, Ankur Gupta, Sudip Roy, Tsung-Yi Ho, Paul Pop:
Fast architecture-level synthesis of fault-tolerant flow-based microfluidic biochips. 1667-1672 - Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform. 1673-1678 - Andreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille:
Verification of networked Labs-on-Chip architectures. 1679-1684 - Seban Kim, Jaeyong Chung:
Synthesis of activation-parallel convolution structures for neuromorphic architectures. 1685-1690 - Armaiti Ardeshiricham, Wei Hu, Joshua Marxen, Ryan Kastner:
Register transfer level information flow tracking for provably secure hardware design. 1691-1696 - Oscar Reparaz, Josep Balasch, Ingrid Verbauwhede:
Dude, is my code constant time? 1697-1702 - Mohammad-Mahdi Bidmeshki, Angelos Antonopoulos, Yiorgos Makris:
Information flow tracking in analog/mixed-signal designs through proof-carrying hardware IP. 1703-1708 - Xinnian Zheng, Haris Vikalo, Shuang Song, Lizy K. John, Andreas Gerstlauer:
Sampling-based binary-level cross-platform performance estimation. 1709-1714 - George Ungureanu, Ingo Sander:
A layered formal framework for modeling of cyber-physical systems. 1715-1720 - Gabriela Breaban, Sander Stuijk, Kees Goossens:
Efficient synchronization methods for LET-based applications on a Multi-Processor System on Chip. 1721-1726 - Xiaoyi Wang, Hongyu Wang, Jian He, Sheldon X.-D. Tan, Yici Cai, Shengqi Yang:
Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks. 1727-1732 - Hameedah Sultan, Smruti R. Sarangi:
A fast leakage aware thermal simulator for 3D chips. 1733-1738 - Sherief Reda, Adel Belouchrani:
Blind identification of power sources in processors. 1739-1744 - Chien-Pang Lu, Iris Hui-Ru Jiang:
Fast low power rule checking for multiple power domain design. 1745-1750 - Danil Sokolov, Vladimir Dubikhin, Victor Khomenko, David Lloyd, Andrey Mokhov, Alex Yakovlev:
Benefits of asynchronous control for analog electronics: Multiphase buck case study. 1751-1756 - Nai-Chen Chen, Pang-Yen Chou, Helmut E. Graeb, Mark Po-Hung Lin:
High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC. 1757-1762 - Shovan Maity, Debayan Das, Shreyas Sen:
Adaptive interference rejection in Human Body Communication using variable duty cycle integrating DDR receiver. 1763-1768 - Kaisheng Zeng, Youyou Lu, Hu Wan, Jiwu Shu:
Efficient storage management for aged file systems on persistent memory. 1769-1774 - Mohammad Samragh Razlighi, Mohsen Imani, Farinaz Koushanfar, Tajana Rosing:
LookNN: Neural network with no multiplication. 1775-1780 - Manuel Mohr, Carsten Tradowsky:
Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-cores. 1781-1786 - Mohamed Ibrahim, Krishnendu Chakrabarty:
Digital-microfluidic biochips for quantitative analysis: Bridging the Gap between microfluidics and microbiology. 1787-1792 - Jeffrey McDaniel, William H. Grover, Philip Brisk:
The case for semi-automated design of microfluidic very large scale integration (mVLSI) chips. 1793-1798 - Seetal Potluri, Alexander Schneider, Martin Horslev-Petersen, Paul Pop, Jan Madsen:
Synthesis of on-chip control circuits for mVLSI biochips. 1799-1804 - Yu-Jhih Chen, Sumit Sharma, Sudip Roy, Tsung-Yi Ho:
Scheduling and optimization of genetic logic circuits on flow-based microfluidic biochips. 1805-1810
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