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ORCIDSaeideh Shirinzadeh
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2020 – today
- 2024
[j6]Kousik Bhunia
, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler:
ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars. ACM Trans. Embed. Comput. Syst. 23(6): 90:1-90:24 (2024)- [c17]Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler:
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. VLSID 2024: 384-389 - 2023
- [c16]Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler:
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. ASP-DAC 2023: 19-25 - [c15]Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler:
Verification of In-Memory Logic Design using ReRAM Crossbars. NEWCAS 2023: 1-5 - 2022
- [j5]Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler:
Parallel Computing of Graph-based Functions in ReRAM. ACM J. Emerg. Technol. Comput. Syst. 18(2): 41:1-41:24 (2022) - [c14]Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler:
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles. DSD 2022: 793-800 - [c13]Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta, Rolf Drechsler:
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications. VLSI-SoC 2022: 1-6 - 2020
- [c12]Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler:
Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c11]Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler:
Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits. ISVLSI 2019: 431-436 - [c10]Steffen Frerix, Saeideh Shirinzadeh, Saman Fröhlich, Rolf Drechsler:
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing. NANOARCH 2019: 1-6 - 2018
- [b1]Saeideh Shirinzadeh:
Synthesis and optimization for logic-in-memory computing using memristive devices. University of Bremen, Germany, 2018, pp. 1-128 - [j4]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Logic Synthesis for RRAM-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1422-1435 (2018) - [c9]Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler:
Logic Design Using Memristors: An Emerging Technology. ISMVL 2018: 121-126 - [c8]Saeideh Shirinzadeh, Rolf Drechsler:
Logic Synthesis for In-memory Computing Using Resistive Memories. ISVLSI 2018: 375-380 - 2017
- [j3]Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli:
A PLiM Computer for the Internet of Things. Computer 50(6): 35-40 (2017) - [j2]Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler:
Synthesis of optical circuits using binary decision diagrams. Integr. 59: 42-51 (2017) - [c7]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler:
Endurance management for resistive Logic-In-Memory computing architectures. DATE 2017: 1092-1097 - [c6]Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler:
An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization. GECCO 2017: 1232-1239 - 2016
- [c5]Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli:
An MIG-based compiler for programmable logic-in-memory architectures. DAC 2016: 117:1-117:6 - [c4]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. DATE 2016: 948-953 - [c3]Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler:
Multi-objective BDD optimization for RRAM based circuit design. DDECS 2016: 46-51 - [c2]Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler:
Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. GECCO (Companion) 2016: 79-80 - 2015
- [c1]Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler:
Multi-Objective BDD Optimization with Evolutionary Algorithms. GECCO 2015: 751-758 - 2013
- [j1]Rahebeh Niaraki Asli, Saeideh Shirinzadeh:
High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design. J. Electron. Test. 29(4): 537-544 (2013)
Coauthor Index
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