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ORCIDAndrea Suardi
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2010 – 2019
- 2019
[j2]Kevin E. Murray
, Andrea Suardi, Vaughn Betz, George A. Constantinides:
Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 719-732 (2019)- 2017
- [c8]Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides:
Quantifying error: Extending static timing analysis with probabilistic transitions. DATE 2017: 1486-1491 - [i1]Bulat Khusainov, Eric C. Kerrigan, Andrea Suardi, George A. Constantinides:
Nonlinear Predictive Control on a Heterogeneous Computing Platform. CoRR abs/1710.08737 (2017) - 2015
- [c7]Eric C. Kerrigan, George A. Constantinides, Andrea Suardi, Andrea Picciau, Bulat Khusainov:
Computer architectures to close the loop in real-time optimization. CDC 2015: 4597-4611 - [c6]Andrea Suardi, Eric C. Kerrigan, George A. Constantinides:
Fast FPGA prototyping toolbox for embedded optimization. ECC 2015: 2589-2594 - 2014
- [j1]Edward Nicholas Hartley, Juan Luis Jerez, Andrea Suardi, Jan M. Maciejowski, Eric C. Kerrigan, George A. Constantinides:
Predictive Control Using an FPGA With Application to Aircraft Control. IEEE Trans. Control. Syst. Technol. 22(3): 1006-1017 (2014) - [c5]Sabato Manfredi, Andrea Suardi:
Optimization-based procedure to support sensor network co-design: An application to dynamic consensus problem. MED 2014: 698-703 - 2013
- [c4]Andrea Suardi, Stefano Longo, Eric C. Kerrigan, George A. Constantinides:
Energy-aware MPC co-design for DC-DC converters. ECC 2013: 3608-3613
2000 – 2009
- 2009
- [c3]Andrea Abba, Antonio Manenti, Andrea Suardi, Angelo Geraci, Giancarlo Ripamonti:
Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices. ERSA 2009: 240-246 - [c2]Andrea Suardi, Antonio Manenti, Andrea Abba, Angelo Geraci:
High-efficiency FPGA Fully-Based Implementation of the Conjugate Gradient Method. ERSA 2009: 247-253 - 2008
- [c1]Andrea Suardi, Antonio Manenti, Andrea Abba, Angelo Geraci:
High Performance Double Precision Reduction Circuit Implementation in FPGA. ERSA 2008: 298-301
Coauthor Index
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