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ORCIDManuel J. Barragan Asian
Manuel J. Barragán
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2020 – today
- 2024
[j24]Deni Germano Alves Neto
, Mohamed Khalil Bouchoucha, Gabriel Maranhão, Manuel J. Barragán, Márcio Cherem Schneider, Andreia Cathelin, Sylvain Bourdel, Carlos Galup-Montoro:
Design-Oriented Single-Piece 5-DC-Parameter MOSFET Model. IEEE Access 12: 87420-87437 (2024)- [j23]Julien Poupon, Manuel J. Barragan Asian, Andreia Cathelin, Sylvain Bourdel:
Design-Oriented Single-Piece Explicit I-V DC Charge-Based Model for MOS Transistors in Nanometric Technologies. IEEE Access 12: 147809-147827 (2024) - [j22]Sana Ibrahim, Ali Al Shakoush, Serge Subias, Loic Vincent, Manuel J. Barragan Asian, Laurent Fesquet, Florence Podevin, Sylvain Bourdel:
Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 3939-3950 (2024) - [j21]Florence Podevin, Imadeddine Bendjeddou, F. Mohsen, Catalin Andrei Dobrin, Sana Ibrahim, Ali Al Shakoush, M. Diallo, Jordan Corsi, Loic Vincent, Manuel J. Barragan Asian, Sylvain Bourdel:
N-Path Filtering and Mixing Analysis - A General Approach Based on Fourier Transform. IEEE Trans. Circuits Syst. I Regul. Pap. 71(12): 5636-5647 (2024) - [c61]Julien Poupon, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel:
Dynamic Analysis of RF CMOS Inverter-Based Ring Oscillators using an All-Region MOSFET Charge-Based Model in 28nm FD-SOI CMOS. ISCAS 2024: 1-5 - [c60]Olivier Occello, Marc Margalef-Rovira, Manuel J. Barragan Asian, C. Durand, A. Rhellab, Loic Vincent, Jordan Corsi, Sylvie Lépilliet, G. Ducournau, P. Ferrari:
Zero-Overhead Nonintrusive Test of mmW Integrated Circuits Based on Wafer-Level Parametric Tests. NewCAS 2024: 79-83 - [c59]Oumayma Belkhadra, Gilles Montoriol, Emmanuel Pistone, Hugo Vallee, Florent Cilici, Manuel J. Barragán, Salvador Mir, Sylvain Bourdel:
An Integrated Miniaturized VNA for On-Chip PA Mismatch Measurement. NewCAS 2024: 228-232 - [c58]Thalis Da C. Guedes, Johan Bourgeat, Manuel J. Barragán, Jean-Marc Duchamp, Philippe Ferrari:
Design and Evaluation of a 10 GHz LNA with Balun and Diodes for HBM and CDM ESD Protection in 28 nm CMOS FD-SOI. SBCCI 2024: 1-5 - 2023
- [j20]Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragán, Philippe Cathelin, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel:
Corrections to "Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge". IEEE Access 11: 39650 (2023) - [c57]Mohamed Khalil Bouchoucha, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel:
A wideband sub-6GHz continuously tunable gm-boosted CG Low Noise Amplifier in 28 nm FD-SOI CMOS technology. ESSCIRC 2023: 381-384 - [c56]Mohamed Khalil Bouchoucha, Mathieu Coustans, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel:
Performance benchmark of State-of-the-art Sub-6-GHz wideband LNAs Based on an Extensive Survey. ISCAS 2023: 1-5 - [c55]Mohamed Khalil Bouchoucha, Dayana A. Pino-Monroy, Patrick Scheer, Philippe Cathelin, Jean-Michel Fournier, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel:
Resistive Feedback LNA design using a 7-parameter design-oriented model for advanced technologies. ISCAS 2023: 1-5 - [c54]Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán:
A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell. ISCAS 2023: 1-5 - [c53]Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragán, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel:
Design-oriented model for short-channel MOS transistors based on inversion charge. LASCAS 2023: 1-4 - [c52]Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán:
Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. LATS 2023: 1-2 - [c51]Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán:
Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation. LATS 2023: 1-2 - [c50]Ankush Mamgain, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Jai Narayan Tripathi:
A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA. NEWCAS 2023: 1-5 - [c49]Deni Germano Alves Neto, Cristina Missel Adotnes, Gabriel Maranhão, Mohamed Khalil Bouchoucha, Manuel J. Barragán, Andreia Cathelin, Márcio Cherem Schneider, Sylvain Bourdel, Carlos Galup-Montoro:
A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE. NEWCAS 2023: 1-5 - 2022
- [j19]Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragán, Philippe Cathelin, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel:
Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge. IEEE Access 10: 86270-86285 (2022) - [c48]Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán:
On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators. ATS 2022: 43-48 - [c47]William R. Eisenstadt, Mark Roos, Devin Morris, José Luis González-Jiménez, Christopery Mounet, Manuel J. Barragán, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Salvador Mir, Sylvain Bourdel, Marc Margalef-Rovira, Issa Alaji, Haitham Ghanem, Guillaume Ducournau, Christophe Gaquière:
Special Session on RF/5G Test. ETS 2022: 1-9 - [c46]Gildas Léger, Antonio J. Ginés, Valentin Gutierrez, Manuel J. Barragán:
A methodology for defect detection in analog circuits based on causal feature selection. ICECS 2022 2022: 1-4 - [c45]Ali Al Shakoush, Sana Ibrahim, Serge Subias, Florence Podevin, Manuel J. Barragán, Dayana A. Pino-Monroy, Imadeddine Bendjeddou, Estelle Lauga-Larroze, Laurent Fesquet, Thierry Taris, Sylvain Bourdel:
N-Path Mixer with Wide Rejection Including the 7th Harmonic for Low Power Multi-standard Receivers. NEWCAS 2022: 256-260 - [c44]Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán:
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. VLSI-SoC 2022: 1-6 - [c43]Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS 2022: 1 - [d1]Mohamed Khalil Bouchoucha, Mathieu Coustans, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel:
A Survey on Sub-6 GHz Wideband LNAs for Ultra- Low-Power IoT applications. IEEE DataPort, 2022
- 2021
- [j18]Jean-Pierre David, Manuel J. Barragán:
Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3131-3132 (2021) - [j17]Marc Margalef-Rovira, Olivier Occello, Abdelhalim A. Saadi, Vanessa Avramovic, Sylvie Lépilliet, Loic Vincent, Manuel J. Barragán, Emmanuel Pistono, Sylvain Bourdel, Christophe Gaquière, Philippe Ferrari:
mm-Wave Through-Load Element for On-Wafer Measurement Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3170-3183 (2021) - [c42]Ankush Mamgain, Manuel J. Barragán, Salvador Mir:
Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation. ETS 2021: 1-6 - [c41]Sylvain Bourdel, Serge Subias, Mohamed Khalil Bouchoucha, Manuel J. Barragán, Andreia Cathelin, Carlos Galup-Montoro:
A gm/ID Design Methodology for 28 nm FD-SOI CMOS Resistive Feedback LNAs. ICECS 2021: 1-4 - [c40]Mohamad El-Chaar, Antonio Augusto Lisboa de Souza, Manuel J. Barragán, Florence Podevin, Sylvain Bourdel, Jean-Daniel Arnould:
Integrated Wideband Millimeter-Wave Bias-Tee - Application to Distributed Amplifier Biasing. NEWCAS 2021: 1-4 - [c39]Marc Margalef-Rovira, Christophe Gaquière, Antonio Augusto Lisboa de Souza, Loic Vincent, Manuel J. Barragán, Emmanuel Pistono, Florence Podevin, Philippe Ferrari:
mm-Wave Single-Pole Double-Throw switches: HBT- vs MOSFET-based designs. NEWCAS 2021: 1-4 - 2020
- [j16]Ekta Sharma, Abdelhalim A. Saadi, Marc Margalef-Rovira, Emmanuel Pistono, Manuel J. Barragán, Antonio Augusto Lisboa de Souza, Philippe Ferrari, Sylvain Bourdel:
Design of a 77-GHz LC-VCO With a Slow-Wave Coplanar Stripline-Based Inductor. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 378-388 (2020) - [c38]Renato S. Feitoza, Manuel J. Barragán, Antonio J. Ginés, Salvador Mir:
On-chip reduced-code static linearity test of Vcm-based switching SAR ADCs using an incremental analog-to-digital converter. ETS 2020: 1-2 - [c37]Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir:
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS 2020: 1-4 - [c36]Marc Margalef-Rovira, Abdelhalim A. Saadi, Sylvain Bourdel, Manuel J. Barragán, Emmanuel Pistono, Christophe Gaquière, Philippe Ferrari:
mm-Wave Through-Load Switch for in-situ Vector Network Analyzer on a 55-nm BiCMOS Technology. NEWCAS 2020: 82-85 - [c35]Renato S. Feitoza, Manuel J. Barragán, Antonio J. Ginés, Salvador Mir:
Static linearity BIST for Vcm-based switching SAR ADCs using a reduced-code measurement technique. NEWCAS 2020: 295-298
2010 – 2019
- 2019
- [j15]Guillaume Renaud, Mamadou Diallo, Manuel J. Barragán, Salvador Mir:
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 281-293 (2019) - [c34]Manuel J. Barragán, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Sylvain Bourdel, Salvador Mir:
On the use of causal feature selection in the context of machine-learning indirect test. DATE 2019: 276-279 - [c33]Hani Malloug, Manuel J. Barragán, Salvador Mir:
A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. ETS 2019: 1-6 - [c32]Florent Cilici, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel, Gildas Léger:
Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration. ISCAS 2019: 1-5 - [c31]Florent Cilici, Gildas Léger, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel:
Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits. SMACD 2019: 17-20 - [c30]Manuel J. Barragán, Gildas Léger:
Feature selection and feature design for machine learning indirect test: a tutorial review. SMACD 2019: 69-72 - [c29]Renato S. Feitoza, Manuel J. Barragán, Salvador Mir:
Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. VLSI-SoC 2019: 263-268 - 2018
- [j14]Ke Huang, Manuel J. Barragán:
Guest Editorial: Special Issue on Analog, Mixed-Signal, and RF Testing. J. Electron. Test. 34(3): 213-214 (2018) - [j13]Hani Malloug, Manuel J. Barragán, Salvador Mir:
Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. J. Electron. Test. 34(3): 263-279 (2018) - [c28]Florent Cilici, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel:
Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. ETS 2018: 1-6 - [c27]Renato S. Feitoza, Manuel J. Barragán, Salvador Mir, Daniel Dzahini:
Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter. IOLTS 2018: 29-34 - [c26]Gildas Léger, Manuel J. Barragán:
Mixed-signal test automation: Are we there yet? ISCAS 2018: 1-5 - [c25]Marc Margalef-Rovira, Manuel J. Barragán, Ekta Sharma, Philippe Ferrari, Emmanuel Pistono, Sylvain Bourdel:
An oscillation-based test technique for on-chip testing of mm-wave phase shifters. VTS 2018: 1-6 - 2017
- [j12]Manuel J. Barragán, William R. Eisenstadt:
Guest Editorial: Analog, Mixed-Signal and RF Testing. J. Electron. Test. 33(3): 281-282 (2017) - [c24]Manuel J. Barragán, Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda:
On the limits of machine learning-based test: A calibrated mixed-signal system case study. DATE 2017: 79-84 - [c23]Hani Malloug, Manuel J. Barragan Asian, Salvador Mir, Laurent Basteres, Hervé Le Gall:
Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. ETS 2017: 1-6 - [c22]Michele Portolan, Manuel J. Barragán, Rshdee Alhakim, Salvador Mir:
Mixed-signal BIST computation offloading using IEEE 1687. ETS 2017: 1-2 - [c21]Guillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragán, Salvador Mir:
Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. VTS 2017: 1-6 - 2016
- [j11]Manuel J. Barragán, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal:
Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. IEEE Des. Test 33(6): 46-54 (2016) - [j10]Guillaume Renaud, Manuel J. Barragán, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet:
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. 32(4): 407-421 (2016) - [j9]Gildas Léger, Manuel J. Barragán:
Brownian distance correlation-directed search: A fast feature selection technique for alternate test. Integr. 55: 401-414 (2016) - [j8]Manuel J. Barragán, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal:
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1876-1888 (2016) - [c20]Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragán, Salvador Mir:
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. ETS 2016: 1-6 - [c19]Gildas Léger, Manuel J. Barragán:
Questioning the reliability of Monte Carlo simulation for machine learning test validation. ETS 2016: 1-6 - 2015
- [j7]Manuel J. Barragan Asian, Gildas Léger:
A Procedure for Alternate Test Feature Design and Selection. IEEE Des. Test 32(1): 18-25 (2015) - [c18]Manuel J. Barragán, Gildas Léger:
Feature selection for alternate test using wrappers: application to an RF LNA case study. DATE 2015: 1229-1232 - [c17]Haralampos-G. D. Stratigopoulos, Manuel J. Barragán, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal:
Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. ITC 2015: 1-7 - [c16]Manuel J. Barragán, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter:
Special session: Hot topics: Statistical test methods. VTS 2015: 1-2 - 2014
- [c15]Guillaume Renaud, Manuel J. Barragán, Salvador Mir, Marc Sabut:
On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. ATS 2014: 212-217 - [c14]Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán:
Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. VLSI-SoC 2014: 1-6 - [c13]Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán:
Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST. VLSI-SoC (Selected Papers) 2014: 129-148 - 2013
- [c12]Manuel J. Barragan Asian, Gildas Léger:
Efficient selection of signatures for analog/RF alternate test. ETS 2013: 1-6 - [c11]Manuel J. Barragán, Gildas Léger, Diego Vázquez, Adoración Rueda:
Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique. LASCAS 2013: 1-4 - 2012
- [j6]Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez:
Digital Adaptive Calibration of Multi-Step Analog to Digital Converters. J. Low Power Electron. 8(2): 182-196 (2012) - [j5]Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez:
Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS. IEEE Trans. Instrum. Meas. 61(8): 2212-2221 (2012) - [c10]Manuel J. Barragan Asian, Gildas Léger, José L. Huertas:
OBT for settling error test of sampled-data systems using signal-dependent clocking. ETS 2012: 1-6 - [c9]Manuel J. Barragan Asian, Gildas Léger, José Luis Huertas:
Multi-condition alternate test of analog, mixed-signal, and RF systems. LATW 2012: 1-6 - 2011
- [j4]Manuel J. Barragan Asian, Rafaella Fiorelli, Gildas Léger, Adoración Rueda, José L. Huertas:
Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures. J. Electron. Test. 27(3): 277-288 (2011) - [j3]Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda:
Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications. J. Electron. Test. 27(3): 305-320 (2011) - [c8]Manuel J. Barragan Asian, Rafaella Fiorelli, Gildas Léger, Adoración Rueda, José L. Huertas:
Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs. Asian Test Symposium 2011: 359-364 - 2010
- [j2]Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda:
A BIST Solution for Frequency Domain Characterization of Analog Circuits. J. Electron. Test. 26(4): 429-441 (2010) - [c7]Manuel J. Barragan Asian, Gloria Huertas, Adoración Rueda, José Luis Huertas:
(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems. DELTA 2010: 8-13 - [c6]Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas:
Low-cost signature test of RF blocks based on envelope response analysis. ETS 2010: 55-60 - [c5]Antonio J. Ginés, Ricardo Doldán, Manuel J. Barragan Asian, Adoración Rueda, Eduardo J. Peralías:
On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation. ISCAS 2010: 1979-1982
2000 – 2009
- 2009
- [c4]Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas:
A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis. Asian Test Symposium 2009: 255-260 - 2008
- [c3]Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda:
Practical Implementation of a Network Analyzer for Analog BIST Applications. DATE 2008: 80-85 - 2007
- [c2]Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez:
Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. DATE 2007: 1301-1306 - 2006
- [c1]Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda:
A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35µm Technology. DDECS 2006: 119-124 - 2005
- [j1]Diego Vázquez, Gloria Huertas, África Luque, Manuel J. Barragan Asian, Gildas Léger, Adoración Rueda, José Luis Huertas:
Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST. J. Electron. Test. 21(3): 221-232 (2005)
Coauthor Index
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