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ORCIDAdit D. Singh
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- affiliation: Auburn University, USA
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2020 – today
- 2024
[c123]Adit D. Singh:
Silent Data Corruption from Timing Marginalities Due to Process Variations. ETS 2024: 1-7- [c122]Arani Sinha, Adit D. Singh:
Innovative Practices Track: Session 2 Silent Data Corruption. VTS 2024: 1 - 2023
- [c121]Adit D. Singh:
Silent Error Corruption: The New Reliability and Test Challenge. LATS 2023: 1-2 - [c120]Adit D. Singh, Sreejit Chakravarty, George Papadimitriou, Dimitris Gizopoulos:
Silent Data Errors: Sources, Detection, and Modeling. VTS 2023: 1-12 - 2022
- [j32]Wendong Wang
, Adit D. Singh, Ujjwal Guin:
A Systematic Bit Selection Method for Robust SRAM PUFs. J. Electron. Test. 38(3): 235-246 (2022) - [c119]Adit D. Singh:
Understanding Vmin Failures for Improved Testing of Timing Marginalities. ITC 2022: 372-381 - 2021
- [j31]Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal:
Estimating Operational Age of an Integrated Circuit. J. Electron. Test. 37(1): 25-40 (2021) - [j30]Sabyasachi Deyati, Barry J. Muldrey, Adit D. Singh, Abhijit Chatterjee:
High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems. J. Electron. Test. 37(1): 41-63 (2021) - [c118]Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee:
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. VTS 2021: 1-7 - [i1]Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner:
Exploring the Mysteries of System-Level Test. CoRR abs/2103.06656 (2021) - 2020
- [j29]Wendong Wang, Ujjwal Guin, Adit D. Singh:
Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices. J. Electron. Test. 36(3): 301-311 (2020) - [c117]Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner:
Exploring the Mysteries of System-Level Test. ATS 2020: 1-6 - [c116]Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee:
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. ITC 2020: 1-10 - [c115]Wendong Wang, Ujjwal Guin, Adit D. Singh:
A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture. VTS 2020: 1-6
2010 – 2019
- 2019
- [c114]Ujjwal Guin, Wendong Wang, Charles Harper, Adit D. Singh:
Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells. HOST 2019: 72-80 - [c113]Adit D. Singh:
An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures. ITC 2019: 1-10 - [c112]Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal:
Two-Pattern ∆IDDQ Test for Recycled IC Detection. VLSID 2019: 82-87 - 2018
- [j28]Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker:
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2152-2165 (2018) - [j27]Ujjwal Guin, Ziqi Zhou, Adit D. Singh:
Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 818-830 (2018) - [c111]Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Francky Catthoor, Abhijit Chatterjee, Adit D. Singh, Hans-Joachim Wunderlich, Naghmeh Karimi:
Device aging: A reliability and security concern. ETS 2018: 1-10 - [c110]Wendong Wang, Adit D. Singh, Ujjwal Guin, Abhijit Chatterjee:
Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs. LATS 2018: 1-6 - [c109]Ujjwal Guin, Adit D. Singh, Mahabubul Alam, Janice Canedo, Anthony Skjellum:
A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things. VLSID 2018: 85-90 - 2017
- [j26]Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja:
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. J. Electron. Test. 33(6): 721-739 (2017) - [c108]Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker:
Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. DATE 2017: 422-427 - [c107]Bernd Becker, Adit D. Singh:
Best paper. ETS 2017: 1 - [c106]Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja:
Exploiting path delay test generation to develop better TDF tests for small delay defects. ITC 2017: 1-10 - [c105]Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja:
Identifying high variability speed-limiting paths under aging. LATS 2017: 1-6 - [c104]Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker:
Efficient SAT-based generation of hazard-activated TSOF tests. VTS 2017: 1-6 - [c103]Ujjwal Guin, Ziqi Zhou, Adit D. Singh:
A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction. VTS 2017: 1-6 - 2016
- [c102]Sujay Pandey, Sabyasachi Deyati, Adit D. Singh, Abhijit Chatterjee:
Noise-Resilient SRAM Physically Unclonable Function Design for Security. ATS 2016: 55-60 - [c101]Adit D. Singh:
Cell Aware and stuck-open tests. ETS 2016: 1-6 - [c100]Adit D. Singh:
Adaptive Test Methods for High IC Quality and Reliability. VLSID 2016: 21-22 - 2015
- [c99]Virendra Singh, Adit D. Singh, Kewal K. Saluja:
A Methodology for Identifying High Timing Variability Paths in Complex Designs. ATS 2015: 115-120 - [c98]Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee:
Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security. ATS 2015: 127-132 - [c97]Adit D. Singh:
Scan based two-pattern tests: should they target opens instead of TDFs? LATS 2015: 1-2 - [c96]Adit D. Singh:
Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs. VLSID 2015: 19-20 - [c95]Yu Wang, Adit D. Singh:
An Efficient Transition Detector Exploiting Charge Sharing. VLSID 2015: 298-303 - [c94]Manuel J. Barragán, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter:
Special session: Hot topics: Statistical test methods. VTS 2015: 1-2 - [c93]Chao Han, Adit D. Singh:
Testing cross wire opens within complex gates. VTS 2015: 1-6 - 2014
- [c92]Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee:
High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. ATS 2014: 200-205 - [c91]Jie Zou, Chao Han, Adit D. Singh:
Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing. ATS 2014: 281-286 - [c90]Ilia Polian, Jie Jiang, Adit D. Singh:
Detection conditions for errors in self-adaptive better-than-worst-case designs. ETS 2014: 1-6 - [c89]Adit D. Singh:
Error detection and recovery in better-than-worst-case timing designs. ETS 2014: 1-6 - [c88]Chao Han, Adit D. Singh:
On the testing of hazard activated open defects. ITC 2014: 1-6 - [c87]Jayaram Natarajan, Sahil Kapoor, Debesh Bhatta, Abhijit Chatterjee, Adit D. Singh:
Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience. VLSID 2014: 122-127 - [c86]Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian:
Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. VLSID 2014: 133-138 - [c85]Chao Han, Adit D. Singh:
Improving CMOS open defect coverage using hazard activated tests. VTS 2014: 1-6 - 2013
- [c84]Chao Han, Adit D. Singh:
Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects. Asian Test Symposium 2013: 189-194 - [c83]Hans A. R. Manhaeve, Pete Harrod, Adit D. Singh, Chintan Patel, Ralf Arnolc, Davide Appello:
Current testing: Dead or alive? ETS 2013: 1 - [c82]Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören:
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC 2013 - [c81]Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee:
A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. VLSI Design 2013: 109-114 - [c80]Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia:
Special session 4B: Elevator talks. VTS 2013: 1 - [e1]Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi, Dharmendar Boolchandani, Virendra Singh, Adit D. Singh:
VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers. Communications in Computer and Information Science 382, Springer 2013, ISBN 978-3-642-42023-8 [contents] - 2012
- [c79]Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita:
SEU tolerant robust memory cell design. IOLTS 2012: 13-18 - [c78]Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita:
SEU Tolerant Robust Latch Design. VDAT 2012: 223-232 - [c77]Xi Qian, Chao Han, Adit D. Singh:
Detection of gate-oxide defects with timing tests at reduced power supply. VTS 2012: 120-126 - 2011
- [c76]Mohammed Abdul Razzaq, Virendra Singh, Adit D. Singh:
SSTKR: Secure and Testable Scan Design through Test Key Randomization. Asian Test Symposium 2011: 60-65 - [c75]Jayaram Natarajan, Joshua W. Wells, Abhijit Chatterjee, Adit D. Singh:
Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations. Asian Test Symposium 2011: 154-160 - [c74]Xi Qian, Adit D. Singh, Abhijit Chatterjee:
Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations. Asian Test Symposium 2011: 303-310 - [c73]Kautalya Mishra, Ahmed Faraz, Adit D. Singh:
Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations. VLSI Design 2011: 382-388 - 2010
- [j25]Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh:
Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 675-679 (2010) - [c72]Balapradeep Gadamsetti, Adit D. Singh:
Current Sensing Completion Detection for high speed and area efficient arithmetic. APCCAS 2010: 240-243 - [c71]Xi Qian, Adit D. Singh:
Distinguishing Resistive Small Delay Defects from Random Parameter Variations. Asian Test Symposium 2010: 325-330 - [c70]Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh:
Modified Scan Flip-Flop for Low Power Testing. Asian Test Symposium 2010: 367-370 - [c69]Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli:
Adapting to adaptive testing. DATE 2010: 556-561 - [c68]Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh:
Modified T-Flip-Flop based scan cell for RAS. ETS 2010: 113-118 - [c67]A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh:
Test application time minimization for RAS using basis optimization of column decoder. ISCAS 2010: 2614-2617 - [c66]Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh:
On Minimization of Test Application Time for RAS. VLSI Design 2010: 393-398 - [c65]Adit D. Singh, Chao Han, Xi Qian:
An output compression scheme for handling X-states from over-clocked delay tests. VTS 2010: 57-62
2000 – 2009
- 2009
- [c64]K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh:
Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. Asian Test Symposium 2009: 237-240 - [c63]Adit D. Singh:
A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. DFT 2009: 422-422 - [c62]Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Christos A. Papachristou:
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. IOLTS 2009: 129 - [c61]Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal:
Output Hazard-Free Transition Delay Fault Test Generation. VTS 2009: 97-102 - 2008
- [c60]Adit D. Singh:
Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects. ITC 2008: 1-8 - [c59]Adit D. Singh:
Scan Delay Testing of Nanometer SoCs. VLSI Design 2008: 13 - [c58]Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee:
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. VLSI Design 2008: 27-32 - 2007
- [j24]Gefu Xu, Adit D. Singh:
Scan cell design for launch-on-shift delay tests with slow scan enable. IET Comput. Digit. Tech. 1(3): 213-219 (2007) - [c57]Gefu Xu, Adit D. Singh:
Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan. ATS 2007: 335-340 - [c56]Gefu Xu, Adit D. Singh:
Achieving high transition delay fault coverage with partial DTSFF scan chains. ITC 2007: 1-9 - [c55]Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril:
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. VLSI Design 2007: 711-716 - [c54]Gefu Xu, Adit D. Singh:
Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. VLSI Design 2007: 763-768 - 2006
- [j23]Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh:
Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction. IEEE Des. Test Comput. 23(2): 110-116 (2006) - [j22]Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh:
New JETTA Editors, 2006. J. Electron. Test. 22(1): 9-10 (2006) - [j21]Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee:
Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects. J. Electron. Test. 22(4-6): 471-482 (2006) - [j20]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 514-524 (2006) - [j19]Haihua Yan, Adit D. Singh:
A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI). IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1216-1226 (2006) - [c53]Gefu Xu, Adit D. Singh:
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. ETS 2006: 9-14 - [c52]Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak:
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design 2006: 606-612 - [c51]Adit D. Singh, Gefu Xu:
Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. VTS 2006: 349-357 - 2005
- [j18]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Pseudo Dual Supply Voltage Domino Logic Design. J. Low Power Electron. 1(2): 145-152 (2005) - [j17]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1103-1107 (2005) - [c50]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Low-power domino circuits using NMOS pull-up on off-critical paths. ASP-DAC 2005: 533-538 - [c49]Adit D. Singh:
T2: Statistical Methods for VLSI Test and Burn-in Optimization. Asian Test Symposium 2005 - [c48]Haihua Yan, Adit D. Singh, Gefu Xu:
Delay Defect Characterization Using Low Voltage Test. Asian Test Symposium 2005: 8-13 - [c47]Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De:
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. ICCD 2005: 567-573 - [c46]Haihua Yan, Gefu Xu, Adit D. Singh:
Low Voltage Test in Place of Fast Clock in DDSI Delay Test. ISQED 2005: 316-320 - [c45]Adit D. Singh:
A self-timed structural test methodology for timing anomalies due to defects and process variations. ITC 2005: 7 - [c44]Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh:
A random access scans architecture to reduce hardware overhead. ITC 2005: 9 - [c43]Haihua Yan, Adit D. Singh:
A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. VLSI Design 2005: 47-52 - [c42]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. VLSI Design 2005: 159-164 - [c41]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. VTS 2005: 298-303 - 2004
- [c40]Haihua Yan, Adit D. Singh:
Reduce Yield Loss in Delay Defect Detection in Slack Interval. Asian Test Symposium 2004: 372-377 - [c39]Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh:
Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits. ETS 2004: 24-29 - [c38]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Sizing CMOS Circuits for Increased Transient Error Tolerance. IOLTS 2004: 11-16 - [c37]Haihua Yan, Adit D. Singh:
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. ITC 2004: 242-251 - [c36]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Low-power dual Vth pseudo dual Vdd domino circuits. SBCCI 2004: 273-277 - 2003
- [j16]Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan:
Multimode scan: Test per clock BIST for IP cores. ACM Trans. Design Autom. Electr. Syst. 8(4): 491-505 (2003) - [j15]Thomas S. Barnett, Adit D. Singh, Victor P. Nelson:
Extending integrated-circuit yield-models to estimate early-life reliability. IEEE Trans. Reliab. 52(3): 296-300 (2003) - [c35]Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa:
IC Reliability Simulator ARET and Its Application in Design-for-Reliability. Asian Test Symposium 2003: 18-23 - [c34]Adit D. Singh:
Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization". ISQED 2003: 7 - [c33]Thomas S. Barnett, Adit D. Singh:
Relating Yield Models to Burn-In Fall-Out in Time. ITC 2003: 77-84 - [c32]Haihua Yan, Adit D. Singh:
Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die. ITC 2003: 105-111 - [c31]Adit D. Singh:
Should Nanometer Circuits be Periodically Tested in the Field? ITC 2003: 1280 - 2002
- [c30]Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh:
Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. ITC 2002: 693-699 - [c29]Michael Gössel, Egor S. Sogomonyan, Adit D. Singh:
Scan-Path with Directly Duplicated and Inverted Duplicated Registers. VTS 2002: 47-52 - [c28]Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy:
Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. VTS 2002: 75-80 - 2001
- [c27]Thomas S. Barnett, Adit D. Singh, Victor P. Nelson:
Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. DFT 2001: 29-38 - [c26]Thomas S. Barnett, Adit D. Singh, Victor P. Nelson:
Estimating burn-in fall-out for redundant memory. ITC 2001: 340-347 - [c25]Egor S. Sogomonyan, Andrej A. Morosov, Jan Rzeha, Michael Gössel, Adit D. Singh:
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging. VTS 2001: 184-189 - [c24]Thomas S. Barnett, Adit D. Singh, Victor P. Nelson:
Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model. VTS 2001: 326-332
1990 – 1999
- 1999
- [j14]Egor S. Sogomonyan, Adit D. Singh, Michael Gössel:
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. J. Electron. Test. 15(1-2): 87-96 (1999) - [c23]David R. Lakin II, Adit D. Singh:
Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study. ITC 1999: 23-30 - [c22]Adit D. Singh, Egor S. Sogomonyan, Michael Gössel, Markus Seuring:
Testability evaluation of sequential designs incorporating the multi-mode scannable memory element. ITC 1999: 286-293 - 1998
- [j13]Christopher G. Knight, Adit D. Singh, Victor P. Nelson:
An IDDQ sensor for concurrent timing error detection. IEEE J. Solid State Circuits 33(10): 1545-1550 (1998) - [c21]Adit D. Singh, David R. Lakin II, Gaurav Sinha, Phil Nigh:
Binning for IC Quality: Experimental Studies on the SEMATECH Data. DFT 1998: 4-10 - [c20]Egor S. Sogomonyan, Adit D. Singh, Michael Gössel:
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. VTS 1998: 324-331 - 1997
- [j12]Walter W. Weber, Adit D. Singh:
Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study. J. Electron. Test. 11(2): 147-156 (1997) - [j11]Jason P. Hurst, Adit D. Singh:
A differential built-in current sensor design for high-speed IDDQ testing. IEEE J. Solid State Circuits 32(1): 122-125 (1997) - [c19]Christopher G. Knight, Adit D. Singh, Victor P. Nelson:
An IDDQ Sensor for Concurrent Timing Error Detection. DFT 1997: 281-289 - [c18]Adit D. Singh, Phil Nigh, C. Mani Krishna:
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study. ITC 1997: 362-369 - 1996
- [j10]Adit D. Singh, C. Mani Krishna:
On the Effect of Defect Clustering on Test Transparency and IC Test Optimization. IEEE Trans. Computers 45(6): 753-757 (1996) - 1995
- [j9]Jae Young Lee, Hee Yong Youn, Adit D. Singh:
Adaptive Unanimous Voting (UV) Scheme for Distributed Self-Diagnosis. IEEE Trans. Computers 44(5): 730-735 (1995) - [c17]Adit D. Singh:
ADTS: an array defect-tolerance scheme for wafer scale gate arrays. DFT 1995: 126-136 - [c16]Adit D. Singh, Haroon Rasheed, Walter W. Weber:
IDDQ Testing of CMOS Opens: An Experimental Study. ITC 1995: 479-489 - [c15]Jason P. Hurst, Adit D. Singh:
A differential built-in current sensor design for high speed IDDQ testing. VLSI Design 1995: 419-423 - [c14]Walter W. Weber, Adit D. Singh:
An experimental evaluation of the differential BICS for IDDQ testing. VTS 1995: 472-485 - 1994
- [c13]Adit D. Singh, Jason P. Hurst:
Incorporating IDDQ testing in BIST: improved coverage through test diversity. VTS 1994: 374-379 - 1993
- [j8]Adit D. Singh, C. Mani Krishna:
On optimizing VLSI testing for product quality using die-yield prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 695-709 (1993) - [c12]Jae Young Lee, Hee Yong Youn, Adit D. Singh:
Adaptive Voting for Faulty (VFF) Node Scheme for Distributed Self-Diagnosis. FTCS 1993: 480-489 - [c11]Adit D. Singh, C. Mani Krishna:
The effect of defect clustering on test transparency and defect levels. VTS 1993: 99-105 - 1992
- [c10]Adit D. Singh, C. Mani Krishna:
Chip Test Optimization Using Defect Clustering Information. FTCS 1992: 366-373 - [c9]C. Mani Krishna, Adit D. Singh:
Analysis of the die test optimization algorithm for negative binomial yield statistics. VTS 1992: 176-181 - 1991
- [j7]Adit D. Singh, Hee Yong Youn:
A Modular Fault-Tolerant Binary Tree Architecture with Short Links. IEEE Trans. Computers 40(7): 882-890 (1991) - [c8]Adit D. Singh, C. Mani Krishna:
On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction. ITC 1991: 228-237 - 1990
- [j6]Adit D. Singh, Singaravel Murugesan:
Fault-Tolerant Systems - Guest Editors' Introduction to the Special Issue. Computer 23(7): 15-17 (1990) - [j5]Israel Koren, Adit D. Singh:
Fault Tolerance in VLSI Circuits. Computer 23(7): 73-83 (1990)
1980 – 1989
- 1989
- [j4]Abraham Mendelson, Dhiraj K. Pradhan, Adit D. Singh:
A single cached copy data coherence scheme for multiprocessor systems. SIGARCH Comput. Archit. News 17(6): 36-49 (1989) - [j3]Hee Yong Youn, Adit D. Singh:
On Implementing Large Binary Tree Architectures in VLSI and WSI. IEEE Trans. Computers 38(4): 526-537 (1989) - [c7]C. Mani Krishna, Adit D. Singh:
Modelling correlated transient failures in fault-tolerant systems. FTCS 1989: 374-381 - [c6]Hee Yong Youn, Adit D. Singh:
An efficient channel routing algorithm for defective arrays. ICCAD 1989: 432-435 - [c5]Hee Yong Youn, Adit D. Singh:
A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI. ICPP (1) 1989: 261-265 - 1988
- [j2]Adit D. Singh:
Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays. IEEE Trans. Computers 37(11): 1398-1410 (1988) - [c4]Hee Yong Youn, Adit D. Singh:
Near Optimal Embedding of Binary Tree Architecture in VLSI. ICDCS 1988: 86-93 - [c3]Hee Yong Youn, Adit D. Singh:
A Highly Efficient Design for Reconfiguring the Processor Array in VLSI. ICPP (1) 1988: 375-382 - 1987
- [c2]Hee Yong Youn, Adit D. Singh:
On Area Efficient and Fault Tolerant Tree Embedding In VLSI. ICPP 1987: 170-177 - 1981
- [j1]Adit D. Singh, F. Gail Gray, James R. Armstrong:
Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules. IEEE Trans. Computers 30(9): 671-674 (1981)
1970 – 1979
- 1978
- [c1]Adit D. Singh, James R. Armstrong:
A simultaneous, radix four, I2L multiplier mechanized via repeated addition. MVL 1978: 114-121
Coauthor Index
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