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ORCIDVTS 1992: Atlantic City, NJ, USA
- 10th IEEE VLSI Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic City, NJ, USA. IEEE Computer Society 1992, ISBN 0-7803-0623-6
- Yuejian Wu, André Ivanov:
Accelerated path delay fault simulation. 1-6 - Irith Pomeranz, Sudhakar M. Reddy:
Generalization of independent faults for transition faults. 7-12 - Yukiko Izuta, Fumiyasu Hirose:
Test pattern generation system for delay faults using a high speed simulation processor 'SP'. 13-18 - Prab Varma:
On test generation for path delay faults in ASICs. 19-24 - Rabindra K. Roy, Naveena Nagi, Abhijit Chatterjee, Manuel A. d'Abreu:
Delay fault testing of iterative arithmetic arrays. 25-30 - Michael M. Y. Hui, Benoit Nadeau-Dostie:
Scan testing of latch arrays. 31-36 - Oliver F. Haberl, Thomas Kropf:
A methodology for the insertion of a hierarchical and boundary-scan compatible self test. 37-42 - Nazar S. Haider, Nick Kanopoulos:
The split boundary scan register technique for testing board interconnects. 43-48 - Rajesh Gupta, Melvin A. Breuer:
Testability properties of acyclic structures and applications to partial scan design. 49-54 - Dhiraj K. Pradhan, Jayashree Saxena:
A design for testability scheme to reduce test application time in full scan. 55-60 - Geetani Edirisooriya, John P. Robinson:
Design of low cost ROM based test generators. 61-66 - Peter A. Johnson, F. Joel Ferguson:
On the effectiveness of simultaneous self-test techniques. 67-72 - Alicja Pierzynska, Slawomir Pilarski:
Built-in self-test design for large embedded PLAs. 73-78 - Prawat Nagvajara, Mark G. Karpovsky:
Coset error detection in BIST design. 79-83 - Mark F. Abate:
A mixed signal tester solution for: standards traceable AC calibration of analog modules. 84-89 - C. Counil, Gaston Cambon:
A functional BIST approach for FIR digital filters. 90-95 - Naveena Nagi, Jacob A. Abraham:
Hierarchical fault modeling for analog and mixed-signal circuits. 96-101 - José Luis Huertas, Diego Vázquez, Adoración Rueda:
On-line testing of switched-capacitor filters. 102-106 - Ben Mathew, Daniel G. Saab:
Robust switch-level test generation. 107-112 - Shunichi Toida, Nageswara S. V. Rao:
On test generation for combinational circuits consisting of AND and EXOR gates. 113-118 - S. Wayne Bollinger, Scott F. Midkiff:
An investigation of circuit partitioning for parallel test generation. 119-124 - Kyuchull Kim, Kewal K. Saluja:
On fault deletion problem in concurrent fault simulation for synchronous sequential circuits. 125-130 - Tales Cleber Pimenta, M. Ebrahim Mokari:
Design of reduced testing for VLSI circuits based on linear code theory. 131-136 - Lew Fock Chong Lew Yan Voon, Christian Dufaza, Christian Landrault:
BIST linear generator based on complemented outputs. 137-142 - Warren H. Debany Jr., Mark Gorniak, Daniel Daskiewich, Anthony R. Macera, Kevin A. Kwiat, Heather B. Dussault:
Empirical bounds on fault coverage loss due to LFSR aliasing. 143-148 - Mark G. Karpovsky, Saeed M. Chaudhry:
Built-in self-diagnostic by space-time compression of test responses. 149-154 - Manjit S. Cheema, Parag K. Lala:
A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults. 155-159 - B. Kolla, Parag K. Lala, K. C. Yarlagadda:
A concurrent checking scheme for single and multibit errors in logic circuits. 160-164 - Steven W. Burns, Niraj K. Jha:
A totally self-checking checker for a parallel unordered coding scheme. 165-170 - Kazuhiko Iwasaki, Toru Fujiwara, Tadao Kasami:
A defect-tolerant design for mask ROMs. 171-175 - C. Mani Krishna, Adit D. Singh:
Analysis of the die test optimization algorithm for negative binomial yield statistics. 176-181 - Ken-ichi Imamiya, Jun-ichi Miyamoto, Nobuaki Ohtuska, Naoto Tomita, Yumiko Iyama:
Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation. 182-187 - Yi-Nan Shen, Fabrizio Lombardi:
Detection of multiple faults in CMOS circuits using a behavioral approach. 188-193 - Angus Wu
, Jack L. Meador:
Data driven neural-based measurement discrimination for IC parametric faults diagnosis. 194-197 - James L. Schafer, Fred A. Policastri, Richard J. McNulty:
Partner SRLs for improved shift register diagnostics. 198-201 - Ibrahim N. Hajj, Terry Lee:
Simulation of physical faults in VLSI circuits. 202-207 - Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross:
The roles of controllability and observability in design for test. 211-216 - Aly Ezzat Salama, Mohamed I. Elmasry:
Testing and design for testability of BiCMOS logic circuits. 217-222 - Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel:
Probe point insertion for at-speed test. 223-228 - Shyang-Tai Su, Rafic Z. Makki:
A testable static RAM structure for efficient coverage of pattern sensitive faults. 229-234 - Sandeep K. Gupta:
Recent advances in BIST. 235-240 - Kwang-Ting Cheng:
Recent advances in sequential test generation. 241-246 - Jacob Savir:
Developments in delay testing. 247-253 - Janusz Rajski, Jagadeesh Vasudevamurthy, Aiman El-Maleh:
Recent advances in logic synthesis with testability. 254-256 - Enrico Macii, Angelo Raffaele Meo:
Techniques to increase sequential ATPG performance. 257-262 - Paolo Camurati, Fulvio Corno, Fulvio Prinetto, Matteo Sonza Reorda:
A simulation-based approach to test pattern generation for synchronous sequential circuits. 263-267 - Prem R. Menon, Hitesh Ahuja:
Redundancy removal and simplification of combinational circuits. 268-273 - David M. Wu, Robert M. Swanson:
Multiple redundancy removal during test generation and synthesis. 274-279 - Warren H. Debany Jr., Anthony R. Macera, Daniel Daskiewich, Mark Gorniak, Kevin A. Kwiat, Heather B. Dussault:
Effective concurrent test for a parallel-input multiplier using modulo 3. 280-285 - Abhijit Chatterjee:
Checksum-based concurrent error detection in linear analog systems with second and higher order stages. 286-291 - Parameswaran Ramanathan, Kewal K. Saluja, Michael J. Franklin:
Zero cost testing of check bits in RAMs with on-chip ECC. 292-297 - Egor S. Sogomonyan, Michael Gössel:
Self-testing and self-checking combinational circuits with weakly independent outputs. 298-303 - Qiao Tong:
Built-in current self-testing scheme (BICST) for CMOS logic circuits. 304-308 - Tung-Li Shen, James C. Daly, Jien-Chung Lo:
On-chip current sensing circuit for CMOS VLSI. 309-314 - Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana:
Behavior of faulty single BJT BiCMOS logic gates. 315-320 - Emmanuel Simeu, Anura Puissochet, Jean-Luc Rainard, Anne-Marie Tagant, Michel Poize:
A new tool for random testability evaluation using simulation and formal proof. 321-326 - David A. Zein, Oliver P. Engel, Gary S. Ditlow:
Algorithms for the design verification of bipolar array chips. 327-332 - David A. Zein, Oliver P. Engel, Gary S. Ditlow:
HLSIM-a new hierarchical logic simulator in APL. 333-338 - Michael Nicolaidis:
Improving the theory of truth table verification of iterative logic arrays. 339-344
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