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ORCIDNick Kanopoulos
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2000 – 2009
- 2004
[c15]Nick Kanopoulos:
Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization. PATMOS 2004: 2- 2000
- [c14]Kostas Adaos, George Alexiou, Nick Kanopoulos:
Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures. ICECS 2000: 567-570
1990 – 1999
- 1999
- [c13]Kostas Adaos, G. Ph. Alexiou, Nikos Kanopoulos:
Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing. ICECS 1999: 33-36 - [r1]Nick Kanopoulos:
Testability Concepts and DFT. The VLSI Handbook 1999 - 1998
- [j20]Theodore Karoubalis, George Alexiou, Nick Kanopoulos:
A dual rail circuits synthesis environment for the implementation of multiple output boolean functions. Int. J. Circuit Theory Appl. 26(4): 329-342 (1998) - [c12]Kostas Adaos, George Alexiou, Nick Kanopoulos:
An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs. International Workshop on Rapid System Prototyping 1998: 78-83 - 1996
- [c11]Tassos Markas, E. Edwards, S. Wang, J. Medero, Nick Kanopoulos:
Automatic synthesis of an 8-bit CPU with 100% on-line error detection capability. ICECS 1996: 968-971 - [c10]W. Weber, Michael G. McNamer, Nick Kanopoulos:
TESPAD: a testability specifications advisor for a structured test methodology. ICECS 1996: 1068-1071 - [c9]Theodoros Antonakopoulos, C. Powers, Nick Kanopoulos:
A versatile wireless system for real-time telemetry applications. ICECS 1996: 1194-1197 - 1995
- [j19]Apostolos Dollas, Nick Kanopoulos:
Reducing the Time to Market Through Rapid Prototyping - Guest Editors' Introduction. Computer 28(2): 14-15 (1995) - [j18]Theodore Karoubalis, Kostas Adaos, George Alexiou, Nick Kanopoulos:
A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier. Int. J. Circuit Theory Appl. 23(6): 587-598 (1995) - [c8]Jason P. Hurst, Nick Kanopoulos:
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits. Asian Test Symposium 1995: 346-352 - [c7]Theodore Karoubalis, George Alexiou, Nick Kanopoulos:
Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs). EURO-DAC 1995: 282-287 - 1994
- [j17]George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos:
On the design of a high-performance, expandable, sorting engine. Integr. 18(1): 121-135 (1994) - [j16]Theodoros Antonakopoulos
, Nick Kanopoulos:
Multiple boundary scan-paths for minimizing circuit-board test-application time. Microprocess. Microprogramming 40(6): 377-386 (1994) - [j15]Tassos Markas, Mark Royals, Nick Kanopoulos:
Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations. IEEE Trans. Very Large Scale Integr. Syst. 2(2): 149-156 (1994) - [c6]George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos:
Design and Implementation of a High-Performance, Modular, Sorting Engine. EDAC-ETC-EUROASIC 1994: 2-8 - 1993
- [j14]Nazar S. Haider, Nick Kanopoulos:
Efficient board interconnect testing using the split boundary scan register. J. Electron. Test. 4(2): 181-189 (1993) - 1992
- [j13]George Alexiou, Nick Kanopoulos:
A new serial/parallel two's complement multiplier for vlsi digital signal processing. Int. J. Circuit Theory Appl. 20(2): 209-214 (1992) - [j12]Nick Kanopoulos, Joseph H. Carabetta:
Design and implementation of a totally self-checking 16 × 16 bit array multiplier. Integr. 14(2): 215-228 (1992) - [j11]Mark Royals, Tassos Markas, Nick Kanopoulos:
A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port. Microprocess. Microprogramming 35(1-5): 493-500 (1992) - [j10]Nick Kanopoulos, Dimitris Pantzartzis, Frederick R. Bartram:
Design of Self-Checking Circuits Using DCVS Logic: A Case Study. IEEE Trans. Computers 41(7): 891-896 (1992) - [c5]Nazar S. Haider, Nick Kanopoulos:
The split boundary scan register technique for testing board interconnects. VTS 1992: 43-48 - 1990
- [j9]Tassos Markas, Mark Royals, Nick Kanopoulos:
On Distributed Fault Simulation. Computer 23(1): 40-52 (1990) - [j8]Tassos Markas, Nick Kanopoulos:
A bus-monitor unit for fault-tolerant system configurations. Microprocessing and Microprogramming 30(1-5): 521-527 (1990) - [c4]Mark Royals, Tassos Markas, Tianmaw Yang, Nick Kanopoulos:
Creating the IC palette [ASIC design]. RSP 1990: 76-86
1980 – 1989
- 1989
- [j7]Jill J. Hallenbeck, James R. Cybrynski, Nick Kanopoulos, Tassos Markas, Nagesh Vasanthavada:
The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability. Computer 22(4): 59-68 (1989) - [j6]Nagesh Vasanthavada, Nick Kanopoulos:
A built-in test module for fault isolation. IEEE Des. Test 6(3): 58-65 (1989) - [j5]J. Dodrill, Nick Kanopoulos:
On the design of a real-time digital median filter. Microprocessing and Microprogramming 27(1-5): 245-249 (1989) - 1988
- [j4]Nick Kanopoulos, Peter N. Marinos:
Design of a bus-monitor for real-time applications. Microprocess. Microprogramming 24(1-5): 717-721 (1988) - [c3]Jill J. Hallenbeck, Nick Kanopoulos, Nagesh Vasanthavada, James W. Watterson:
CAD Tools for Supporting System Design for Testability. ITC 1988: 993 - 1987
- [j3]Nick Kanopoulos, Nagesh Vasanthavada:
A monolithic scan-line bit producer for real-time image rasterization. Microprocess. Microprogramming 21(1-5): 57-63 (1987) - 1986
- [c2]Nick Kanopoulos, Peter N. Marinos:
A High-Performance Single-Chip VLSI Signal Processor Architecture. Aegean Workshop on Computing 1986: 166-179 - 1985
- [j2]Nick Kanopoulos, Vassilios Makios:
A single-chip adaptive delta modulator with optimum performance. Integr. 3(4): 319-328 (1985) - 1984
- [j1]Nikos Kanopoulos, G. Thomas Mitchell:
Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors. IEEE Des. Test 1(2): 52-59 (1984) - 1983
- [c1]Nick Kanopoulos, G. Thomas Mitchell:
Testing of Bit-Serial Signal Processors. ITC 1983: 719-727
Coauthor Index
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