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ORCIDIEEE Design & Test of Computers, Volume 1
Volume 1, Number 1, February 1984
- Hillel Ofek:
Guest Editor's Introduction Design Automation. 16-17 - Francine S. Frome:
Improving color CAD Systems for Users: Some Suggestions from Human Factors Studies. 18-27 - Larry N. Dunn:
IBM'S Engineering Design System Support for VLSI Design and Verification. 30-40 - Charles W. Rose, Greg M. Ordy, Paul J. Drongowski:
N.mPc: A Study in University-Industry Technology Transfer. 44-56 - Thaddeus J. Kowalski, Donald E. Thomas:
The VLSI Design Automation Assistant: An IBM System/370 Design. 60-69 - Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo:
Fast Pass-Transistor Simulation for Custom MOS Circuits. 71-81 - Miron Abramovici, Prem R. Menon, David T. Miller:
Critical Path Tracing: An Alternative to Fault Simulation. 83-93
Volume 1, Number 2, May 1984
- Robert E. Anderson:
Linking Design&Test. 27-31 - John R. Kuban, William C. Bruce:
Self-Testing the Motorola MC6804P2. 33-41 - William S. Blackley, Mervyn A. Jack, James R. Jordan:
A Digital Polarity Correlator with Built-in Self Test and Self Repair. 42-49 - Nikos Kanopoulos, G. Thomas Mitchell:
Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors. 52-59 - Robert C. Kroeger:
Testability Emphasis in the General Electric A/VLSI Program. 61-65 - Chantal Robach, Philippe Malecha, Gilles Michel:
CATA: A Computer-Aided Test Analysis System. 68-79 - Michael J. Bending:
Hitest: A Knowledge-Based Test Generation System. 83-92 - David Florcik, David Low, Martin Roche:
Prototype Debug using ATE. 94-99 - Rudy Garcia:
The Fairchild Sentry 50 Tester: Establishing New ATE Performance Limits. 101-109
Volume 1, Number 3, August 1984
- Richard M. Sedmak, Donald E. Thomas:
Probing the State of the Art. 18-19 - Tom Blank:
A Survey of Hardware Accelerators Used in Computer-Aided Design. 21-39 - W. R. Heller, C. George Hsi, Wadie F. Mikhaill:
Wirability-designing wiring space for chips and chip packages. 43-51 - Jin H. Kim, John McDermott, Daniel P. Siewiorek
:
Exploiting Domain Knowledge in IC Cell Layout. 52-64 - Ronald L. Wadsack:
Design Verification and Testing of the WE 32100 CPUs. 66-75 - Prithviraj Banerjee, Jacob A. Abraham:
Characterization and Testing of Physical Failures in MOS Logic Circuits. 76-86 - Mark R. Barber:
Fundamental Timing Problems in Testing MOS VLSI on Modern ATE. 90-97
Volume 1, Number 4, November 1984
- Akira Motohara, Hideo Fujiwara:
Design for Testability for Complete Test Coverage. 25-32 - Steve Sapiro:
The electronic workstation-an overview. 33-41 - Johnny J. LeBlanc:
LOCST: A Built-In Self-Test Technique. 45-52 - Dwight D. Hill:
Icon: A Tool for Design at Schematic, Virtual Grid, and Layout Levels. 53-60 - Yashwant K. Malaiya, Ramesh Narayanaswamy:
Modeling and Testing for Timing Faults in Synchronous Sequential Circuits. 62-74 - Alice C. Parker:
Automated Synthesis of Digital systems. 75-81
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