default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC 1988: Washington, D.C., USA
- Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988. IEEE Computer Society 1988, ISBN 0-8186-0870-6
Session 1: Plenary: Keynote Address and Invited Speakers
Keynote Speaker
- A. Blanton Godfrey:
Managing Quality : Today's Opportunities, Tomorrow's Challenges. ITC 1988: 1
Invited Speakers
- Lutz P. Henckels:
Scan Path and Beyond : The Road to Improved ASIC Testability. ITC 1988: 2 - Alberto L. Sangiovanni-Vincentelli:
Optimal Logic Synthesis and Testability : Two Sides of the Same Coin. 3-12
Session 2: New Advances in Test Hardware
- Sheng-Jen Tsai, Charles D. Hechtman:
GaAs Driver and Sensor for a High-Speed Test System. 13-22 - Christopher W. Branson, Don Murray, Steve Sullivan:
Integrated Pin Electronics for a VLSI Test System. 23-27 - J. R. Birchak, H. K. Haill:
Characteristic Impedance and Coupling Coefficients for Multilayer PC Boards. 28-38
Session 3: Board Test: New Problems and Applications
- Robert E. McAuliffe:
Practical Production Testing of ISDN Circuit Boards. 39-46 - Mark G. Karpovsky, Prawat Nagvajara:
Board-Level Diagnosis by Signature Analysis. 47-53 - Stephen Y. H. Su, Hede Ma:
Fault Isolation in Grey Systems. 54-63
Session 4: Testing Microprocessors: A Life Cycle's Work
- Catherine Bellon, Raoul Velazco, Haissam Ziade:
Analysis of Experimental Results on Functional Testing and Diagnosis of Complex Circuits. 64-72 - Hans Peter Klug:
Microprocessor Testing by Instruction Sequences Derived from Random Patterns. 73-80 - Janusz Sosnowski:
Detection of Control Flow Errors Using Signature and Checking Instructions. 81-88
Session 5: Software and Hardware Approaches to Fault Simulation
- Vinod Narayanan, Vijay Pitchumani:
: A Parallel Algorithm for Fault Simulation on the Connection Machine. 89-93 - Jean Paul Caisso, Bernard Courtois:
Fault Simulation and Test Pattern Generation at the Multiple-Valued Switch Level. 94-101 - Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato:
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. 102-107
Session 6: Ultimate: The Wave of the Future
- Teruo Tamama, Naoaki Narumi, Taiichi Otsuji, Masao Suzuki, Tsuneta Sudo:
Key Technologies for 500 MHz VLSI Test System "ULTIMATE". 108-113 - Tohru Adachi, M. Tanno, Tsuneta Sudo:
Software Environment for 500 MHz VLSI Test System "ULTIMATE". 114-119 - Yoshimitsu Sakagawa, Yusio Akazawa, Naoaki Narumi, Akira Yoshii, Tsuneta Sudo:
Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE". 120-125
Session 7: Boundary Scan and Test Bus
- Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski:
Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. 126-137 - Clay Gloster, Franc Brglez:
Boundary Scan with Cellular-Based Built-In Self-Test. 138-145 - Matthias Gruetzner:
Design for Testability for Wafer-Scale Integration Interconnect Systems Design and Test Methodology. 146-152
Session 8: Test Features of Today's Microprocessors
- Theo J. Powell, Fred Hwang, Bill Johnson:
Testability Features in the TMS370 Family of Microcomputers. 153-160 - Luis A. Bonet:
Testability Features of a 32 Kbps ADPCM Transcoder. 161-171 - Yasuyuki Nozuyama, Akira Nishimura, Jun Iwamura:
Design for Testability of a 32-Bit Microprocessor, the TX1. 172-182
Session 9: Panel Session: What ist the Path to Fast Fault Simulation?
- Miron Abramovici, Balaji Krishnamurthy, Rob Mathews, Bill Rogers, Michael Schulz, Sharad Seth, John A. Waicukauski:
What is the Path to Fast Fault Simulation? 183-192
Session 10: Panel Session: Componenent ATE Timing Accuracy Specifications: Can We Standardize?
- Marc Mydill:
Standardization of ATE Timing Accuracy Specifications. 193-194
Session 11: Panel Sesssion: Testability Standards
- Phil Collins:
Boundary Scan: The ATE Vendors' View. 195-196 - Pete Fleming:
Semiconductor Perspective on Test Standards. 197-198 - Charles R. Kime:
Impact of Testability Standards on University Research and Instruction. 199-200 - David J. Richards:
Value of Testability Standards in Testing Commercial Products. 201-202
Session 13: Panel Session Test Education: Linking Theory and Practice
- Edward J. McCluskey:
Practice and Theory. 203-204 - Samiha Mourad:
Digital Testing, Theory and Practice. 205-206 - Kenneth Rose:
Do the Designs Work ? 207-208
Session 14: High-Level Test Generation
- Stephen M. Lea, Nigel Brown, Tim Katz, Phil Collins:
Expert System for the Functional Test Program Generation of Digital Electronic Circuit Boards. 209-220 - Brian T. Murray, John P. Hayes:
Hierarchical Test Generation Using Precomputed Tests for Modules. 221-229 - Gerold Affs, Reiner W. Hartenstein, Andrea Wodtko:
The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions. 230-235
Session 15: Weighted Pseudorandom Pattern Genereation for BIST
- Hans-Joachim Wunderlich:
Multiple Distributions for Biased Random Test Patterns. 236-244 - John A. Waicukauski, Eric Lindbloom:
Fault Detection Effectiveness of Weighted Random Patterns. 245-255 - Fardad Siavoshi:
WTPGA : A Novel Weighted Test Pattern Generation Approach for VLSI Built-In Self-Test. 256-262
Session 16: RAM Design for Test
- Dhiraj K. Pradhan, Nirmala R. Kamath:
RTRAM: Reconfigurable and Testable Multi-Bit RAM Design. 263-278 - Pinaki Mazumder:
An On-Chip Double-Bit Error-Correcting Code for Three-Dimensional Dynamic Random-Access Memory. 279-288 - Steve Grennan:
Application of a Commercial Data Base Management System to Memory Device Test Program Generation and Debugging. 289-294
Session 17: Quality, Yield, and the Cost of Test
- Edward J. McCluskey, Fred Buelow:
IC Quality and Test Transparency. 295-301 - Chris Salzmann, Martin Funcell, Richard Taylor:
Design for Test and the Cost of Quality. 302-307 - W. David Ballew, Lauren M. Streb:
Elimination of Incoming Test Based Upon In-Process Failure and Repair Costs. 308-313
Session 19: Design and Evaluation of Signature Analysis Based BIST
- Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski:
On Multiple Fault Coverage and Aliasing Probability Measures. 314-321 - Jacob Savir, William H. McAnney:
Identification of Failing Tests with Cycling Registers. 322-328 - Sandeep K. Gupta, Dhiraj K. Pradhan:
A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. 329-342
Session 20: SRAM Test Methods
- Frans P. M. Beenker, Rob Dekker, Loek Thijssen:
Fault Modeling and Test Algorithm Development. 343-352 - Frans P. M. Beenker, Rob Dekker, Loek Thijssen:
A Realistic Self-Test Machine for Static Random Access Memories. 353-361 - Manuel J. Raposa:
Dual Port Static RAM Testing. 362-368
Session 21: Reliability Test Detection Strategies
- A. P. Dorey, B. K. Jones, Andrew Mark David Richardson, P. C. Russell, Y. Z. Xu:
Reliability Testing by Precise Electrical Measurement. 369-373 - Masaki Hashizume, Takeomi Tamesada, Kazuhiro Yamada, Masaaki Kawakami:
Fault Detection of Combinational Circuits Based on Supply Current. 374-380 - Birger Schneider, Peter Oestergaard:
An Advanced Data Compaction Approach for Test During Burn-In. 381-390
Session 22: Board Test Technology and Practice
- Charles D. Hechtman:
In-Circuit Test Fixture. 391-400 - Luis Balme, Anne Mignotte, Jean-Yves Monari, Patrick Pondaven, Christophe Vaucher:
New Testing Equipment for SMT PC Boards. 401-410 - John Arena:
Evaluating the Limitations of High-Speed Board Testers. 411-420
Session 23: BIST Control and Test Scheduling
- John Y. Sayah, Charles R. Kime:
: Test Scheduling for High Performance VLSI System Implementations. 421-430 - Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien:
Concurrent Control of Multiple BIT Structures. 431-442 - C. Mani Krishna, Yann-Hang Lee:
Optimal Scheduling of Signature Analysis for VLSI Testing. 443-451
Session 24: CAE and Workstations I
- John Ivie:
A High Level Approach to Integrating Design and Test. 452-459 - Ji-en Morris Chang, William T. Krakow:
Optimal Use of Timing Resources: A Crucial Step in Test Program Generation. 460-465 - Cristopher Merritt:
A Strategy for Generating Functional Tests from Device Simulations. 466-474
Session 25: Realistic Defects and Their Impact on Shipped Quality
- John Paul Shen, F. Joel Ferguson:
Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. 475-484 - Michael Demjanenko, Shambhu J. Upadhyaya:
Dynamic Techniques for Yield Enhancement of Field Programmable Logic Arrays. 485-491 - Eun Sei Park, Thomas W. Williams, M. Ray Mercer:
Statistical Delay Fault Coverage and Defect Level for Delay Faults. 492-499
Session 26: Panel Session: High Frequency DUT-Tester Interconnection Problems
- Bernd Reichelmann:
Contactors for Testing at High Frequencies. 500-501
Session 27: Implementation and Analysis of BIST
- Melvin A. Breuer, Jung-Cheun Lien:
A Test and Maintenance Controller for a Module Containing Testable Chips. 502-513 - Mehdi Katoozi, Mani Soma:
A BIST Design of Structured Arrays with Fault-Tolerant Layout. 514-521 - Jon G. Udeli Jr.:
Reconfigurable Hardware for Pseudo-Exhaustive Test. 522-530 - David L. Landis, Daniel C. Muha:
Evaluation of System BIST Using Computational Performance Measures. 531-536
Session 28: CAE and Workstations II
- Arthur E. Downey, Kazuhiko Matsuda:
Some New Techniques in Waveshape Capture and Analysis. 537-546 - Patrick M. Powers:
A High-Resolution Waveform Analysis Tool. 547-550 - Cihan Tinaztepe, Bülent Özgüç:
Functional Test Program Generation Through interactive Graphics. 551-558 - Yuichi Kawabata, Masami Maruyama, Al Tejeda:
PGTOOL: An Automatic Interactive Program Generation Tool for Testing New-Generation Memory Devices. 559-568
Session 29: Advances in Ffault Simulation and Fault Modeling
- William H. Nicholls, Mani Soma:
Fault Bundling: Reducing Machine Evaluation Activity in Hierarchical Concurrent Fault Simulation. 569-573 - Deborah Machlin, David Gross, Sudhir Kadkade, Ernst G. Ulrich:
Switch-Level Concurrent Fault Simulation Based on a General Purpose List Traversal Mechanism. 574-581 - Steven P. Smith, Bill Underwood, M. Ray Mercer:
D^3FS: A Demand Driven Deductive Fault Simulator. 582-592 - Tapan J. Chakraborty, Sumit Ghosh:
On Behavior Fault Modeling for Combinational Digital Designs. 593-600
Session 30: High-Speed Probing
- Brian Leslie, Farid Matta:
Membrane Probe Card Technology (the Future for High Performance Wafer Test). 601-607 - C. Barsotti, S. Tremaine, M. Bonham:
Very High Density Probing. 608-614 - T. Roland Fredriksen, David Grano:
New Automated Prober Support for High Pincount Test Heads. 615-620
Session 31: Design for Testability I
- Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines. 621-630 - Desmond F. D'Souza:
A Knowledge Representation Scheme for DFT. 631-641 - Hideo Fujiwara, Osamu Fujisawa, Kazunori Hikone:
Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique. 642-648
Session 32: Testing ASICs
- Gary D. Culbertson:
Managing the ASIC Design to Test Process. 649-656 - Eric Archambeau, Ken Van Egmond:
Built-In Test Compiler in an ASIC Environment. 657-664 - A. Walter, Y. Kleinman, L. Edelshteyn, Jeff Gartner:
An Expert Test Program Generation System for Per-Pin Testers. 665-668
Session 33: Test Generation: Techniques
- Samy Makar, Edward J. McCluskey:
On the Testing of Multiplexers. 669-679 - Sandip Kundu, Sudhakar M. Reddy:
Robust Tests for Parity Trees. 680-687 - Henry Cox, Janusz Rajski:
Stuck-Open and Transition Fault Testing in CMOS Complex Gates. 688-694
Session 34: Novel Test Techniques Using Optics
- G. Tremblay, P. Meyrueix, J. C. Peuzin:
Optical Testing of Printed Circuit Boards. 695-699 - Francois J. Henley, Hee-June Choi:
Test Head Design Using Electro-Optic Receivers and GaAs Pin Electronics for a Gigahertz Production Test System. 700-709 - Dean J. Kratzer, Steve Barton, Francois J. Henley, David A. Plomgrem:
High-Speed Pattern Generator and GaAs Pin : Electronics for a Gigahertz Production Test System. 710-718
Session 35: Design for Testability II
- M. M. Pradhan, E. J. O'Brien, S. L. Lam, James Beausang:
Circular BIST with Partial Scan. 719-729 - Hi-Keung Tony Ma, A. Richard Newton, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli:
An Incomplete Scan Design Approach to Test Generation for Sequential Machines. 730-734 - S. Bhawmick, M. S. Khaira, P. P. Mishra, A. Das, A. Dasgupta, P. Palchaudhury:
Threading of Multiple Scan Paths in a VLSI Circuit. 735-743
Session 36: Mixed-Signal Testing
- John Beck, James Pappas, Robert Rose, Larry Seiler:
Integrated Test Logic for Video ICs. 744-751 - John L. Russo:
Flexible Deep Memory Architecture Aids Program Development. 752-754 - Eric Rosenfeld:
Timing Generation for DSP Testing. 755-763
Session 37: Test Generation: Algorithms
- Gabriel M. Silberman, Ilan Y. Spillinger:
G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. 764-772 - Steven D. Millman, Edward J. McCluskey:
Detecting Bridging Faults with Stuck-at Test Sets. 773-783 - Markus Robinson, Janusz Rajski:
An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. 784-795
Session 38: Process Improvement: Data in Action
- Chi W. Yau, Song-Lin Chang, Bruce F. Jordan, Joe J. Schwermann, Joan A. Wellman:
Trouble-Shooting: A Key to Process Improvement. 796-803 - Raymond J. Balzer, Greg A. Larsen:
Predicting and Obtaining High Final Test Yields. 804-815 - Neil Hutchinson:
CIM , Electronics Manufacturing and ATE. 816-822
Session 39: Analog Design for Testability
- Kenneth D. Wagner, Thomas W. Williams:
Design for Testability of Mixed Signal Integrated Circuits. 823-828 - Gertjan J. Hemink, Berend W. Meijer, Hans G. Kerkhoff:
TASTE: A Tool for Analog System Testability Evaluation. 829-838 - M. J. Marlett, Jacob A. Abraham:
DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests. 839-844
Session 40: Test Generation: Delay Testing
- Ankan K. Pramanick, Sudhakar M. Reddy:
On the Detection of Delay Faults. 845-856 - Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger:
Delay Test Generation 1: Concepts and Coverage Metrics. 857-866 - Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger:
Delay Test Generation 2: Algebra and Algorithms. 867-876
Session 41: Systems Test I
- Stephen R. Demba, Ernst G. Ulrich, Karen Panetta, David Giramma:
Experiences with Concurrent Fault Simulation of Diagnostic Programs. 877-883 - Hidetoshi Tanaka, Masato Kawai, Izumi Sugasaki, Tadanobu Hakuba:
System Level Fault Dictionary Generation. 884-887 - Stephen Y. H. Su, Hede Ma:
Designs for Diagnosability and Reliability in VLSI Systems. 888-897
Session 42: E-Beam Concepts
- M. Melgara, M. Battu, P. Garino, J. Dowe, Y. J. Vernay, M. Marzouki, Francis M. Boland:
Automatic Location of IC Design Errors Using Beam System. 898-907 - Hironobu Niijima, Yasuo Tokunaga, Shouichi Koshizuka, Kazuo Yakuwa, Péter Fazekas, Mathias Sturm, Hans-Peter Feuerbaum:
Electron Beam Tester Integrated into a VLSI Tester. 908-913
Session 43: Concurrent BIST Techniques
- Kent D. Wilken, John Paul Shen:
Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control Errors. 914-925 - Lawrence P. Holmquist, Larry L. Kinney:
Error Detection with Latency in Sequential Circuits. 926-933 - Leon J. Sigal, Charles R. Kime:
Concurrent Off-Phase Built-in Self-Test of Dormant Logic. 934-941
Session 44: VLSI Processor Test: Techniques and Technology
- Mark Marshall:
Techniques for User Testing of the 68882. 942-947 - Kenneth R. Stuchlik:
Simultaneous Switching Noise Evaluation of Advanced CMOS Logic (ACL). 948-957 - Douglas B. Arnett, K. S. Bhaskar:
Emulative Testing at the Bus Speed Limit. 958-968
Session 45: Systems Test II
- Donald H. Merliho, John Hadjilogiou:
Built-In Test Strategy for Next Generation Military Avionic Hardware. 969-975 - Bulent I. Dervisoglu:
Using Scan Technology for Debug and Diagnostics in a Workstation Environment. 976-986 - Mike Ricchetti, John Hoglund:
Scan Diagnostic Strategy for the Series 10000 Prism Workstation. 987-992
Poster Session
- Jill J. Hallenbeck, Nick Kanopoulos, Nagesh Vasanthavada, James W. Watterson:
CAD Tools for Supporting System Design for Testability. 993 - Cuong Bui:
Testability Using Random Access Test Register. 994-995 - Michael Treseler:
Designing State Machines for Testability. 996 - Samiha Mourad, Edward J. McCluskey:
On Benchmarking Digital Testing Systems. 997 - Peter N. Marinos:
The Non-Linear Feedback Shift-Register as a Built-In Self-Test (BIST) Resource. 998 - David Stannard, Bozena Kaminska:
Detection of Hard Faults in a Combinational Circuit Using Budget Constraints. 999 - Jon G. Udeli Jr., Edward J. McCluskey:
Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation. 1000 - Sami A. Al-Arian, Kevin A. Kwiat:
Defining a Standard for Fault Simulator Evaluation. 1001 - G. J. Hill, B. C. Roberts, C. P. Strudwick:
Determination of Safe Back-Driving Currents in Bond Wires and Dice. 1002
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-20 19:49 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
