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ORCIDIlan Y. Spillinger
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2000 – 2009
- 2000
[j11]Ilan Y. Spillinger, Chris J. Newburn:
Guest Editors' Introduction. J. Instr. Level Parallelism 2 (2000)
1990 – 1999
- 1999
- [e1]Ronny Ronen, Matthew K. Farrens, Ilan Y. Spillinger:
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999. ACM/IEEE Computer Society 1999, ISBN 0-7695-0437-X [contents] - 1996
- [j10]Guy Even, Ilan Y. Spillinger, Leon Stok:
Retiming revisited and reversed. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3): 348-357 (1996) - 1995
- [c8]Leon Stok, Ilan Y. Spillinger, Guy Even:
Improving initialization through reversed retiming. ED&TC 1995: 150-154 - 1994
- [j9]Gabriel M. Silberman, Ilan Y. Spillinger:
A backtracing-oriented procedure for the analysis of combinational gate-level designs. Integr. 17(3): 271-286 (1994) - [j8]Gideon D. Intrater, Ilan Y. Spillinger:
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers. IEEE Trans. Computers 43(10): 1140-1150 (1994) - 1993
- [j7]Guy Even, Ophir Rachman, Ilan Y. Spillinger:
Linear test sequences for detecting functionally faulty RAM's. Integr. 16(1): 75-89 (1993) - [j6]Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman:
Architectural Improvement for a Data-Driven VLSI Processing Array. J. Parallel Distributed Comput. 19(4): 308-322 (1993) - 1992
- [c7]Gideon D. Intrater, Ilan Y. Spillinger:
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers. ISCA 1992: 106-113 - 1991
- [j5]Gabriel M. Silberman, Ilan Y. Spillinger:
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation. IEEE Trans. Computers 40(1): 66-79 (1991) - [j4]Gabriel M. Silberman, Ilan Y. Spillinger:
RIDDLE: A Foundation for Test Generation on a High-Level Design Description. IEEE Trans. Computers 40(1): 80-87 (1991) - 1990
- [j3]Gabriel M. Silberman, Ilan Y. Spillinger:
Using functional fault simulation and the difference fault model to estimate implementation fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1335-1343 (1990)
1980 – 1989
- 1989
- [j2]Raphael Renous, Gabriel M. Silberman, Ilan Y. Spillinger:
Whistle: A Workbench for Test Development of Library-Based Designs. Computer 22(4): 27-41 (1989) - [c6]Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman:
Architectural Improvements for Data-Driven VLSI Processing Arrays. FPCA 1989: 243-259 - 1988
- [c5]Gabriel M. Silberman, Ilan Y. Spillinger:
RIDDLE: a foundation for test generation on a high level design description. FTCS 1988: 76-81 - [c4]Gabriel M. Silberman, Ilan Y. Spillinger:
G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. ITC 1988: 764-772 - [c3]Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger:
Delay Test Generation 1: Concepts and Coverage Metrics. ITC 1988: 857-866 - [c2]Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger:
Delay Test Generation 2: Algebra and Algorithms. ITC 1988: 867-876 - 1986
- [j1]Ilan Y. Spillinger, Gabriel M. Silberman:
Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(3): 396-404 (1986) - [c1]Gabriel M. Silberman, Ilan Y. Spillinger:
The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage. ITC 1986: 332-339
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