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ORCIDVijay S. Iyengar
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2010 – 2019
- 2019
[c31]Tongfei Chen, Jirí Navrátil, Vijay S. Iyengar, Karthikeyan Shanmugam
:
Confidence Scoring Using Whitebox Meta-models with Linear Classifier Probes. AISTATS 2019: 1467-1475- 2018
- [i3]Tongfei Chen, Jirí Navrátil, Vijay S. Iyengar, Karthikeyan Shanmugam:
Confidence Scoring Using Whitebox Meta-models with Linear Classifier Probes. CoRR abs/1805.05396 (2018) - 2017
- [c30]Karthikeyan Natesan Ramamurthy, Dennis Wei, Emily Ray, Moninder Singh, Vijay S. Iyengar, Dmitriy A. Katz-Rogozhnikov, Jingwei Yang, Kevin N. Tran, Gigi Y. Yuen-Reed:
A configurable, big data system for on-demand healthcare cost prediction. IEEE BigData 2017: 1524-1533 - [i2]Amit Dhurandhar, Vijay S. Iyengar, Ronny Luss, Karthikeyan Shanmugam:
TIP: Typifying the Interpretability of Procedures. CoRR abs/1706.02952 (2017) - [i1]Amit Dhurandhar, Vijay S. Iyengar, Ronny Luss, Karthikeyan Shanmugam:
A Formal Framework to Characterize Interpretability of Procedures. CoRR abs/1707.03886 (2017)
2000 – 2009
- 2008
- [c29]Matthew L. Hill, Murray Campbell, Yuan-Chi Chang, Vijay S. Iyengar:
Event detection in sensor networks for modern oil fields. DEBS 2008: 95-102 - 2007
- [c28]Vijay S. Iyengar, Ioana Boier, Karen Kelley, Raymond Curatolo:
Analytics for Audit and Business Controls in Corporate Travel and Entertainment. AusDM 2007: 3-12 - 2006
- [c27]Vijay S. Iyengar, David Flaxer, Anil Nigam, John Vergo:
Evaluation of IT Portfolio Options by Linking to Business Services. DEECS 2006: 66-80 - 2004
- [c26]Vijay S. Iyengar:
On detecting space-time clusters. KDD 2004: 587-592 - 2003
- [c25]Chung-Sheng Li, Charu C. Aggarwal, Murray Campbell, Yuan-Chi Chang, Gregory Glass, Vijay S. Iyengar, Mahesh Joshi, Ching-Yung Lin, Milind R. Naphade, John R. Smith, Belle L. Tseng, Min Wang, Kun-Lung Wu, Philip S. Yu:
Epi-SPIRE: a system for environmental and public health activity monitoring. ICME 2003: 713-716 - 2002
- [j9]Tong Zhang, Vijay S. Iyengar:
Recommender Systems Using Linear Classifier. J. Mach. Learn. Res. 2: 313-334 (2002) - [c24]Vijay S. Iyengar:
Transforming data to satisfy privacy constraints. KDD 2002: 279-288 - 2001
- [c23]Matthew L. Hill, Yuan-Chi Chang, Vijay S. Iyengar, Chung-Sheng Li:
Texture-space segmentation and multi-resolution mapping for forestry applications. ICASSP 2001: 1581-1584 - [c22]Vijay S. Iyengar, Tong Zhang:
Empirical Study of Recommender Systems Using Linear Classifiers. PAKDD 2001: 16-27 - [c21]Vijay S. Iyengar, Jon Lee, Murray Campbell:
Evaluating multiple attribute items using queries. EC 2001: 144-153 - 2000
- [c20]Vijay S. Iyengar, Chidanand Apté, Tong Zhang:
Active learning using adaptive resampling. KDD 2000: 91-98
1990 – 1999
- 1999
- [c19]Vijay S. Iyengar:
HOT: Heuristics for Oblique Trees. ICTAI 1999: 91-98 - 1996
- [c18]Vijay S. Iyengar, Louise Trevillyan, Pradip Bose:
Representative Traces for Processor Models with Infinite Cache. HPCA 1996: 62-72 - 1995
- [j8]Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal:
AVPGEN-A test generator for architecture verification. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 188-200 (1995) - 1994
- [j7]Daniel Brand, Vijay S. Iyengar:
Identification of redundant delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 553-565 (1994) - [c17]Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen:
Architectural Verification of Processors Using Symbolic Instruction Graphs. ICCD 1994: 454-459 - 1992
- [j6]Vijay S. Iyengar, Gopalakrishnan Vijayan:
Optimized test application timing for AC test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11): 1439-1449 (1992) - [c16]Daniel Brand, Vijay S. Iyengar:
Identification of Single Gate Delay Fault Redundancies. ICCD 1992: 24-28 - [c15]Ashok K. Chandra, Vijay S. Iyengar:
Constraint Slving for Test Case Generation. ICCD 1992: 245-248 - [c14]Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy:
A Small Test Generator for Large Designs. ITC 1992: 30-40 - [c13]Yaron Aizenbud, Paul Chang, Moshe Leibowitz, Dave Smith, Bernd Könemann, Vijay S. Iyengar, Barry K. Rosen:
AC Test Quality: Beyond Transition Fault Coverage. ITC 1992: 568-577 - [c12]Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams:
Delay Test: The Next Frontier for LSSD Test Systems. ITC 1992: 578-587 - 1991
- [c11]Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar:
Symbolic implication in test generation. EURO-DAC 1991: 492-496 - [c10]Vijay S. Iyengar, Gopalakrishnan Vijayan:
Test Application Timing: The Unexplored Issue in AC Test. ITC 1991: 840-847 - 1990
- [j5]Vijay S. Iyengar, Barry K. Rosen, John A. Waicukauski:
On computing the sizes of detected delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 299-312 (1990)
1980 – 1989
- 1989
- [c9]Daniel Brand, Vijay S. Iyengar:
Synthesis of Pseudo-Random Pattern Testable Designs. ITC 1989: 501-508 - 1988
- [j4]Daniel Brand, Vijay S. Iyengar:
Timing Analysis Using Functional Analysis. IEEE Trans. Computers 37(10): 1309-1315 (1988) - [j3]Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
SLS-a fast switch-level simulator [for MOS]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 838-849 (1988) - [c8]Vijay S. Iyengar, Donald T. Tang:
On simulating faults in parallel. FTCS 1988: 110-115 - [c7]Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger:
Delay Test Generation 1: Concepts and Coverage Metrics. ITC 1988: 857-866 - [c6]Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger:
Delay Test Generation 2: Algebra and Algorithms. ITC 1988: 867-876 - 1987
- [j2]John A. Waicukauski, Eric Lindbloom, Barry K. Rosen, Vijay S. Iyengar:
Transition Fault Simulation. IEEE Des. Test 4(2): 32-38 (1987) - 1986
- [c5]Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
SLS - a fast switch level simulator for verification and fault coverage analysis. DAC 1986: 164-170 - [c4]Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman:
Efficient Fault Simulation of CMOS Circuits with Accurate Models. ITC 1986: 520-529 - [c3]John A. Waicukauski, Eric Lindbloom, Vijay S. Iyengar, Barry K. Rosen:
Transition Fault Simulation by Parallel Pattern Single Fault Propagation. ITC 1986: 542-551 - 1985
- [j1]Vijay S. Iyengar, Larry L. Kinney:
Concurrent Fault Detection in Microprogrammed Control Units. IEEE Trans. Computers 34(9): 810-821 (1985) - [c2]Zeev Barzilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman:
Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits. ITC 1985: 722-731 - 1982
- [c1]Vijay S. Iyengar, Larry L. Kinney:
Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units. ITC 1982: 469-479
Coauthor Index
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