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ORCIDBrion L. Keller
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Journal Articles
- 2015
[j7]Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen
:
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. IEEE Des. Test 32(4): 40-48 (2015)- 2010
- [j6]Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki:
Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Trans. Inf. Syst. 93-D(1): 17-23 (2010) - 2009
- [j5]Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller:
CTL and Its Usage in the EDA Industry. IEEE Des. Test Comput. 26(1): 36-43 (2009) - [j4]Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai:
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. 5(4): 520-528 (2009) - 2002
- [j3]Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera:
Extending OPMISR beyond 10x Scan Test Efficiency. IEEE Des. Test Comput. 19(5): 65-72 (2002) - 1996
- [j2]Pamela S. Gillis, Tom S. Guzowski, Brion L. Keller, Randal H. Kerr:
Test methodologies and design automation for IBM ASICs. IBM J. Res. Dev. 40(4): 461-474 (1996) - 1991
- [j1]Brion L. Keller, David P. Carlson, William Maloney:
The Compiled Logic Simulator. IEEE Des. Test Comput. 8(1): 21-34 (1991)
Conference and Workshop Papers
- 2015
- [c34]Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen:
At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. ATS 2015: 79-84 - 2014
- [c33]Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen:
Efficient testing of hierarchical core-based SOCs. ITC 2014: 1-10 - 2013
- [c32]Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui:
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. ETS 2013: 1-6 - [c31]Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim:
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC 2013: 1-10 - 2012
- [c30]Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen:
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC 2012: 1-10 - 2011
- [c29]Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel:
Automation of 3D-DfT Insertion. Asian Test Symposium 2011: 395-400 - 2010
- [c28]Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise:
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC 2010: 724-733 - 2009
- [c27]Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman:
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium 2009: 295-300 - [c26]Brion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings:
A Partially-Exhaustive Gate Transition Fault Model. Asian Test Symposium 2009: 361-364 - [c25]Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang:
Capture power reduction using clock gating aware test generation. ITC 2009: 1-9 - 2008
- [c24]Brion L. Keller, Sandeep Bhatia, Thomas Bartenstein, Brian Foutz, Anis Uzzaman:
Optimizing Test Data Volume Using Hybrid Compression. ATS 2008: 157-162 - [c23]Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor:
Test Generation for State Retention Logic. ATS 2008: 237-242 - 2007
- [c22]Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen:
Using Programmable On-Product Clock Generation (OPCG) for Delay Test. ATS 2007: 69-72 - [c21]Brion L. Keller, Tom Jackson, Anis Uzzaman:
A Review of Power Strategies for DFT and ATPG. ATS 2007: 213 - [c20]Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise:
Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. ITC 2007: 1-10 - 2006
- [c19]Anis Uzzaman, Brion L. Keller, Vivek Chickermane:
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. ATS 2006: 132 - [c18]Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie:
OCI: Open Compression Interface. ITC 2006: 1-4 - 2005
- [c17]Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi:
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium 2005: 156-161 - [c16]Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman:
Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium 2005: 470 - [c15]Brion L. Keller:
Encounter test OPMISR+ on-chip compression. ITC 2005: 2 - [c14]Brion L. Keller, Thomas Bartenstein:
Use of MISRs for compression and diagnostics. ITC 2005: 9 - 2004
- [c13]Vivek Chickermane, Brian Foutz, Brion L. Keller:
Channel Masking Synthesis for Efficient On-Chip Test Compression. ITC 2004: 452-461 - [c12]Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane:
An Economic Analysis and ROI Model for Nanometer Test. ITC 2004: 518-524 - 2001
- [c11]Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater:
A SmartBIST Variant with Guaranteed Encoding. Asian Test Symposium 2001: 325- - [c10]Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller:
High Performance Parallel Fault Simulation. ICCD 2001: 308-313 - [c9]Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay:
CTL the language for describing core-based test. ITC 2001: 131-139 - [c8]Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko:
OPMISR: the foundation for compressed ATPG vectors. ITC 2001: 748-757 - 2000
- [c7]Paul Chang, Brion L. Keller, Sarala Paliwal:
Effective parallel processing techniques for the generation of test data for a logic built-in self test system. Asian Test Symposium 2000: 374-379 - [c6]Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton:
Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. ITC 2000: 530-537 - 1999
- [c5]Paul Chang, Brion L. Keller, Sarala Paliwal:
Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. ICCD 1999: 175- - [c4]Brion L. Keller:
Using STIL to describe embedded core test requirements. ITC 1999: 1150 - 1998
- [c3]Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs:
ATPG in practical and non-traditional applications. ITC 1998: 632-640 - 1992
- [c2]Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams:
Delay Test: The Next Frontier for LSSD Test Systems. ITC 1992: 578-587 - 1991
- [c1]Brion L. Keller, David A. Haynes:
Design Automation of Test for the EX/9000TM Series Processors. ICCD 1991: 550-553
Coauthor Index
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