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2010 – 2019
- 2010
[c8]Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise:
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC 2010: 724-733
2000 – 2009
- 2007
- [c7]Vikram Iyengar, Jinjun Xiong
, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah:
Variation-aware performance verification using at-speed structural test and statistical timing. ICCAD 2007: 405-412 - [c6]Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland:
An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. VTS 2007: 173-178 - 2006
- [c5]David E. Lackey:
Efficient Latch and Clock Structures for System-on-Chip Test Flexibility. ITC 2006: 1-7 - 2003
- [c4]Jürgen Koehl, David E. Lackey, George W. Doerre:
IBM's 50 Million gate ASICs. ASP-DAC 2003: 628-634 - [c3]David E. Lackey, Paul S. Zuchowski, Jürgen Koehl:
Designing mega-ASICs in nanogate technologies. DAC 2003: 770-775 - 2002
- [j2]George W. Doerre, David E. Lackey:
The IBM ASIC/SoC methodology - A recipe for first-time success. IBM J. Res. Dev. 46(6): 649-660 (2002) - [c2]David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn:
Managing power and performance for System-on-Chip designs using Voltage Islands. ICCAD 2002: 195-202 - 2000
- [c1]David E. Lackey:
Applying placement-based synthesis for on-time system-on-a-chip design. CICC 2000: 121-124
1990 – 1999
- 1996
- [j1]James J. Engel, Thomas S. Guzowski, Anderson Hunt, David E. Lackey, Lansing D. Pickup, Robert A. Proctor, Karla Reynolds, Ann Marie Rincon, David R. Stauffer:
Design methodology for IBM ASIC products. IBM J. Res. Dev. 40(4): 387-406 (1996)
Coauthor Index
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