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ORCIDJürgen Koehl
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2000 – 2009
- 2008
[c11]Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl:
Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22- 2007
- [c10]Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl:
Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI 2007: 43-48 - 2006
- [c9]Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp:
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. DATE 2006: 387-392 - [c8]Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte:
Yield Improvement by Local Wiring Redundancy. ISQED 2006: 473-478 - 2003
- [c7]Jürgen Koehl, David E. Lackey, George W. Doerre:
IBM's 50 Million gate ASICs. ASP-DAC 2003: 628-634 - [c6]David E. Lackey, Paul S. Zuchowski, Jürgen Koehl:
Designing mega-ASICs in nanogate technologies. DAC 2003: 770-775 - 2001
- [c5]Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni:
Automatic Hierarchical Design: Fantasy or Reality? (Panel). ICCAD 2001: 656 - 2000
- [c4]Jürgen Koehl, Jürgen Schietke:
Platzierungsbasierte Logikoptimierung komplexer VLSI Chips. MBMV 2000: 270-277
1990 – 1999
- 1998
- [c3]Jürgen Koehl, Ulrich Baur, Thomas Ludwig, Bernhard Kick, Thomas Pflueger:
A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset. DATE 1998: 312-320 - [c2]Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl:
Analysis, reduction and avoidance of crosstalk on VLSI chips. ISPD 1998: 211-218 - 1997
- [j1]Bernhard Kick, Ulrich Baur, Jürgen Koehl, Thomas Ludwig, Thomas Pflueger:
Standard-cell-based design methodology for high-performance support chips. IBM J. Res. Dev. 41(4&5): 505-514 (1997) - 1991
- [c1]Ren-Song Tsay, Jürgen Koehl:
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. DAC 1991: 620-625
Coauthor Index
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