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ORCIDJournal of Low Power Electronics, Volume 5
Volume 5, Number 1, April 2009
- Ajit Gupte, Bharadwaj Amrutur:
Adaptive Global Elimination Algorithm for Low Power Motion Estimation. 1-16 - Jalel Ktari
, Mohamed Abid:
A Low Power Design Space Exploration Methodology Based on High Level Models and Confidence Intervals. 17-30 - Rahul M. Badghare, Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rajendra M. Patrikar:
Design of Low Power Parallel Multiplier. 31-39 - Y. K. Sudharshan, D. Sreenu, Ashok K. Saxena, Sudeb Dasgupta:
Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study. 40-49 - T. Sasilatha, J. Raja:
Modified Design and Analysis of a Performance Optimized Common Gate LNA for Low Power Wireless Sensor Network Applications. 50-57 - George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi:
Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. 58-68 - Lars Svensson:
Selected Peer-Reviewed Articles from the PATMOS 2008 Workshop. 69 - Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah:
Statistical Power Analysis for High-Performance Processors. 70-76 - Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner:
Low-Power Coding for Networks-on-Chip with Virtual Channels. 77-84 - Maurice Keller, William P. Marnane:
Low Energy ASIC Elliptic Curve Processor. 85-95 - Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich:
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. 96-105 - Roni Wiener, Gila Kamhi, Moshe Y. Vardi:
Intelligate: An Algorithm for Learning Boolean Functions for Dynamic Power Reduction. 106-112 - Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating. 113-121
Volume 5, Number 2, August 2009
- Yang Xu, Hu He, Yihe Sun:
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures. 123-134 - Gaurav Singh, Jacob B. Schwartz, Sandeep K. Shukla:
A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent Action-Oriented Specifications. 135-144 - Rishad Ahmed Shafik, Bashir M. Al-Hashimi, Sandip Kundu, Alireza Ejlali:
Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip. 145-156 - Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan:
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. 157-172 - K. Sreejith, Bharadwaj Amrutur, Ashok Balivada:
A Workload Based Lookup Table for Minimal Power Operation Under Supply and Body Bias Control. 173-184 - Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri:
Selective Forward Body Bias for High Speed and Low Power SRAMs. 185-195 - Guillaume Terrasson, Renaud Briand, Skandar Basrour:
A Design Technique for Power Constrained CMOS Low-Noise Amplifier Dedicated to Wireless Sensor Networks. 196-205 - Angelo Monteiro, Marcelino B. Santos, Alexandre Neves, Nuno Dias:
Noise Minimization for Low Power Bandgap Reference and Low Dropout Regulator Cores. 206-222 - Wing Yan Leung, Tsz Yin Man, Dongwei Zhang, Mansun Chan:
A Multi-Stage Low-Dropout Regulator with 1 pF Compensation Capacitor for System-on-Chip Applications. 223-228 - Suhwan Kim, Gabriel A. Rincón-Mora:
Achieving High Efficiency Under Micro-Watt Loads with Switching Buck DC-DC Converters. 229-240 - Nuno Dias, Marcelino B. Santos, Angelo Monteiro, Pedro Braga, Alexandre Neves:
Gate Driver Voltage Optimization for Multi-Mode Low Power DC-DC Conversion. 241-254 - Ajit Gupte, Bharadwaj Amrutur:
Adaptive Global Elimination Algorithm for Low Power Motion Estimation (J. Low Power Electronics 5: 1-16 (2009)). 255-256
Volume 5, Number 3, October 2009
- Rajendran Panda, Preeti Ranjan Panda:
A Special Issue on the "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009. 255-256 - Sanjay Kumar Wadhwa:
CMOS Proportional-to-Absolute Temperature Current Reference for Low Voltage Operation. 257-264 - Tamal Das, Pradip Mandal:
Switched-Capacitor Based Buck Converter Design Using Current Limiter. 265-278 - Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas:
A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. 279-290 - Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil:
Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization. 291-302 - Weihuang Wang, Euncheol Kim, Kiran K. Gunnam, Gwan S. Choi:
Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels. 303-312 - Muhammad Mudassar Nisar, Abhijit Chatterjee:
Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using Dual Real-Time Feedback. 313-325 - Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. 326-338 - Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham:
Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level. 339-353 - Nitin Kataria, Forrest Brewer, João Pedro Hespanha, Timothy Sherwood:
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems. 354-362 - Ramkumar Jayaseelan, Tulika Mitra:
Temperature Aware Scheduling for Embedded Processors. 363-372 - Sandro Penolazzi, Ahmed Hemani, Luca Bolognino:
A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures. 373-384 - Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Massoud Pedram:
Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips. 385-395 - Amir-Mohammad Rahmani, Ali Afzali-Kusha, Massoud Pedram:
A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution. 396-405
Volume 5, Number 4, December 2009
- Sumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla:
SCoPE: Statistical Regression Based Power Models for Co-Processors Power Estimation. 407-415 - Saadia Dhouib, Eric Senn, Jean-Philippe Diguet, Dominique Blouin, Johann Laurent:
Energy and Power Consumption Estimation for Embedded Applications and Operating Systems. 416-428 - K. Shyamala, J. Vimalkumar, V. Kamakoti:
Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits. 429-438 - Po-Kuan Huang, Soheil Ghiasi:
Energy-Aware Compilation for Embedded Processors with Technology Scaling Considerations. 439-453 - Deming Chen, Scott Cromar:
An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power. 454-463 - Saurabh Chaudhury, J. Srinivasa Rao, Santanu Chattopadhyay:
State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis. 464-473 - Tooraj Nikoubin, Fatemeh Eslami, Amirali Baniasadi, Keivan Navi:
A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic. 474-483 - Balaji Jayaraman, Navakanta Bhat:
Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology. 484-496 - Sherif A. Tawfik, Volkan Kursun:
Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density and Reduced Leakage Power. 497-508 - Simon Sheung Yan Ng, Steven B. Bibyk:
An Asynchronous Sigma Delta Analog to Digital Converter for Broadband Wireless Receiver with Adaptive Digital Filtering Technique. 509-519 - Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai:
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. 520-528
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