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2020 – today
- 2024
[j12]Xiaoqiang Li
, Chu Chen, Yihe Sun, Hao Cheng:
Low/Middle-Frequency Positive External- Damping Design Under Self-Stability Constraint for Inner Control Loop of Grid-Forming Converters. IEEE Trans. Ind. Electron. 71(5): 4762-4772 (2024)
2010 – 2019
- 2013
- [j11]Bo Yu, Rosa H. M. Chan, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon:
On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network. IEEE Trans. Biomed. Eng. 60(1): 198-202 (2013) - [j10]Jie Wu, Jia Wang, Kun Li, Hai Zhou, Qin Lv, Li Shang, Yihe Sun:
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 325-338 (2013) - 2012
- [j9]Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun:
Reliability Modeling and Management of Nanophotonic On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 98-111 (2012) - 2011
- [j8]Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon:
Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(4): 502-515 (2011) - [j7]Junli Gu, Yihe Sun, Steven S. Lumetta, Rakesh Kumar:
MOPED: Accelerating Data Communication on Future CMPs. IEEE Micro 31(4): 42-50 (2011) - [c19]Bo Yu, Terrence S. T. Mak, Leslie Smith, Yihe Sun, Alex Yakovlev, Chi-Sang Poon:
Memory efficient on-line streaming for multichannel spike train analysis. EMBC 2011: 2315-2318 - [c18]Allann Al-armaghany, Bo Yu, Terrence S. T. Mak, Kin-Fai Tong, Yihe Sun:
Feasibility study for future implantable neural-silicon interface devices. EMBC 2011: 3009-3015 - [c17]Bo Yu, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon:
Real-time neuronal networks reconstruction using hierarchical systolic arrays. EMBC 2011: 7298-7301 - [c16]Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun:
MOPED: Orchestrating interprocess message data on CMPs. HPCA 2011: 111-120 - 2010
- [j6]Zheng Li, Moustafa Mohamed, Hongyu Zhou, Li Shang, Alan Rolf Mickelson, Dejan Filipovic, Manish Vachharajani, Wounjhang Park, Yihe Sun:
Global On-Chip Coordination at Light Speed. IEEE Des. Test Comput. 27(4): 54-67 (2010) - [c15]Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon:
A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. FPL 2010: 556-561 - [c14]Junli Gu, Rakesh Kumar, Steven S. Lumetta, Yihe Sun:
Accelerating data movement on future chip multi-processors. IFMT 2010: 3:1-3:12 - [c13]Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun:
Power-efficient variation-aware photonic on-chip network management. ISLPED 2010: 31-36
2000 – 2009
- 2009
- [j5]Yang Xu, Hu He, Yihe Sun:
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures. J. Low Power Electron. 5(2): 123-134 (2009) - [c12]Zheng Li, Dan Fay, Alan Rolf Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun:
Spectrum: a hybrid nanophotonic-electric on-chip network. DAC 2009: 575-580 - [c11]Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe Sun:
Latency criticality aware on-chip communication. DATE 2009: 1052-1057 - [c10]Zheng Shen, Hu He, Yihe Sun:
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. DSD 2009: 505-512 - [c9]Zheng Li, Jie Wu, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun:
A high-performance low-power nanophotonic on-chip network. ISLPED 2009: 291-294 - 2008
- [j4]Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, Yihe Sun:
Transaction-Aware Network-on-Chip Resource Reservation. IEEE Comput. Archit. Lett. 7(2): 53-56 (2008) - [c8]Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei:
Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. DELTA 2008: 20-25 - 2007
- [j3]Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun:
Heuristic on a Novel Power Management System Cooperating with Compiler. J. Low Power Electron. 3(1): 22-27 (2007) - [j2]Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun:
A Video Specific Instruction Set Architecture for ASIP design. VLSI Design 2007: 58431:1-58431:7 (2007) - [c7]Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng:
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. ASAP 2007: 371-376 - 2006
- [c6]Zhou Zhixiong, Yang Xu, He Hu, Yihe Sun:
A Retargetable Compiler of VLIW ASIP for Media Signal Processing. ESA 2006: 46-52 - [c5]Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun:
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design. IIH-MSP 2006: 587-592 - 2005
- [c4]Yanjun Zhang, Hu He, Yihe Sun:
A new register file access architecture for software pipelining in VLIW processors. ASP-DAC 2005: 627-630 - 2003
- [j1]Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai:
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. J. VLSI Signal Process. 33(1-2): 191-197 (2003) - [c3]He Hu, Yihe Sun:
Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST. Asian Test Symposium 2003: 507 - 2002
- [c2]Ke Jiang, Yihe Sun:
An Optimizing Search Method of Systolic Array Design. IASTED PDCS 2002: 573-577 - 2001
- [c1]Lei Xu, Yihe Sun, Hongyi Chen:
Scan array solution for testing power and testing time. ITC 2001: 652-659
Coauthor Index
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