"A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in ..."

Xingjun Wu et al. (2003)

> Home

Details and statistics

DOI: 10.1023/A:1021110405895

access: closed

type: Journal Article

metadata version: 2020-05-20

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/vlsisp/WuCSG03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsisp/WuCSG03
Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai:
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. J. VLSI Signal Process. 33(1-2): 191-197 (2003)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.