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Fatemeh Eslami
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2010 – 2019
- 2018
- [j3]Fatemeh Eslami, Steven J. E. Wilton:
Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug. ACM Trans. Design Autom. Electr. Syst. 23(6): 72:1-72:25 (2018) - [c7]Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton:
Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. ETS 2018: 1-2 - 2016
- [j2]Fatemeh Eslami, Steven J. E. Wilton:
An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. SIGARCH Comput. Archit. News 44(4): 20-25 (2016) - [i1]Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton:
Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. CoRR abs/1606.06457 (2016) - 2015
- [c6]Fatemeh Eslami, Steven J. E. Wilton:
An adaptive virtual overlay for fast trigger insertion for FPGA debug. FPT 2015: 32-39 - 2014
- [c5]Fatemeh Eslami, Steven J. E. Wilton:
Incremental distributed trigger insertion for efficient FPGA debug. FPL 2014: 1-4 - 2013
- [c4]Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton:
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. FCCM 2013: 45-52 - [c3]Mostafa Farahani, Fatemeh Eslami, Amirali Baniasadi:
Application Specific Low Leakage data Cache for embedded processors. IGCC 2013: 1-6 - 2011
- [c2]Fatemeh Eslami, Mihai Sima:
Capacitive Boosting for FPGA Interconnection Networks. FPL 2011: 453-458
2000 – 2009
- 2009
- [j1]Tooraj Nikoubin, Fatemeh Eslami, Amirali Baniasadi, Keivan Navi:
A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic. J. Low Power Electron. 5(4): 474-483 (2009) - [c1]Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani:
Application Specific Transistor Sizing for Low Power Full Adders. ASAP 2009: 195-198
Coauthor Index
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