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Tooraj Nikoubin
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2020 – today
- 2024
- [c12]Omid Bazgir, Satwik Gali, Tooraj Nikoubin:
Area-power and Energy Efficient Substitution box (S-box) in Advanced Encryption Standard (AES). ACM Great Lakes Symposium on VLSI 2024: 263-267 - [c11]Yogeswar Reddy Thota, Tooraj Nikoubin:
TinyML for ECG Biometrics on Resource Constrained Devices. ISVLSI 2024: 521-526 - [c10]Mahdieh Grailoo, Tooraj Nikoubin, José L. Núñez-Yáñez:
Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform. NorCAS 2024: 1-6 - [e1]Inna Partin-Vaisband, Srinivas Katkoori, Lu Peng, Boris Vaisband, Tooraj Nikoubin:
Proceedings of the Great Lakes Symposium on VLSI 2024, GLSVLSI 2024, Clearwater, FL, USA, June 12-14, 2024. ACM 2024 [contents]
2010 – 2019
- 2019
- [j7]Tooraj Nikoubin, Hareesh-Reddy Basireddy:
Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells. IEEE Access 7: 17312-17327 (2019) - [j6]Hareesh-Reddy Basireddy, Karthikeya Challa, Tooraj Nikoubin:
Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1138-1147 (2019) - [c9]Priyanka Lohray, Satwik Gali, Srirathan Rangisetti, Tooraj Nikoubin:
Rounding Technique Analysis for Power-Area & Energy Efficient Approximate Multiplier Design. CCWC 2019: 420-425 - [c8]Ashish Joshi, Srirathan Rangisetti, Priyanka Lohray, Tooraj Nikoubin:
Fast & Energy Efficient Binary to BCD Converter with Complement Based Logic Design (CBLD) for BCD Multipliers. CCWC 2019: 426-434 - 2016
- [j5]Tooraj Nikoubin, Mahdieh Grailoo, Changzhi Li:
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 398-402 (2016) - [c7]Mahdieh Grailoo, Ashish Joshi, Mounika Mulkalapally, Tooraj Nikoubin:
Power and Energy Efficient Standard Cells with CDM Logic Style for Optimization of Multiplier Structures. ICCCNT 2016: 10:1-10:5 - [c6]Mounika Mulkalapally, Jacob Manning, Paul Gatewood, Tooraj Nikoubin:
High Speed, Area and Power Efficient 32-bit Vedic Multipliers. ICCCNT 2016: 11:1-11:7 - [c5]Ashish Joshi, Thejaswani Putta, Tooraj Nikoubin:
Power and Energy Efficient Standard Cell Library Design in CDM Logic Style with FinFET Transistors. ICCCNT 2016: 12:1-12:5 - [c4]Nikhil Patil, Teja Geddamuri, Tooraj Nikoubin:
Complement Based Logic Design (CBLD) for Area and Power Efficiency of Arithmetic Building Blocks. ICCCNT 2016: 13:1-13:6 - [c3]Ashish Patankar, Tooraj Nikoubin:
Wearable System for Obstacle Detection and Human Assistance Using Ultrasonic Sensor Array. ICCCNT 2016: 14:1-14:6 - 2015
- [c2]Tooraj Nikoubin, José Maria Muñoz-Ferreras, Roberto Gómez-García, Daan Liang, Changzhi Li:
Structural health monitoring of wind turbines using a low-cost portable k-band radar: An ab-initio field investigation. WiSNet 2015: 69-71 - 2014
- [c1]Yiran Li, Changzhan Gu, Tooraj Nikoubin, Changzhi Li:
Wireless radar devices for smart human-computer interaction. MWSCAS 2014: 65-68 - 2013
- [j4]Reza Faghih Mirzaee, Tooraj Nikoubin, Keivan Navi, Omid Hashemipour:
Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic. Microelectron. J. 44(12): 1238-1250 (2013) - 2010
- [j3]Tooraj Nikoubin, Mahdieh Grailoo, Sayyed Hasan Mozafari:
Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style. J. Low Power Electron. 6(4): 503-512 (2010) - [j2]Tooraj Nikoubin, Poona Bahrebar, Sara Pouri, Keivan Navi, Vaez Iravani:
Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits. VLSI Design 2010: 264390:1-264390:17 (2010)
2000 – 2009
- 2009
- [j1]Tooraj Nikoubin, Fatemeh Eslami, Amirali Baniasadi, Keivan Navi:
A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic. J. Low Power Electron. 5(4): 474-483 (2009)
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