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ORCID10th NorCAS 2024, Lund, Sweden
- 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), Lund, Sweden, October 29-30, 2024. IEEE 2024, ISBN 979-8-3315-1766-3
- Moritz Weißbrich, Alexander Meyer, Adilet Dossanov, Vadim Issakov, Guillermo Payá Vayá:
A 505nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs. 1-6 - Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn:
A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces. 1-6 - Belal Mostafa Amin, Ilkka Nissinen:
Highly linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensor. 1-6 - Hadi Mousanejad Jeddi, Mahdieh Grailoo, José L. Núñez-Yáñez:
Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks. 1-7 - Fatemeh Abbassi, Timm Ostermann, Christoph Wagner:
Enhanced Mixer-First Receiver Using Series Switch N-Path Passive Mixer for Millimeter-Wave 5G Applications. 1-5 - John Reuben, Suzanne Lancaster, Dietmar Fey, Stefan Slesazeck:
On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory. 1-6 - Florian Maurer, Michael Meidinger, Yiming Lu, Thomas Hallermeier, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf:
QoS-Aware Dynamic Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement Learning. 1-6 - Mohammed Al Shihabi, Natachai Terawatsakul, Alireza Saberkari:
Compact and Efficient Switching Power Amplifier for Micro-NMR Applications. 1-6 - Abolfazl Sajadi, Nusa Zidaric, Todor Stefanov, Nele Mentens:
A Systematic Comparison of Side-channel Countermeasures for RISC-V-based SoCs. 1-7 - Jochen Rust, Marvin Henkel, Nils Hülsmeier, Moritz Bärthel, Steffen Paul:
Exploiting SORN-Arithmetic for Efficient Cross Correlation in Low-Complexity FPGAs. 1-5 - André F. Ponchet, Javad Bagheri Asli, Alireza Saberkari, César W. V. Casañas, Atila Alvandpour, Ingemar Söderquist, Osamu Saotome:
Analysis and Design of a Reconfigurable RF-DC Rectifier for RF Energy Harvesting Systems. 1-6 - Shaown Mojumder, Simon Friedrich, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Martin Friedrich, Oliver Renke, Holger Blume, Julian Höfer, Patrick Schmidt, Jürgen Becker, Darius Grantz, Markus Kock, Jens Benndorf, Nael Fasfous, Pierpaolo Morì, Hans-Jörg Vögel, Samira Ahmadifarsani, Leonidas Kontopoulos, Ulf Schlichtmann, Kay Bierzynski:
ZuSE-KI-Mobil AI Chip Design Platform: An Overview. 1-7 - You Wu, Kei Awano, Kento Okamura, Teruaki Ono, Kohei Sakamoto, Hiroaki Kitaike, Hironori Tagawa, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, Kiichi Niitsu:
A 2 Hz, 1.2-2 V, 0.22-9 nW, 0.007 mm2 65 nm CMOS Multiple- Output Down-Converter-Less Clock Generator Using Stacked an Oscillator and Frequency Dividers for Scaling-Friendly IoTs. 1-6 - Kazi Mohammad Abidur Rahman, Abdelrahman Noshy Abdelalim Ahmed, Görschwin Fey, Ulf Kulau:
Hardware-accelerated Compression Core on RISC-V for Online-BCG Data Reduction. 1-6 - Alessandro Catania, Francesco Gagliardi, Michele Dei:
Design of Single-Bit Switched-Capacitor ΔΣ Modulators Employing Fast-Settling Techniques. 1-7 - Sergei Devadze, Christine Elizabeth Nielsen, Dmitri Mihhailov, Peeter Ellervee:
Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis. 1-7 - Rg Raghavendra, Kamlesh Singh, Milind Gopal Agrawal:
A Clock Duty Cycle Correction Circuitry for Ultra-Wide Frequency Range using Nested Loops. 1-7 - Yasir Al-Ameri, Ming Nguyen, Tomi Westerlund:
FPGA-Based Hardware Acceleration for Deep Learning in Mobile Robotics. 1-7 - Wei Cao, Alireza Saberkari, Atila Alvandpour:
High-Sensitivity Hybrid Compensated RF-to-DC Converter for Low-Power RFEH Applications. 1-6 - José L. Núñez-Yáñez:
Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device Training. 1-7 - Rashed Al Amin, Roman Obermaisser:
FPGA-based Resource Efficient High Throughput Object Detection Using Pipelined CNN and Custom SSD. 1-5 - Muhammad Ali, Ensieh Aliagha, Mahmoud Elnashar, Diana Göhringer:
RV-ProViler: Evaluating RISC-V ISA for Application-Specific Requirements. 1-7 - Julian Haase, Najdet Charaf, Alexander Groß, Diana Göhringer:
Design Space Exploration of Dynamically Reconfigurable Network-on-Chip Architectures with Multiobjective Evolutionary Algorithms. 1-7 - Raffaele Meloni, H. Peter Hofstee, Zaid Al-Ars:
Tywaves: A Typed Waveform Viewer for Chisel. 1-6 - Kari Hepola, Jatan Shrestha, Joonas Multanen, Vivienne Wang, Joni Pajarinen, Pekka Jääskeläinen:
Cycle Count Estimation of VLIW Processors Using Machine Learning. 1-7 - Jonas Schupp, Patrick Karl, Jens Nöpel, Alexander Hepp, Tim Music, Georg Sigl:
RISC-V Triplet: Tapeouts for Security Applications. 1-6 - Luca Bellemo, Giorgio Spiazzi, Andrea Bevilacqua:
On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting. 1-6 - Pablo Navarro-Torrero, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox:
Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems. 1-7 - Pau Ortega-Castro, Felipe Rojas-Muñoz, José Miguel Mora-Gutiérrez, Piedad Brox, Macarena C. Martínez-Rodríguez:
VLSI integration of a RO-based PUF into a 65 nm technology. 1-7 - Viktor Razilov, Emil Matús, Gerhard P. Fettweis:
Implementation of the Tagged Geometric History Length Access Interval Predictor. 1-4 - Fabian C. Legl, Jonas Kantic:
Fully Automated Implementation of Reservoir Computing Models on FPGAs for Nanosecond Inference Times. 1-7 - Moritz Bärthel, Nils Hülsmeier, Jochen Rust, Steffen Paul:
Quantitative Evaluation on the Limits of SORN Arithmetic Hardware Circuits. 1-5 - Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua:
On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers. 1-5 - Olle Hansson, Oscar Gustafsson, José L. Núñez-Yáñez:
Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks. 1-7 - Mayuri Bhadra, Stephanie Ecker, Daniel Albert, Ravindra Ramaiah, Sebastian Prebeck, Wolfgang Ecker:
Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond. 1-7 - Antti Nurmi, Abdesattar Kalache, Timo D. Hämäläinen:
Hardware Solutions for Eliminating Context Switching Latency in Processor-Based Hard Real-Time Systems. 1-6 - Kimiyoshi Usami, Mina Fukushima, Songxiang Wang, Kaito Nagai:
An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge Accumulation. 1-6 - Pegah Shafaghi, Yasser Rezaeiyan, Sonal Shreya, Farshad Moradi, Hooman Farkhani:
Novel Circuit for In-Memory Computing within STT-RAM Memory Blocks. 1-6 - Dumitra Iancu, Lina Tinnerberg, Ove Edfors, Liang Liu:
Indoor Positioning using Distributed MIMO: Processing Architecture and FPGA Implementation. 1-6 - Zakaria Madaoui, Henri Lunnikivi, Pawel Dzialo, Per Lindgren:
Towards modularity of the Rust RTIC real-time scheduling framework. 1-7 - Ahmad Othman, Ahmed Kamaleldin, Diana Göhringer:
AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded Applications. 1-7 - Kari Hepola, Tharaka Ranasinghe Arachchige, Joonas Multanen, Pekka Jääskeläinen:
Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom Instructions. 1-7 - Vida Sobhani, Jan Lorenz, Tobias Gemmeke:
Inter-node Communication in Multi-FPGA-based Computational Neuroscience Simulators: PHY-to-Link. 1-7 - Sebastian Jaster, Julian Haase, Diana Göhringer, Elke Franz:
Improving Reliability in Network-on-Chip with Trust-based Adaptive Routing Approaches. 1-7 - Oliver Schrape, Anselm Breitenreiter, Li Lu, Marko S. Andjelkovic, Ernesto Pun-Garcia, Marisa López-Vallejo, Milos Krstic:
Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction. 1-4 - Sebastian Haas, Christopher Dunkel, Friedrich Pauls, Mattis Hasler, Yogesh Verma:
Trustworthy Silicon: An MPSoC for a Secure Operating System. 1-7 - Md Najmussadat, Y. Tawfik, R. Ahamed, Mikko Varonen, Dristy Parveg, Antti Lamminen, Pekka Pursula, Kari A. I Halonen:
MMIC Design for Radiometer Receiver at 240 GHz in 0.13 μm SiGe BiCMOS Technology. 1-5 - Iuliia Topko, Tanja Harbaum, Jürgen Becker:
Towards a General Compilation Approach for On-device Training in Embedded Systems. 1-7 - Hiroaki Kitaike, Hironori Tagawa, Masaya Kaneko, Jin Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hiroki Wakatsuchi, Kyoya Takano, Hirofumi Shinohara, Kiichi Niitsu:
A 0.00027 mm2 1.2V 0.089pJ/bit 10Gbps 41.6 GHz Standard-Cell-Based Passive-Less Wireless OOK Transmitter with On-Chip Antenna in 12nm FinFET. 1-6 - Mikael Henriksson, Hugo Winbladh, Oscar Gustafsson:
Multi-Stream FFT Architectures for a Distributed MIMO Large Intelligent Surfaces Testbed. 1-6 - Mohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri:
Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study. 1-7 - Mahdieh Grailoo, Tooraj Nikoubin, José L. Núñez-Yáñez:
Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform. 1-6
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