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2020 – today
- 2024
[j25]Kimiyoshi Usami
, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho:
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 89-102 (2024)- [c59]Kimiyoshi Usami, Mina Fukushima, Songxiang Wang, Kaito Nagai:
An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge Accumulation. NorCAS 2024: 1-6 - 2023
- [j24]Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho:
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 532-542 (2023) - [c58]Kimiyoshi Usami, Songxiang Wang, Kaito Nagai, Giovanna Latronico, Paolo Mele:
A 200mV Operable On-Chip Temperature Sensor for IoT Devices Powered by Energy Harvesters with Ultra-Low Output Voltage. IoTaIS 2023: 65-71 - [c57]Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi:
A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c56]Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano:
Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations. NorCAS 2022: 1-7 - 2021
- [j23]Yoshinori Ono, Kimiyoshi Usami:
Energy Efficient Approximate Storing of Image Data for MTJ Based Non-Volatile Flip-Flops and MRAM. IEICE Trans. Electron. 104-C(7): 338-349 (2021) - [c55]Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho:
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops. MCSoC 2021: 273-280 - 2020
- [c54]Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda:
Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. COOL CHIPS 2020: 1-3 - [c53]Yoshinori Ono, Kimiyoshi Usami:
Energy Efficient Approximate Storing of Image Data for MTJ Based Non-volatile Memory. NVMSA 2020: 1-6
2010 – 2019
- 2018
- [c52]Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami:
Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. NVMSA 2018: 91-98 - [c51]Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami:
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. ReConFig 2018: 1-6 - 2017
- [j22]Yusuke Yoshida, Kimiyoshi Usami:
Energy-Efficient Standard Cell Memory with Optimized Body-Bias Separation in Silicon-on-Thin-BOX (SOTB). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2785-2796 (2017) - [j21]Hayate Okuhara, Yu Fujita, Kimiyoshi Usami, Hideharu Amano:
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1578-1582 (2017) - [c50]Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano:
Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. ISOCC 2017: 148-149 - [c49]Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki:
Building block multi-chip systems using inductive coupling through chip interface. ISOCC 2017: 152-154 - [c48]Masaru Kudo, Kimiyoshi Usami:
Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. NVMSA 2017: 1-6 - [c47]Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano:
Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. VLSI-SoC 2017: 1-6 - [c46]Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano:
Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI. VLSI-SoC (Selected Papers) 2017: 1-21 - 2016
- [j20]Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. IEICE Trans. Electron. 99-C(8): 909-917 (2016) - [j19]Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. 99-C(8): 926-935 (2016) - 2015
- [j18]Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. 98-C(7): 536-543 (2015) - [j17]Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. 98-C(7): 559-568 (2015) - [j16]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1376-1391 (2015) - [c45]Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano:
A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control. COOL Chips 2015: 1-3 - [c44]Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano:
An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. ISLPED 2015: 207-212 - 2014
- [c43]Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC 2014: 843-848 - [c42]Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa:
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips 2014: 1-3 - [c41]Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura:
Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE 2014: 1-6 - [c40]Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium 2014: 1 - [c39]Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC 2014: 1-7 - [c38]Yu Fujita, Kimiyoshi Usami, Hideharu Amano:
A Thermal Management System for Building Block Computing Systems. MCSoC 2014: 165-171 - 2013
- [j15]Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki:
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. 96-C(4): 404-412 (2013) - [j14]Kimiyoshi Usami:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2457 (2013) - [j13]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2597-2611 (2013) - [j12]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c37]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c36]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c35]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - [c34]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT 2013: 1-4 - 2012
- [c33]Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC 2012: 407-412 - [c32]Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano:
Trade-off analysis of fine-grained power gating methods for functional units in a CPU. COOL Chips 2012: 1-3 - [c31]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 - [c30]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [c29]Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura:
Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI 2012: 233-238 - [c28]Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura:
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED 2012: 625-632 - [c27]Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. MCSoC 2012: 59-66 - [r1]Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura:
Geyser. Handbook of Energy-Aware and Green Computing 2012: 49-65 - 2011
- [j11]Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami:
Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2499-2509 (2011) - [j10]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. 6(4): 1092-1102 (2011) - [j9]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. 4: 182-192 (2011) - [j8]Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011) - [j7]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 520-533 (2011) - [c26]Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami:
Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. ARC 2011: 230-241 - [c25]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo:
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 - [c24]Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo:
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips 2011: 1-3 - [c23]Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8 - [c22]Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura:
On-chip detection methodology for break-even time of power gated function units. ISLPED 2011: 241-246 - 2010
- [c21]Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo:
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370 - [c20]Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Adaptive power gating for function units in a microprocessor. ISQED 2010: 29-37 - [c19]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS 2010: 61-68
2000 – 2009
- 2009
- [c18]Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano:
Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS 2009: 171-182 - [c17]Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386 - 2008
- [c16]Jerry Frenkil, Ken Choi, Kimiyoshi Usami:
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. DATE 2008 - [c15]Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano:
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT 2008: 329-332 - [c14]Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617 - 2007
- [c13]Kimiyoshi Usami:
Overview on Low Power SoC Design Technology. ASP-DAC 2007: 634-636 - 2006
- [j6]Naoaki Ohkubo, Kimiyoshi Usami:
Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3482-3490 (2006) - [c12]Naoaki Ohkubo, Kimiyoshi Usami:
Delay modeling and static timing analysis for MTCMOS circuits. ASP-DAC 2006: 570-575 - [c11]Kimiyoshi Usami, Naoaki Ohkubo:
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. ICCD 2006: 155-161 - 2002
- [j5]Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa:
Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2667-2673 (2002) - [j4]Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak:
Code Coverage-Based Power Estimation Techniques for Microprocessors. J. Circuits Syst. Comput. 11(5): 557- (2002) - [c10]Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa:
Automated selective multi-threshold design for ultra-low standby applications. ISLPED 2002: 202-206 - 2000
- [c9]Kimiyoshi Usami, Mutsunori Igarashi:
Low-power design methodology and applications utilizing dual supply voltages. ASP-DAC 2000: 123-128 - [c8]Naoyuki Kawabe, Kimiyoshi Usami:
Low-power technique for on-chip memory using biased partitioning and access concentration. CICC 2000: 275-278 - [c7]Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak:
Function-level power estimation methodology for microprocessors. DAC 2000: 810-813
1990 – 1999
- 1998
- [j3]Kimiyoshi Usami, Mutsunori Igarashi, Fumihiro Minami, Takashi Ishikawa, Masahiro Kanazawa, Makoto Ichida, Kazutaka Nogami:
Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE J. Solid State Circuits 33(3): 463-472 (1998) - [j2]Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama:
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE J. Solid State Circuits 33(11): 1772-1780 (1998) - [c6]Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi:
A Clock-Gating Method for Low-Power LSI Design. ASP-DAC 1998: 307-312 - [c5]Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda:
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. CICC 1998: 495-498 - [c4]Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda:
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC 1998: 483-488 - 1997
- [c3]Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka:
A low-power design method using multiple supply voltages. ISLPED 1997: 36-41 - 1995
- [c2]Kimiyoshi Usami, Mark Horowitz:
Clustered voltage scaling technique for low-power design. ISLPD 1995: 3-8 - 1990
- [c1]Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori:
Datapath Generator Based on Gate-Level Symbolic Layout. DAC 1990: 388-393
1980 – 1989
- 1989
- [j1]Takeji Tokumaru, Eeji Masuda, Chikahiro Hori, Kimiyoshi Usami, Misao Miyata, Jun Iwamura:
Design of a 32 bit microprocessor, TX1. IEEE J. Solid State Circuits 24(4): 938-944 (1989)
Coauthor Index
[j25] [j24] [c56] [c55] [c54] [c52] [c51] [j21] [c50] [c49] [c47] [c46] [j20] [j19] [j18] [j17] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [j15] [j12] [c37] [c36] [c35] [c33] [c32] [c31] [c30] [c27] [r1] [j10] [j9] [j8] [j7] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c15] [c14]
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