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2020 – today
- 2023
[c120]Jiaxiang Li, Masao Yanagisawa, Youhua Shi:
An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators. ASICON 2023: 1-4- [c119]Yirui Su, Masao Yanagisawa, Youhua Shi:
Strategy for Improving Cycle of Maximized Energy Output of Triboelectric Nanogenerators. ICICDT 2023: 131-135 - 2021
- [j98]Lin Ye, Jinghao Ye
, Masao Yanagisawa, Youhua Shi:
Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow. IEEE Access 9: 17411-17420 (2021) - 2020
- [j97]Jinghao Ye, Masao Yanagisawa, Youhua Shi:
Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(9): 1063-1070 (2020) - [j96]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures. IEICE Trans. Inf. Syst. 103-D(7): 1618-1622 (2020) - [j95]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. IPSJ Trans. Syst. LSI Des. Methodol. 13: 10-20 (2020) - [j94]Saki Tajima, Masao Yanagisawa, Youhua Shi:
Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets. IEEE Trans. Circuits Syst. II Express Briefs 67-II(6): 1114-1118 (2020) - [c118]Jinghao Ye, Masao Yanagisawa, Youhua Shi:
A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters. APCCAS 2020: 121-124 - [c117]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. LASCAS 2020: 1-4
2010 – 2019
- 2019
- [j93]Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(4): 641-653 (2019) - [j92]Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(6): 860-865 (2019) - [j91]Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(8): 953-965 (2019) - [j90]Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
An FPGA Implementation Method based on Distributed-register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 12: 38-41 (2019) - [c116]Siya Bao, Masao Yanagisawa, Nozomu Togawa:
A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments. ICIS (best papers) 2019: 109-123 - [c115]Jinghao Ye, Masao Yanagisawa, Youhua Shi:
A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing. APCCAS 2019: 29-32 - [c114]Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi:
A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks. APCCAS 2019: 317-320 - [c113]Jinghao Ye, Masao Yanagisawa, Youhua Shi:
An Adder-Segmentation-based FIR for High Speed Signal Processing. ASICON 2019: 1-4 - [c112]Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa:
Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE 2019: 1-6 - [c111]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. ICECS 2019: 578-581 - [c110]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Error Correction Coding of Stochastic Numbers Using BER Measurement. IOLTS 2019: 243-246 - [c109]Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. ISCAS 2019: 1-4 - 2018
- [j89]Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(5): 831-843 (2018) - [j88]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1002-1013 (2018) - [j87]Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1014-1024 (2018) - [j86]Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1025-1034 (2018) - [j85]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1045-1052 (2018) - [j84]Masaru Oya, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2308-2319 (2018) - [j83]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2320-2326 (2018) - [j82]Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - [c108]Siya Bao, Masao Yanagisawa, Nozomu Togawa:
Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis. IEEE BigData 2018: 3628-3637 - [c107]Tomotaka Inoue, Kento Hasegawa, Yuki Kobayashi, Masao Yanagisawa, Nozomu Togawa:
Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach. ICCE-Berlin 2018: 1-4 - [c106]Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
Robust Indoor/Outdoor Detection Method based on Sparse GPS Positioning Information. ICCE-Berlin 2018: 1-4 - [c105]Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A Multiple Cyclic-Route Generation Method for Strolling Based on Point-of-Interests. ICCE-Berlin 2018: 1-2 - [c104]Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
Bicycle Behavior Recognition using Sensors Equipped with Smartphone. ICCE-Berlin 2018: 1-6 - [c103]Siya Bao, Masao Yanagisawa, Nozomu Togawa:
Road-illuminance level inference across road networks based on Bayesian analysis. ICCE 2018: 1-6 - [c102]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
A hardware-Trojan classification method utilizing boundary net structures. ICCE 2018: 1-4 - [c101]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. IOLTS 2018: 53-56 - [c100]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis. IOLTS 2018: 97-102 - [c99]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. ISCAS 2018: 1-5 - [c98]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A loop structure optimization targeting high-level synthesis of fast number theoretic transform. ISQED 2018: 106-111 - [c97]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. NGCAS 2018: 182-185 - [c96]Mamoru Hirota, Ayumu Tsuboi, Masayuki Yokoyama, Masao Yanagisawa:
Gesture recognition of air-tapping and its application to character input in VR space. SIGGRAPH ASIA Posters 2018: 45:1-45:2 - [c95]Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa:
An Ising model mapping to solve rectangle packing problem. VLSI-DAT 2018: 1-4 - 2017
- [j81]Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa:
Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(4): 1015-1028 (2017) - [j80]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1427-1438 (2017) - [j79]Koki Igawa, Masao Yanagisawa, Nozomu Togawa:
A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1439-1451 (2017) - [j78]Siya Bao, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa:
A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(11): 2439-2450 (2017) - [j77]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2857-2868 (2017) - [j76]Kotaro Terada, Masao Yanagisawa, Nozomu Togawa:
A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2911-2924 (2017) - [j75]Masayuki Yokoyama, Ryohei Koyama, Masao Yanagisawa:
An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices. J. Sensors 2017: 3980906:1-3980906:12 (2017) - [c94]Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Soft error tolerant latch designs with low power consumption (invited paper). ASICON 2017: 52-55 - [c93]Daiki Asai, Masao Yanagisawa, Nozomu Togawa:
Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. ASICON 2017: 64-67 - [c92]Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
A low cost and high speed CSD-based symmetric transpose block FIR implementation. ASICON 2017: 311-314 - [c91]Tomotaka Inoue, Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Designing hardware trojans and their detection based on a SVM-based approach. ASICON 2017: 811-814 - [c90]Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A stayed location estimation method for sparse GPS positioning information. GCCE 2017: 1-5 - [c89]Ryoya Momose, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa:
An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons. GCCE 2017: 1-5 - [c88]Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
A robust scan-based side-channel attack method against HMAC-SHA-256 circuits. ICCE-Berlin 2017: 79-84 - [c87]Siya Bao, Masao Yanagisawa, Nozomu Togawa:
Personalized one-day travel with multi-nearby-landmark recommendation. ICCE-Berlin 2017: 239-242 - [c86]Masaru Oya, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojan detection and classification based on steady state learning. IOLTS 2017: 215-220 - [c85]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojans classification for gate-level netlists using multi-layer neural networks. IOLTS 2017: 227-232 - [c84]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. ISCAS 2017: 1-4 - [c83]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa:
Effective write-reduction method for MLC non-volatile memory. ISCAS 2017: 1-4 - [c82]Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A selector-based FFT processor and its FPGA implementation. ISOCC 2017: 88-89 - [c81]Yuki Yahagi, Masao Yanagisawa, Nozomu Togawa:
Robust AES circuit design for delay variation using suspicious timing error prediction. ISOCC 2017: 101-102 - [c80]Ayumu Tsuboi, Mamoru Hirota, Junki Sato, Masayuki Yokoyama, Masao Yanagisawa:
A proposal for wearable controller device and finger gesture recognition using surface electromyography. SIGGRAPH ASIA (Posters) 2017: 9:1-9:2 - 2016
- [j74]Koki Igawa, Masao Yanagisawa, Nozomu Togawa:
Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms. IEICE Electron. Express 13(18): 20160641 (2016) - [j73]Koki Igawa, Masao Yanagisawa, Nozomu Togawa:
A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1278-1293 (2016) - [j72]Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1294-1310 (2016) - [j71]Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa:
Bi-Partitioning Based Multiplexer Network for Field-Data Extractors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1410-1414 (2016) - [j70]Masaru Oya, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Masao Yanagisawa, Nozomu Togawa:
Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2335-2347 (2016) - [j69]Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa:
A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2348-2362 (2016) - [j68]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2398-2411 (2016) - [c79]Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
Implementation evaluation of scan-based attack against a Trivium cipher circuit. APCCAS 2016: 220-223 - [c78]Siya Bao, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa:
A safe and comprehensive route finding method for pedestrian based on lighting and landmark. GCCE 2016: 1-5 - [c77]Keisuke Kono, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa:
Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning. GCCE 2016: 1-2 - [c76]Ryoya Yano, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa:
Pedestrian navigation based on landmark recognition using glass-type wearable devices. GCCE 2016: 1-2 - [c75]Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojans classification for gate-level netlists based on machine learning. IOLTS 2016: 203-206 - [c74]Masaru Oya, Masao Yanagisawa, Nozomu Togawa:
Redesign for untrusted gate-level netlists. IOLTS 2016: 219-220 - [c73]Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa:
Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices. ISCAS 2016: 978-981 - [c72]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A high-performance circuit design algorithm using data dependent approximation. ISOCC 2016: 95-96 - [c71]Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A delay variation and floorplan aware high-level synthesis algorithm with body biasing. ISQED 2016: 75-80 - [c70]Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
In-situ Trojan authentication for invalidating hardware-Trojan functions. ISQED 2016: 152-157 - [c69]Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa:
Rotator-based multiplexer network synthesis for field-data extractors. SoCC 2016: 194-199 - 2015
- [j67]Kotaro Terada, Masao Yanagisawa, Nozomu Togawa:
A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1366-1375 (2015) - [j66]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1376-1391 (2015) - [j65]Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1392-1405 (2015) - [j64]Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1406-1418 (2015) - [j63]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2484-2493 (2015) - [j62]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa:
ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2494-2504 (2015) - [j61]Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa:
A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2537-2546 (2015) - [j60]Huiqian Jiang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2547-2555 (2015) - [j59]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. Inf. Media Technol. 10(1): 1-7 (2015) - [c68]Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
Clock skew estimate modeling for FPGA high-level synthesis and its application. ASICON 2015: 1-4 - [c67]Keita Igarashi, Masao Yanagisawa, Nozomu Togawa:
Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. ASICON 2015: 1-4 - [c66]Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa:
Small-sized and noise-reducing power analyzer design for low-power IoT devices. ASICON 2015: 1-4 - [c65]Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
A low-power soft error tolerant latch scheme. ASICON 2015: 1-4 - [c64]Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. ASICON 2015: 1-4 - [c63]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa:
A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC 2015: 496-501 - [c62]Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A score-based classification method for identifying hardware-trojans at gate-level netlists. DATE 2015: 465-470 - [c61]Masayuki Yokoyama, Ryohei Koyama, Masao Yanagisawa:
Muscle analysis of hand and forearm during tapping using surface electromyography. GCCE 2015: 595-598 - [c60]Kengo Takeda, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa:
A visible corner-landmark based route finding algorithm for pedestrian navigation. GCCE 2015: 601-602 - [c59]Siya Bao, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa:
A landmark-based route recommendation method for pedestrian walking strategies. GCCE 2015: 672-673 - [c58]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. ICCAD 2015: 682-689 - [c57]Kotaro Terada, Masao Yanagisawa, Nozomu Togawa:
A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. ISCAS 2015: 2129-2132 - [c56]Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. SoCC 2015: 7-12 - [c55]Koki Ito, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa:
Partitioning-based multiplexer network synthesis for field-data extractors. SoCC 2015: 263-268 - 2014
- [j58]Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa:
Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1444-1451 (2014) - [j57]Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa:
Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2434-2442 (2014) - [j56]Yuta Hagio, Masao Yanagisawa, Nozomu Togawa:
A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. Inf. Media Technol. 9(4): 446-455 (2014) - [j55]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. IPSJ Trans. Syst. LSI Des. Methodol. 7: 74-80 (2014) - [j54]Yuta Hagio, Masao Yanagisawa, Nozomu Togawa:
A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 7: 81-90 (2014) - [c54]Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. APCCAS 2014: 244-247 - [c53]Kotaro Terada, Masao Yanagisawa, Nozomu Togawa:
A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. APCCAS 2014: 248-251 - [c52]Huiqian Hang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-based side-channel attack on Camellia cipher using scan signatures. APCCAS 2014: 252-255 - [c51]Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. APCCAS 2014: 300-303 - [c50]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
A write-reducing and error-correcting code generation method for non-volatile memories. APCCAS 2014: 304-307 - [c49]Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Secure scan design using improved random order and its evaluations. APCCAS 2014: 555-558 - [c48]Masashi Shio, Masao Yanagisawa, Nozomu Togawa:
Linear and bi-linear interpolation circuits using selector logics and their evaluations. ISCAS 2014: 1436-1439 - [c47]Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa:
Scan-based attack on the LED block cipher using scan signatures. ISCAS 2014: 1460-1463 - [c46]Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Throughput driven check point selection in suspicious timing error prediction based designs. LASCAS 2014: 1-4 - 2013
- [j53]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(1): 312-321 (2013) - [j52]Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1283-1292 (2013) - [j51]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2597-2611 (2013) - [j50]Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. Inf. Media Technol. 8(3): 867-874 (2013) - [j49]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. Inf. Media Technol. 8(4): 913-923 (2013) - [j48]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. IPSJ Trans. Syst. LSI Des. Methodol. 6: 101-111 (2013) - [j47]Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. J. Inf. Process. 21(3): 572-579 (2013) - [c45]Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa:
Scan-based attack against Trivium stream cipher independent of scan structure. ASICON 2013: 1-4 - [c44]Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi:
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON 2013: 1-4 - [c43]Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. ISCAS 2013: 1432-1435 - [c42]Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa:
A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. ISCAS 2013: 1736-1739 - [c41]Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa:
Suspicious timing error prediction with in-cycle clock gating. ISQED 2013: 335-340 - [c40]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Secure Scan Design with Dynamically Configurable Connection. PRDC 2013: 256-262 - [c39]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT 2013: 1-4 - 2012
- [j46]Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures. IEICE Electron. Express 9(17): 1414-1422 (2012) - [j45]Seungju Lee, Masao Yanagisawa, Nozomu Togawa:
A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(9): 1538-1549 (2012) - [j44]Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
Scan-Based Attack on AES through Round Registers and Its Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2338-2346 (2012) - [j43]Koji Ara, Tomoaki Akitomi, Nobuo Sato, Kunio Takahashi, Hideyuki Maeda, Kazuo Yano, Masao Yanagisawa:
Integrating Wearable Sensor Technology into Project-management Process. Inf. Media Technol. 7(2): 882-894 (2012) - [j42]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures. Inf. Media Technol. 7(4): 1319-1330 (2012) - [j41]Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa:
A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution. IPSJ Trans. Syst. LSI Des. Methodol. 5: 96-105 (2012) - [j40]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 5: 106-117 (2012) - [j39]Koji Ara, Tomoaki Akitomi, Nobuo Sato, Kunio Takahashi, Hideyuki Maeda, Kazuo Yano, Masao Yanagisawa:
Integrating Wearable Sensor Technology into Project-management Process. J. Inf. Process. 20(2): 406-418 (2012) - [j38]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 176-181 (2012) - [c38]Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-based attack against DES cryptosystems using scan signatures. APCCAS 2012: 599-602 - [c37]Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa:
Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. APCCAS 2012: 603-606 - [c36]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. APCCAS 2012: 607-610 - [c35]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. ISCAS 2012: 576-579 - [c34]Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient high-level synthesis for HDR architectures with clock gating. ISOCC 2012: 135-138 - [c33]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Dynamically changeable secure scan architecture against scan-based side channel attack. ISOCC 2012: 155-158 - 2011
- [j37]Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Speeding-up exact and fast FIFO-based cache configuration simulation. IEICE Electron. Express 8(14): 1161-1167 (2011) - [j36]Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto:
Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(4): 1082-1090 (2011) - [j35]Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto:
Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2482-2489 (2011) - [j34]Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. Inf. Media Technol. 6(2): 276-285 (2011) - [j33]Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Inf. Media Technol. 6(4): 1076-1091 (2011) - [j32]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scan Vulnerability in Elliptic Curve Cryptosystems. IPSJ Trans. Syst. LSI Des. Methodol. 4: 47-59 (2011) - [j31]Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. IPSJ Trans. Syst. LSI Des. Methodol. 4: 60-69 (2011) - [j30]Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 4: 150-165 (2011) - [j29]Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 4: 166-181 (2011) - 2010
- [j28]Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2481-2489 (2010) - [j27]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1294-1299 (2010) - [c32]Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. APCCAS 2010: 712-715 - [c31]Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. APCCAS 2010: 1083-1086 - [c30]Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. APCCAS 2010: 1139-1142 - [c29]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scan-based attack against elliptic curve cryptosystems. ASP-DAC 2010: 407-412 - [c28]Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ISCAS 2010: 921-924 - [c27]Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS 2010: 1867-1870
2000 – 2009
- 2009
- [j26]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An L1 Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1442-1453 (2009) - [j25]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(9): 2304-2317 (2009) - [j24]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3119-3127 (2009) - [j23]Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3169-3179 (2009) - [j22]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Scan-Based Attack Based on Discriminators for AES Cryptosystems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3229-3237 (2009) - [j21]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Two-Level Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3238-3247 (2009) - [c26]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Exact and fast L1 cache simulation for embedded systems. ASP-DAC 2009: 817-822 - [c25]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Design-for-secure-test for crypto cores. ITC 2009: 1 - 2008
- [j20]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Trans. Inf. Syst. 91-D(3): 776-780 (2008) - [j19]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3514-3523 (2008) - [j18]Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. Inf. Media Technol. 3(4): 691-703 (2008) - [j17]Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 1: 78-90 (2008) - [j16]Mika Naganawa, Yuichi Kimura, Junichi Yano, Masahiro Mishina, Masao Yanagisawa, Kenji Ishii, Keiichi Oda, Kiichi Ishiwata:
Robust estimation of the arterial input function for Logan plots using an intersectional searching algorithm and clustering in positron emission tomography for neuroreceptor imaging. NeuroImage 40(1): 26-34 (2008) - [c24]Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh:
FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm. APCCAS 2008: 701-704 - [c23]Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. APCCAS 2008: 705-708 - [c22]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Unknown response masking with minimized observable response loss and mask data. APCCAS 2008: 1779-1781 - [c21]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
GECOM: Test data compression combined with all unknown response masking. ASP-DAC 2008: 577-582 - [c20]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702 - 2007
- [j15]Shuichi Takitoh, Shogo Fujii, Yoichi Mase, Junichi Takasaki, Toshimasa Yamazaki, Yozo Ohnishi, Masao Yanagisawa, Yusuke Nakamura, Naoyuki Kamatani:
Accurate automated clustering of two-dimensional data for single-nucleotide polymorphism genotyping by a combination of clustering methods: evaluation by large-scale real data. Bioinform. 23(4): 408-413 (2007) - [c19]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS 2007: 149-152 - 2006
- [j14]Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. IEICE Trans. Electron. 89-C(3): 243-249 (2006) - [j13]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 996-1004 (2006) - [c18]Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC 2006: 594-599 - [c17]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC 2006: 653-658 - [c16]Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito:
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT 2006: 136-144 - 2005
- [j12]Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 876-884 (2005) - [j11]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Trans. Inf. Syst. 88-D(7): 1340-1349 (2005) - [c15]Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A processor core synthesis system in IP-based SoC design. ASP-DAC 2005: 286-291 - [c14]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura:
Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium 2005: 386-389 - [c13]Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) 2005: 3499-3502 - 2004
- [c12]Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A thread partitioning algorithm in low power high-level synthesis. ASP-DAC 2004: 74-79 - [c11]Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC 2004: 250-255 - [c10]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC 2004: 743-750 - [c9]Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium 2004: 432-437 - 2003
- [j10]Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(5): 1082-1092 (2003) - [j9]Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3056-3062 (2003) - [j8]Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3099-3109 (2003) - [j7]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3218-3224 (2003) - [c8]Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A hardware/software partitioning algorithm for SIMD processor cores. ASP-DAC 2003: 135-140 - 2002
- [j6]Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 827-834 (2002) - [j5]Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2603-2611 (2002) - [j4]Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2655-2666 (2002) - [c7]Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) 2002: 171-176 - [c6]Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
VLSI Architecture for a Flexible Motion Estimation with Parameters. ASP-DAC/VLSI Design 2002: 452-457 - 2001
- [c5]Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Area/delay estimation for digital signal processor cores. ASP-DAC 2001: 156-161 - 2000
- [c4]Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki:
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). ASP-DAC 2000: 309-312
1990 – 1999
- 1999
- [j3]Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki:
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. J. Circuits Syst. Comput. 9(1-2): 09-112 (1999) - [j2]Tingrong Zhao, Masao Yanagisawa, Tatsuo Ohtsuki:
Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations. J. Circuits Syst. Comput. 9(1-2): 67-82 (1999) - [c3]Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ASP-DAC 1999: 335-338 - 1998
- [j1]Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 803-818 (1998) - [c2]Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki:
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. ASP-DAC 1998: 265-274 - [c1]Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki:
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. ASP-DAC 1998: 519-526
Coauthor Index
[j38] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [j27] [c32] [c31] [c30] [c29] [c28] [c27] [j26] [j25] [j24] [j23] [j22] [j21] [c26] [c25] [j20] [j19] [j18] [j17] [c24] [c23] [c22] [c21] [c20] [c19] [j14] [j13] [c18] [c17] [j12] [j11] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [j10] [j9] [j8] [j7] [c8] [j6] [j5] [j4] [c7] [c6] [c5] [c4] [j3] [j2] [c3] [j1] [c2] [c1]
[c120] [c119] [j98] [j97] [j94] [c118] [c115] [c114] [c113] [c109] [j87] [j86] [c94] [c92] [c71] [c70] [j66] [j64] [j61] [c65] [c64] [c62] [c56] [c51] [c49] [c46] [j51] [c43] [c41] [c40] [c39] [j46] [j44] [j38] [c36] [c33] [j27] [c30] [c27] [j25] [j24] [c25] [j20] [j19] [c22] [c21] [c20] [c19] [j13] [c17] [c16] [c14] [c9] [j9]
[j96] [j95] [c117] [j93] [j92] [j91] [j90] [c116] [c112] [c111] [c110] [c109] [j89] [j88] [j87] [j86] [j85] [j84] [j83] [j82] [c108] [c107] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [c98] [c97] [c95] [j81] [j80] [j79] [j78] [j77] [j76] [c94] [c93] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [j74] [j73] [j72] [j71] [j70] [j69] [j68] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [j67] [j66] [j65] [j64] [j63] [j62] [j61] [j60] [j59] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c60] [c59] [c58] [c57] [c56] [c55] [j58] [j57] [j56] [j55] [j54] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [j53] [j52] [j51] [j50] [j49] [j48] [j47] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [j46] [j45] [j44] [j42] [j41] [j40] [j38] [c38] [c37] [c36] [c35] [c34] [c33] [j37] [j36] [j35] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [j27] [c32] [c31] [c30] [c29] [c28] [c27] [j26] [j25] [j24] [j23] [j22] [j21] [c26] [c25] [j20] [j19] [j18] [j17] [c24] [c23] [c22] [c21] [c20] [c19] [j14] [j13] [c18] [c17] [j12] [j11] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [j10] [j8] [j7] [c8] [j6] [j5] [j4] [c7] [c6] [c5] [c4] [j3] [c3] [j1] [c2] [c1]
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