default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISOCC 2016: Jeju, South Korea
- International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016. IEEE 2016, ISBN 978-1-5090-3219-8
- Dukju Ahn, Jiwoong Park, Patrick P. Mercier:
A 200-kHz/6.78-MHz wireless power transmitter featuring concurrent dual-band operation. 1-2 - Arnold C. Paglinawan
, Edison E. Mojica:
Electrical performance analysis of biogas fuelled generator with purifier. 3-4 - Sangeeta Singh, J. V. R. Ravindra, B. Rajendra Naik:
Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip. 5-6 - M. Vafaiee, Majid Jalili, Reza Sabbaghi-Nadooshan, Hamid Sarbazi-Azad:
An efficient on-chip network with packet compression capability. 7-8 - Song-Woo Choi, Min-Woo Seo, Suk-Ju Kang:
Prediction-based latency compensation technique for head mounted display. 9-10 - Jaehyuk Choi:
Review of low power image sensors for always-on imaging. 11-12 - Chong-Yang Lin, Kuei-Ann Wen:
MEMS resonator based thermometer SoC design in CMOS 0.18 μm standard process. 13-14 - Chun-Lin Chien, Kuei-Ann Wen:
A decouple structured gyroscope with integrated readout circuit on standard 0.18pm 1P6M CMOS technology. 15-16 - Po-Chun Chuang, Kuei-Ann Wen:
Monolithic MEMS resonator based pressure sensor and readout design. 17-18 - Dong-Shik Kim, Won-Sang Yoon, Sang-Hoon Chai:
Implementation of RF frequency synthesizer for smart utility network system. 19-20 - Jusung Kim, Keunkwan Ryu, Sungchan Kim, Sang-Hun Lee:
LNA topologies for RX carrier aggregation. 21-22 - Jin-Ho Kim, Yong Moon:
A design of dual-band smart tag. 23-24 - Sungjin Shin, Hyunchol Shin:
Design of 28GHz CMOS phased array T/R circuits for 3-dimensional beamforming applications. 25-26 - No Yong Kwon, Bora Kim, Yong Moon:
A study of META-voltage controlled oscillator and prescaler using 65nm CMOS process: META-VCO and prescaler using 65nm CMOS precess. 27-28 - Bruce C. Kim, Sang-Bock Cho:
Recent advances in TSV inductors for 3D IC technology. 29-30 - Ramu Seva, Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Approximate stochastic computing (ASC) for image processing applications. 31-32 - Yu-Liang Tsai, Pei-Yun Tsai, Ching-Horng Lee, Li-Mei Chen, Sz-Yuan Lee:
Design and implementation of multi-mode block adaptive quantizer for synthetic aperture radar. 33-34 - Yong Deok Ahn, Suk-Ju Kang:
Mapping table-based fisheye image correction for low computational complexity. 35-36 - Weizhen Wang, Jun Han, Zhicheng Xie, Shan Huang, Xiaoyang Zeng:
Cryptographie coprocessor design for IoT sensor nodes. 37-38 - Soyeon Kang, Inhyuk Choi, Hyeonchan Lim, Sungyoul Seo, Sungho Kang:
Software-based embedded core test using multi-polynomial for test data reduction. 39-40 - Ho Sub Lee, Suk-Ju Kang, Young Hwan Kim:
Motion vector smoothing of boundary of moving object for frame rate up-conversion. 41-42 - Wei Pang, Hantao Huang, Fengwei An, Hao Yu:
Low-power and real-time computer vision on-chip. 43-44 - Sangho Yoon, Young Hwan Kim:
Image interpolation based on Hessian analysis. 45-46 - Joonggeun Ahn, Jihoon Kim, Youngjoo Lee:
Sharpness-aware real-time haze removal for advanced driver assistance systems. 47-48 - Sumedh Dhabu, Chip-Hong Chang:
A new scheme for secret-hiding in DSP circuits. 49-50 - Kohei Yamada, Yosuke Toyama, Hiroki Ishikuro:
A programmable ΔΣ SAR-ADC with charge shuttling technique. 51-52 - Behnam Samadpoor Rikan, Sang-Yun Kim, Kang-Yoon Lee:
11-Bit 1.8uW 40KS/s segmented SAR ADC for sensor applications. 55-56 - Seongheon Shin, Hyung-Joun Yoo:
A pipelined time stretching for high throughput counter-based time-to-digital converters. 57-58 - Hengzhou Yuan, Yang Guo, Yao Liu, Bin Liang, Qian-cheng Guo, Jia-wei Tan:
A low-jitter self-biased phase-locked loop for SerDes. 59-60 - Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya:
36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector. 61-62 - Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface. 63-64 - Majid Jalili, Julien Bourgeois, Hamid Sarbazi-Azad:
Power-efficient partially-adaptive routing in on-chip mesh networks. 65-66 - Kenta Shimazaki, Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki, Toshitaka Tsuda, Nozomu Togawa:
Hash-table and balanced-tree based FIB architecture for CCN routers. 67-68 - Yeon-Jin Kim, Zhe-Yan Piao, Jin-Gyun Chung, In-Gul Jang, Kyung-Ju Cho:
Low latency IFFT design for 3GPP LTE. 69-70 - Yuhwai Tseng, Ting-You Lin, Songwen Yau, Yingchieh Ho, Chauchin Su:
A 0.5V/22 μW low power transceiver IC for use in ESC intra-body communication system. 71-72 - Kiwon Yoon, Suhyeong Choi, Youngsoo Shin:
Area efficient neuromorphic circuit based on stochastic computation. 73-74 - Esther Kim, Deokgwan Jeong, Taehyoun Oh:
A 4.1mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process. 75-76 - Jungwoo Seo, Joonsang Yu, Jongeun Lee, Kiyoung Choi:
A new approach to binarizing neural networks. 77-78 - Sangkyu Lee, Hoyoung Tang, Kyungrak Choi, Jongsun Park:
Customized SRAM design for low power video code applications. 79-80 - Cyrel Ontimare Manlises, Febus Reidj G. Cruz, Wen-Yaw Chung:
ISFET with built-in calibration registers through segmented eight-bit binary search in three-point algorithm using FPGA. 81-82 - Jiayi Ma, Cong Hao, Wencan Zhang, Takeshi Yoshimura:
Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip. 83-84 - Shugang Wei:
Computation of modular multiplicative inverses using residue signed-digit additions. 85-86 - Dongsuk Jeon:
Design techniques for ultra-efficient computing. 87-88 - Van-Phuc Hoang, Van-Lan Dao, Cong-Kha Pham:
An ultra-low power AES encryption core in 65nm SOTB CMOS process. 89-90 - Pei-Ching Huang, Shi-Yu Huang:
Cell-based delay locked loop compiler. 91-92 - Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Hybrid GDI-NCL for area/power reduction. 93-94 - Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A high-performance circuit design algorithm using data dependent approximation. 95-96 - Keewon Cho, Jooyoung Kim, Hayoung Lee, Sungho Kang:
Discussion of cost-effective redundancy architectures. 97-98 - Beomsang Yoo, Taehui Na, Byungkyu Song, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang:
Equalization scheme analysis for high-density spin transfer torque random access memory. 99-100 - Kangwook Jo, Kyungseon Cho, Hongil Yoon:
Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA). 101-102 - Chua-Chin Wang, Chia-Lung Hsieh:
Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process. 103-104 - Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue:
Single-flux-quantum cache memory architecture. 105-106 - Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Parallel decoding for multi-stage BCH decoder. 107-108 - JuHyung Hong, Sangwoo Han, Eui-Young Chung:
A RAM cache approach using host memory buffer of the NVMe interface. 109-110 - Hung-Wen Lin, Jin-Yi Lin:
A passband lock loop circuit system for band pass filter. 111-112 - V. Priya, Murali Krishna Rajendran, Shourya Kansal, Ashudeb Dutta:
A 11mV single stage thermal energy harvesting regulator with effective control scheme for extended peak load. 113-114 - Yuki Matsuda, Akio Shimizu, Yohei Ishikawa, Sumio Fukai:
Buffer with Neuron MOSFETs for class-G headphone driver. 115-116 - Sung-min Lee, Ju Eon Kim, Dong-Hyun Yoon, Kwang-Hyun Baek:
Energy-efficient spread second capacitor capacitive-DAC for SAR ADCs. 117-118 - Yui-Hwan Sa, Pyo-Hoon Son, Ki-Hong Kim, Hi-Seok Kim, Hyeong-Woo Cha:
A design of new voltage to current converter with high linearity and wide tuning. 119-120 - Seyed Mohammad Noghabaei, Mohamad Sawan:
A fully integrated high-efficiency step-up DC-DC converter for energy harvesting applications. 121-122 - Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi:
An integrated optical parallel adder as a first step towards light speed data processing. 123-124 - Yong-Bin Kim:
Integrated circuits design using carbon nanotube field effect transistor. 125-126 - Asim Khan, Chong-Min Kyung:
Memory efficient hardware accelerator for kernel support vector machine based pedestrian detection. 127-128 - Young-Woo Lee, Junghwan Kim, Inhyuk Choi, Sungho Kang:
A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. 129-130 - Sang-Hwan Kim, Byoung Soo Choi, Jang-Kyoo Shin, Jae-Hyoun Park, Kyoung-Il Lee:
Novel pixel calibration circuit for bolometer-type uncooled infrared image sensor. 131-132 - Deng-Shian Wang, Yun-Shen Liu, Chua-Chin Wang:
A novel frequency-shift readout system for CEA concentration detection application. 133-134 - Seongjoo Lee, Minkyu Song:
Design of a configurable bit-resolution CMOS image sensor for the image depth extraction. 139-140 - Tae Hyun Kim, Hyunyul Lim, Sungho Kang:
P-backtracking: A new scan chain diagnosis method with probability. 141-142 - Yonghee Yun, Young Hwan Kim:
Design-time energy optimization for asymmetric multiprocessor system-on-chip. 143-144 - Seung-Yeob Lee, Joon-Sung Yang:
eFuse based IC authentication architecture. 145-146 - Heetae Kim, Inhyuk Choi, Jaeil Lim, Hyunggoy Oh, Sungho Kang:
Process variation-aware bridge fault analysis. 147-148 - Junghwan Kim, Young-Woo Lee, Minho Cheong, Sungyoul Seo, Sungho Kang:
A test methodology to screen scan-path failures. 149-150 - Mustafijur Rahman, Ramesh Harjani:
CMOS energy efficient integrated radios for emerging low power standards. 151-152 - Zhaoyang Weng, Jingjing Dong, Hanjun Jiang, Zhihua Wang:
A 400MHz 3-10Mbps transceiver IC with ∼0.3 nJ/bit TX/RX energy efficiency for body area applications. 153-154 - Sudhakar Pamarti, N. Sinha, Sameed Hameed, Mansour Rachid:
Time-varying circuit approaches for software defined and cognitive radio applications. 155-156 - Tse-Wei Wang, Yi-Lin Tsai, Chong-Rong Lee, Fu-Lian Hung, Tsung-Hsien Lin:
A 0.5-V sub-mW energy-efficient receiver in 0.18-μm CMOS for IoT applications. 157-158 - Jiwon Bang, Junghwan Pyo, Yongjin Jeong:
Automatic image deviation detection for AVM auto-calibration. 159-160 - Eunchong Lee, Sang-Seol Lee, Youngbae Hwang, Sung-Joon Jang:
Hardware implementation of fast traffic sign recognition for intelligent vehicle system. 161-162 - Junghwan Pyo, Jiwon Bang, Yongjin Jeong:
Front collision warning based on vehicle detection using CNN. 163-164 - Ronnie O. Serfa Juan, Min Woo Jeong, Hi-Seok Kim:
Development of burst error effect reduction algorithm for CAN using interleaver method. 165-166 - Hohyon Song, Bosun Jeong, Hyunkyu Choi, Taeho Cho, Hweihn Chung:
Hardware implementation of aggregated channel features for ADAS. 167-168 - Kristofor B. Gibson, Truong Q. Nguyen, Hannoh Yoon:
Improvements in parallel SIMD implementation of single image defogging. 169-170 - Yeejin Lee, Truong Q. Nguyen, Changyoung Han:
Dehazing in color filter array domain. 171-172 - Yan Gong, Yeejin Lee, Truong Q. Nguyen:
Nighttime image enhancement applying dark channel prior to raw data from camera. 173-174 - Zhaowei Cai, Matthew Jacobsen, Nuno Vasconcelos:
Pedestrian detection aided by temporal prior. 175-176 - Kunyao Chen, Subarna Tripathi, Youngbae Hwang, Truong Q. Nguyen:
Moving objects detection using classifying object proposals for driver assistance system. 177-178 - Soon Kwon, Hyuk-Jae Lee:
Dense stereo-based real-time ROI generation for on-road obstacle detection. 179-180 - Jong-Chern Lee, Jihwan Kim, Kyung Whan Kim, Young Jun Ku, Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jaejin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee:
High bandwidth memory(HBM) with TSV technique. 181-182 - Jinsan Kwon, Taeho Hwang, Dong-Sun Kim:
Emulation of processing in memory architecture for application development. 183-184 - Young-Jong Jang, Byung-Soo Kim, Dong-Sun Kim, Taeho Hwang:
Implementation of a low-overhead processing-in-memory architecture. 185-186 - Hongsik Jeong:
High density PCM(phase change memory) technology. 187-188 - Young-Hyun Baek:
Robust optical fingerprint sensor to moisture fingerprints. 189-190 - Ryota Shimizu, Shusuke Yanagawa, Yasutaka Monde, Hiroki Yamagishi, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Deep learning application trial to lung cancer diagnosis for medical sensor systems. 191-192 - Takashi Nakada, Hiroshi Nakamura, Toshifumi Nakamoto, Toru Shimizu:
Normally-off power management for sensor nodes of global navigation satellite system. 193-194 - Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Hiroyuki Kondo:
Low-power multi-sensor system with normally-off sensing technology for IoT applications. 195-196 - Kazunari Inoue, Yuji Yano:
A large scale access-control list for IoT security comprising embedded IP-core and DDR DRAM. 197-198 - Kiyotaka Komoku, Kazutami Arimoto, Tomoyuki Yokogawa, Hitoshi Yamauchi, Yoichiro Sato, Hidekuni Takao:
3D2 processing architecture - High reliability and low power computing for novel nano tactile sensor array. 199-200 - Noriyuki Miura, Shivam Bhasin:
Attack sensing against EM leakage and injection. 201-202 - Daisuke Fujimoto, Yusuke Nagahama, Tsutomu Matsumoto:
How to design hardware prime field multipliers for bilinear pairing. 203-204 - Yang Huang, Letian Huang, Xiaohang Wang:
A lightweight metric for the evaluation of network congestion in NoC-based MPSoC. 205-206 - Hai Peng, Letian Huang, John Chen:
An efficient FPGA implementation for odd-even sort based KNN algorithm using OpenCL. 207-208 - Shuyu Chen, Letian Huang, Song Li:
An address remapping algorithm to reduce power consumption in NoC-based chip-multiprocessors. 209-210 - Tianchan Guan, Xiaoyang Zeng, Letian Huang, Tianchan Guan, Mingoo Seok:
Neural network based seizure detection system using raw EEG data. 211-212 - Tso-Bing Juang, Ying-Ren Lee, Chin-Chieh Chiu:
Low-cost concurrent error detection schemes for logarithmic converters. 213-214 - Uzma Jamil, Shehzad Khalid, M. Usman Akram:
Digital image preprocessing and hair artifact removal by using Gabor wavelet. 215-216 - Yuechun Wang, Ka Lok Man, Robert G. Maunder, Jin-Kyung Lee, Kyung Ki Kim:
A flexible software defined radio-based UHF RFID reader based on the USRP and LabView. 217-218 - Lanxiang Wang, Menglong He, Zhao Wang, Mark Leach, Jing Chen Wang, Ka Lok Man, Eng Gee Lim:
Radio frequency energy harvesting technology. 219-220 - SangGi Do, Seungwon Kim, Seokhyeong Kang:
Skew control methodology for useful-skew implementation. 221-222 - Fan Yang, Gowri Sankar Ramachandran, Piers W. Lawrence, Sam Michiels, Wouter Joosen, Danny Hughes:
μPnP-WAN: Wide area plug and play sensing and actuation with LoRa. 225-226 - Jung Woo Shin, Jung-Hwan Oh, Sang Muk Lee, Seung Eun Lee:
CAN FD controller for in-vehicle system. 227-228 - Ji Kwang Kim, Oh Seong Gwon, Seung Eun Lee:
Design of an area-efficient hardware filter for embedded system. 229-230 - Sang-Yub Lee, Duck Keun Park, Jae-Jin Ko, Jae Kyu Lee, Choul Jun Kang:
A network architecture design of embedded system for media service in bus. 231-232 - Keonhee Lee, Hyuntae Ju, Yong Mu Jeong, Soo-Young Min:
A study on improvement of recognition accuracy by applying machine learning algorithms to the vision-based traffic condition analysis system. 233-234 - Eun-Ae Park, Hyuntae Ju, Yong Mu Jeong, Soo-Young Min:
A study on improvement of vision-based traffic condition analysis system by comparing feature data of images. 235-236 - Hyo Sub Choi, Deepak Ghimire:
A study on river water level monitoring method in a debris barrier. 237-238 - Gyutae Oh, Inhye Park, Sang-Yub Lee, Jae-Jin Ko:
Software design for GUI display in the wearable device. 239-240 - Himchan Park, Zhang-Zhi Yu, Jinwoo Kim, Jinwook Burm:
Resolution tunable ring oscillator type TDC. 241-242 - YoungBae Kim, Qiang Tong, Ken Choi, Yunsik Lee:
Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics. 243-244 - Junsub Yoon, Jongsun Kim:
A MDLL-based multi-phase clock multiplier. 247-248 - Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, Keiji Kishine:
Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system. 249-250 - Chang-Bum Park, Chan-Kyeong Jung, Shin-Il Lim:
A transient enhanced external capacitor-less LDO with a CMOS only sub-bandgap voltage reference. 251-252 - Jongsun Kim, Bongho Bae:
A fast-locking clock multiplying DLL. 253-254 - Sang Heon Lee, Seong Jae Hyeon, Kim Jong Gu, Kwang Sub Yoon:
A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBs. 255-256 - Byoung-Kwan Jeon, Seong-Kwan Hong, Oh-Kyong Kwon:
A low-power 10-bit single-slope ADC using power gating and multi-clocks for CMOS image sensors. 257-258 - Nguyen Huu Tho, Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang:
A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector. 259-260 - Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, Keiji Kishine:
Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS. 261-262 - Hong-Jhih Chen, Jau-Ji Jou, Tien-Tsorng Shih:
Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter. 263-264 - JiHoon Kim, YoungJu Hwang, Yong Moon:
A study of the referenceless CDR based on PLL. 265-266 - Jin-Ho Kim, Yong Moon:
A design of NFC analog front-end with the frequency selector. 267-268 - Seongrae Kim, Junhee Lee, Youngmin Kim:
Speed-adaptive ratio-based lane detection algorithm for self-driving vehicles. 269-270 - Suk-Hui Lee, Ki-Jin Kim, Kwang-Ho Ahn, Sung-il Bang:
A design of tunable component for font end module. 271-272 - Haengson Son, Seonyoung Lee, Kyoungwon Min:
Efficient and real-time stereo matching hardware architecture for high-resolution image. 273-274 - Hyung Seok Kim, Hyouk-Kyu Cha:
A low-power, low-noise neural recording amplifier for implantable biomedical devices. 275-276 - Su-Jeong Yun, Chi-Ho Lin:
Design of emotion lighting control system on the power spectrum algorithm. 277-278 - Hyung Seok Kim, Hyouk-Kyu Cha:
A low-power capacitive-feedback CMOS neural recording amplifier for biomedical applications. 279-280 - Hyoung-Ro Lee, Chi-Ho Lin, Won-Jong Kim:
Development of an IoT-based visitor detection system. 281-282 - (Withdrawn) Current mode four-quadrant multiplier design using CNTFET. 283-284
- Dominik Auras, Sebastian Birke, Tobias Piwczyk, Rainer Leupers, Gerd Ascheid:
A flexible MCMC detector ASIC. 285-286 - Eunbi Ku, Chulho Chung, Byungcheol Kang, Jaeseok Kim:
Throughput enhancemnet with optimal fragmented MSDU size for fragmentation and aggregation scheme in WLANs. 287-288 - (Withdrawn) Design of NFC transceiver for automotive applications. 289-290
- Sung Jun Lee, Jae Ho Jung, Bong Hyuk Park:
Possibility verification of drone detection radar based on pseudo random binary sequence. 291-292 - Zhe-Yan Piao, Jin-Gyun Chung:
Design of low latency successive cancellation decoder for polar codes. 293-294 - Sunghyun Kim, Youngmin Kim:
Adaptive approximate adder (A3) to reduce error distance for image processor. 295-296 - Shuai Li, Ken Choi, Yunsik Lee:
Artificial neural network implementation in FPGA: A case study. 297-298 - Yunseok Jang, Junwon Mun, Jaeseok Kim:
Resource-efficient FPGA architecture of Canny edge detector. 299-300 - Wei Zhang, Youde Hu, Keji Cui, Dongxuan Bao, Dashan Pan, Lebo Wang, Li-Rong Zheng:
Standing wave oscillator based clock distribution. 301-302 - Yunho Park, Jonghyuk Kwon, Youngjoo Lee:
Area-efficient and high-speed binary divider architecture for bit-serial interfaces. 303-304 - Jinkyu Kim, Juyeob Kim, Byungjo Kim, Miyoung Lee, Joohyun Lee:
Hardware design exploration of fully-connected deep neural network with binary parameters. 305-306 - Jong Kang Park, Jun Sung Go, Jong Tae Kim:
A pre-characterization method for multiple single-event transient analysis in cell-based designs. 307-308 - Sang-Seol Lee, Eunchong Lee, Youngbae Hwang, Sung-Joon Jang:
Hardware implementation of fast high dynamic range processor for real-time 4K UHD video. 309-310 - Rahaprian Mudiarasan Premavathi, Qiang Tong, Ken Choi, Yunsik Lee:
A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability. 311-312 - Taemin Lee, Sungjoo Yoo:
A dual-retention time architecture towards secure and high performance STT-RAM main memory subsystem. 313-314 - Taemin Lee, Sungjoo Yoo:
Selective refresh to avoid read disturb errors in STT-RAM main memory. 315-316 - Chulhoon Kim, Chanho Lee:
Design of eMMC controller with multiple channels. 317-318 - Nguyen Xuan Truong, Huyk-Jae Lee:
Energy-based iterative cost aggregation in depth estimation with a stereo camera. 319-320 - Jaehyuk So, Junwon Mun, Kyungmook Oh, Jaeseok Kim:
Implementation of Low complexity inter prediction for IoT systems. 321-322 - Geun-Jun Kim, Bongsoon Kang:
Halo effect suppression for single image haze removal method. 323-324 - Chang-Hee Park, Hyun-Tae Kim, Young-Min Jang, Sang-Bock Cho:
A design of real time detection IP with color detection for surveillance. 325-326 - Lu Xiao, Xiao-Xuan Huang, Yi-Chang Lu:
Non-photorealistic rendering from real video sequences with discontinuity reduction using fast video segmentation. 327-328 - Sukho Lee, Hyunmi Kim:
An H.265/HEVC 4K UHD slim codec design with shared prediction unit architecture. 329-330 - Young Ho Kim, Tae-Sun Kim, Myung Hoon Sunwoo, Jae Heon Jeong:
Fast CU size decision method for HEVC using CU split information of adjacent frames. 331-332 - Heekyeong Jeon, Kwanho Lee, Seonghyung Han, Kwangyeob Lee:
The parallelization of convolution on a CNN using a SIMT based GPGPU. 333-334 - Tae-Chul Hong, Kunseok Kang, Kwangjae Lim, Jae Young Ahn:
Transmission timing configuraiton for control and non-payload communication of unmanned aerial vehicle. 335-336 - Huajuan Zhang, Hao Xiao, Ning Wu:
A system-level design of MapReduce-based embedded multiprocessor system-on-chips. 337-338 - Donghoon Seong, Kichang Jang, Wonjoon Hwang, Hyeondeok Jeon, Joongho Choi:
Radio-frequency energy-harvesting IC with DC-DC converter. 339-340 - Hyun-Young Lee, Byeong-Chan Jeon, Won-ki Park, Sung-Chul Lee:
Design and verification of sensorless BLDC motor start-up logic with FPGA. 341-342 - Donglie Gu, Shengpeng Tang, Jianxiong Xi, Lenian He, Kexu Sun:
A dimmable and power-compensated AC direct LED driver with high efficiency. 343-344 - Tzung-Je Lee:
HV switch using differential voltage shaping driver for 13 series li-ion battery cells BMS. 345-346 - Tae-Heon Lee, Jong-Gu Kim, Kwang Sub Yoon:
A CMOS buck converter with PFM / hysteretic mode. 347-348 - (Withdrawn) A single inductor multiple output(SIMO) buck/boost DC-DC converter with output error-driven random control. 349-350
- Shengpeng Tang, Xianzhi Meng, Donglie Gu, Jianxiong Xi, Lenian He, Kexu Sun:
A synchronous boost converter with high speed and high accuracy peak current control unit. 351-352 - Byung Gun Joung, Yangho Seo, Chulwoo Kim:
A digital low-dropout(DLDO) regulator with 14dB power supply rejection enhancement. 353-354 - Tae-Hee You, Jeongbin Kim, Minyoung Im, Eui-Young Chung:
FPGA power estimation simulator for dynamic input data. 355-356 - Jyun-Yan Li, Ing-Jer Huang:
Full system verification of compatible microprocessors with a dual physical core verification platform. 357-358 - Jong Hyuk Park, Joon-Sung Yang:
Memory ECC architecutre utilizing memory column spares. 359-360
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-14 21:09 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
