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2020 – today
- 2020
[j11]Yuuki Tanaka
, Yuuki Suzuki, Shugang Wei:
Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation. J. Circuits Syst. Comput. 29(9): 2050136:1-2050136:8 (2020)
2010 – 2019
- 2016
- [c17]Shugang Wei:
Computation of modular multiplicative inverses using residue signed-digit additions. ISOCC 2016: 85-86 - 2015
- [c16]Shugang Wei:
Fast signed-digit arithmetic circuits for residue number systems. ICECS 2015: 344-347 - 2014
- [j10]Yuuki Tanaka, Shugang Wei:
Efficient squaring circuit using canonical signed-digit number representation. IEICE Electron. Express 11(2): 20130955 (2014) - [c15]Shugang Wei:
Conversions between RNS and mixed-radix numbers using signed-digit arithmetic. ISIC 2014: 600-603 - 2013
- [j9]Changjun Jiang, Shugang Wei:
RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2n-1, 2n + 1, 22n + 1, 2n} USING SIGNED-DIGIT NUMBER. J. Circuits Syst. Comput. 22(1) (2013) - [j8]Mingda Zhang, Shugang Wei:
High-Speed Modular Multipliers Based on a New Binary Signed-Digit Adder Tree Structure. J. Circuits Syst. Comput. 22(6) (2013) - 2012
- [c14]Shugang Wei:
An RSA encryption implementation method using residue signed-digit arithmetic circuits. BMEI 2012: 1299-1303 - [c13]Changjun Jiang, Shugang Wei:
Residue-weighted number conversion for moduli set {22n - 1, 22n+1 - 1, 2n} using signed-digit number. NEWCAS 2012: 9-12 - 2011
- [c12]Mingda Zhang, Shugang Wei:
Efficient residue checker using new binary modular adder tree structure for error detection of arithmetic. FSKD 2011: 2427-2431
2000 – 2009
- 2006
- [j7]Shuangching Chen, Shugang Wei:
New Booth Modulo m Multipliers with Signed-Digit Number Arithmetic. Inf. Media Technol. 1(1): 212-221 (2006) - [j6]Shuangching Chen, Shugang Wei:
Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2n-1, 2n, 2n+1). Inf. Media Technol. 1(2): 899-908 (2006) - [j5]Shugang Wei, Kensuke Shimizu:
Modulo (2p plusminus 1) Multipliers Using a Three-operand Modular Signed-digit Addition Algorithm. J. Circuits Syst. Comput. 15(1): 129-144 (2006) - [c11]Shuangching Chen, Shugang Wei:
Weighted-to-residue and residue-to-weighted converters with three-moduli (2n-1, 2n, 2n+1) signed-digit architectures. ISCAS 2006 - 2005
- [j4]Shugang Wei, Kensuke Shimizu:
Dynamic Range Compression Characteristics Using an Interpolating Polynomial for Digital Audio Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(2): 586-589 (2005) - [c10]Shugang Wei:
Number conversions between RNS and mixed-radix number system based on Modulo (2p - 1) signed-digit arithmetic. SBCCI 2005: 160-165 - 2003
- [j3]Shugang Wei, Kensuke Shimizu:
Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits. J. Circuits Syst. Comput. 12(1): 41-54 (2003) - [c9]Shugang Wei, Kensuke Shimizu:
Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic. ISCAS (5) 2003: 221-224 - 2002
- [c8]Shugang Wei, Shuangching Chen, Kensuke Shimizu:
Fast modular multiplication using Booth recoding based on signed-digit number arithmetic. APCCAS (2) 2002: 31-36 - [c7]Shugang Wei, Kensuke Shimizu:
Residue signed-digit arithmetic circuit with a complement of modulus and the application to RSA encryption processor. ICECS 2002: 591-594 - 2001
- [c6]Shugang Wei, Kensuke Shimizu:
Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System. DFT 2001: 72-77 - [c5]Shugang Wei, Kensuke Shimizu:
Fast residue arithmetic multipliers based on signed-digit number system. ICECS 2001: 263-266 - 2000
- [c4]Shugang Wei, Kensuke Shimizu:
Residue arithmetic circuits using a signed-digit number representation. ISCAS 2000: 24-27
1990 – 1999
- 1999
- [c3]Shugang Wei, Kensuke Shimizu:
Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation. Great Lakes Symposium on VLSI 1999: 218- - [c2]Shugang Wei, Kensuke Shimizu:
Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits. VLSI Design 1999: 212-217 - 1998
- [c1]Shugang Wei, Kensuke Shimizu:
Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits. ISMVL 1998: 276-281 - 1991
- [j2]Shugang Wei, Michitaka Kameyama, Tatsuo Higuchi:
Performance evaluation of a multivalued rsa encryption vlsi. Syst. Comput. Jpn. 22(7): 12-21 (1991) - 1990
- [j1]Michitaka Kameyama, Shugang Wei, Tatsuo Higuchi:
Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits. Syst. Comput. Jpn. 21(6): 21-31 (1990)
Coauthor Index
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