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2020 – today
- 2024
[j115]Martin Lukac, Saadat Nursultan, Georgiy Krylov, Oliver Keszöcze, Abilmansur Rakhmettulayev, Michitaka Kameyama:
Geometric Refactoring of Quantum and Reversible Circuits Using Graph Algorithms. IEICE Trans. Inf. Syst. 107(8): 930-939 (2024)- [c100]Martin Lukac, Krzysztof Podlaski, Shinobu Nagayama, Michitaka Kameyama:
Ternary Function Classification Using Machine Learning. ISMVL 2024: 65-71 - 2023
- [c99]Martin Lukac
, Michitaka Kameyama:
Verification Based Algorithm Selection. IDT 2023: 25-30 - 2022
- [c98]Martin Lukac, Krzysztof Podlaski, Michitaka Kameyama:
Approximate Function Classification. ICCS (1) 2022: 207-213 - 2021
- [j114]Martin Lukac, Pawel Kerntopf, Michitaka Kameyama:
Optimization of LNN Reversible Circuits Using an Analytic Sifting Method. J. Circuits Syst. Comput. 30(9): 2150166:1-2150166:23 (2021) - 2020
- [c97]Martin Lukac, Ayazkhan Bayanov, Albina Li, Kamila Abdiyeva, Nadira Izbassarova, Magzhan Gabidolla, Michitaka Kameyama:
Selecting Algorithms Without Meta-features. ICPR Workshops (4) 2020: 607-621
2010 – 2019
- 2018
- [c96]Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama:
CNOT-Measure Quantum Neural Networks. ISMVL 2018: 186-191 - [c95]Kenichi Takada, Michitaka Kameyama:
High-Accuracy Scene Recognition and Its Application to Highly-Safe Intelligent Systems. SMC 2018: 2528-2533 - 2017
- [c94]Katsuhiko Shimabukuro, Michitaka Kameyama:
Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic. ISMVL 2017: 19-24 - [c93]Martin Lukac, Michitaka Kameyama, Yevgeniya Migranova:
Live-feeling communication: Multi-algorithm approach to the estimation of human intentions. SMC 2017: 2152-2157 - [i6]Martin Lukac, Gerhard W. Dueck, Michitaka Kameyama, Anirban Pathak:
Building a Completely Reversible Computer. CoRR abs/1702.08715 (2017) - [i5]Martin Lukac, Aigerim Bazarbayeva, Michitaka Kameyama:
Context Based Visual Content Verification. CoRR abs/1709.00141 (2017) - 2016
- [i4]Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama:
Reasoning and Algorithm Selection Augmented Symbolic Segmentation. CoRR abs/1608.03667 (2016) - [i3]Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama:
On Minimal Accuracy Algorithm Selection in Computer Vision and Intelligent Systems. CoRR abs/1608.03832 (2016) - 2015
- [j113]Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2658-2669 (2015) - [j112]Martin Lukac, Michitaka Kameyama:
An algorithm selection based platform for image understanding using high-level symbolic feedback and machine learning. Int. J. Mach. Learn. Cybern. 6(3): 417-434 (2015) - [j111]Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama:
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 619-630 (2015) - [c92]Michitaka Kameyama:
Novel VLSI Architectures for Real-World Intelligent Systems. ISMVL 2015: 132 - [i2]Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama:
Symbolic Segmentation Using Algorithm Selection. CoRR abs/1505.07934 (2015) - 2014
- [j110]Martin Lukac, Dipal Shah, Marek A. Perkowski, Michitaka Kameyama:
Synthesis of Quantum Arrays from Kronecker Functional Lattice Diagrams. IEICE Trans. Inf. Syst. 97-D(9): 2262-2269 (2014) - [j109]Xu Bai, Michitaka Kameyama:
Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network. IEICE Trans. Inf. Syst. 97-D(9): 2278-2285 (2014) - [j108]Xu Bai, Michitaka Kameyama:
Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI. IEICE Trans. Electron. 97-C(10): 1028-1035 (2014) - [j107]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, Michitaka Kameyama:
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. J. Comput. Eng. 2014: 634269:1-634269:8 (2014) - [j106]Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller:
Reversible, Information-Preserving Logic and Its Application. J. Multiple Valued Log. Soft Comput. 23(3-4): 379-406 (2014) - [c91]Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama:
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing. APCCAS 2014: 639-642 - [c90]Martin Lukac, Maher Hawash, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf:
Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits Patterns. DSD 2014: 708-711 - [c89]Martin Lukac, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf, Claudio Moraga:
Analysis of Faults in Reversible Computing. ISMVL 2014: 115-120 - [c88]Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka:
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. ISMVL 2014: 214-219 - 2013
- [j105]Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama:
RFID-based localization with Non-Blocking tag scanning. Ad Hoc Networks 11(8): 2264-2272 (2013) - [j104]Xu Bai, Michitaka Kameyama:
A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme. IEICE Trans. Inf. Syst. 96-D(7): 1449-1456 (2013) - [j103]Xu Bai, Michitaka Kameyama:
A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits. IEICE Trans. Electron. 96-C(8): 1083-1093 (2013) - [j102]Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama:
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design. IEICE Trans. Inf. Syst. 96-D(8): 1632-1644 (2013) - [j101]Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2576-2586 (2013) - [j100]Martin Lukac, Michitaka Kameyama, Marek A. Perkowski:
Quantum Finite State Machines - a Circuit Based Approach. Int. J. Unconv. Comput. 9(3-4): 267-301 (2013) - [j99]Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama:
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures. J. Multiple Valued Log. Soft Comput. 20(5-6): 595-623 (2013) - [c87]Martin Lukac, Michitaka Kameyama, Kosuke Hiura:
Natural image understanding using algorithm selection and high-level feedback. Intelligent Robots and Computer Vision: Algorithms and Techniques 2013: 86620D - [c86]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment. EMBC 2013: 651-654 - [c85]Martin Lukac, Michitaka Kameyama:
Bayesian Network for algorithm selection: Real-world hierarchy for nodes reduction. iCAST/UMEDIA 2013: 69-75 - [c84]Maher Hawash, Martin Lukac, Michitaka Kameyama, Marek A. Perkowski:
Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format. ISMVL 2013: 41-46 - [c83]Xu Bai, Michitaka Kameyama:
Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI. ISMVL 2013: 164-169 - [c82]Xu Bai, Michitaka Kameyama:
An Area-Efficient Multiple-Valued Reconfigurable VLSI Architecture Using an X-Net. ISMVL 2013: 272-277 - [c81]Martin Lukac, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf:
Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences. ISMVL 2013: 322-327 - 2012
- [j98]Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama:
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. 95-D(2): 354-363 (2012) - [j97]Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. IEICE Trans. Electron. 95-C(8): 1434-1443 (2012) - [j96]Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama:
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Trans. Electron. 95-C(12): 1872-1882 (2012) - [j95]Bo Sun, Michitaka Kameyama:
Driver's Intention Estimation Based on Bayesian Networks for a Highly-Safe Intelligent Vehicle. J. Robotics Mechatronics 24(1): 219-225 (2012) - [j94]Xu Bai, Nobuaki Okada, Michitaka Kameyama:
A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme. J. Multiple Valued Log. Soft Comput. 20(1-2): 1-18 (2012) - [j93]Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski:
High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation? J. Multiple Valued Log. Soft Comput. 20(1-2): 89-120 (2012) - [c80]Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama:
FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. ISCAS 2012: 1339-1342 - [c79]Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. ISCAS 2012: 3017-3020 - [c78]Shogo Kisara, Michitaka Kameyama:
Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits. ISMVL 2012: 104-109 - [c77]Xu Bai, Michitaka Kameyama:
Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture. ISMVL 2012: 208-213 - [c76]Yoshichika Fujioka, Michitaka Kameyama:
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme. ISOCC 2012: 235-238 - 2011
- [j92]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(1): 342-351 (2011) - [j91]Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama:
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. IEICE Trans. Electron. 94-C(10): 1669-1679 (2011) - [j90]Kan Watanabe, Masaru Fukushi, Michitaka Kameyama:
Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing. Inf. Media Technol. 6(2): 362-374 (2011) - [j89]Kan Watanabe, Masaru Fukushi, Michitaka Kameyama:
Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing. J. Inf. Process. 19: 39-51 (2011) - [j88]Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama:
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. IEEE Trans. Circuits Syst. Video Technol. 21(10): 1453-1466 (2011) - [j87]Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1394-1406 (2011) - [c75]Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. ASP-DAC 2011: 89-90 - [c74]Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama:
High Performance Tag Singulation for Memory-Less RFID Systems. ICC 2011: 1-6 - [c73]Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama:
Non-blocking tag scanning for passive RFID localization. ISDA 2011: 1140-1145 - [c72]Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller:
Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation. ISMVL 2011: 131-138 - [i1]Maarti nLukac, Marek A. Perkowski, Michitaka Kameyama:
Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics. CoRR abs/1107.3383 (2011) - 2010
- [j86]Dalia Nashat, Xiaohong Jiang, Michitaka Kameyama:
Group Testing Based Detection of Web Service DDoS Attackers. IEICE Trans. Commun. 93-B(5): 1113-1121 (2010) - [j85]Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama:
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. IEICE Trans. Electron. 93-C(8): 1338-1348 (2010) - [j84]Michitaka Kameyama:
Foreword. IEICE Trans. Inf. Syst. 93-D(8): 2025 (2010) - [j83]Nobuaki Okada, Michitaka Kameyama:
Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits. IEICE Trans. Inf. Syst. 93-D(8): 2126-2133 (2010) - [j82]Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama:
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. IEICE Trans. Inf. Syst. 93-D(8): 2134-2144 (2010) - [j81]Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama:
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2570-2580 (2010) - [c71]Martin Lukac, Marek A. Perkowski, Michitaka Kameyama:
Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions. IEEE Congress on Evolutionary Computation 2010: 1-8 - [c70]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA 2010: 179-186 - [c69]Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama:
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. ERSA 2010: 271-274 - [c68]Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama:
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA 2010: 281-284 - [c67]Martin Lukac, Michitaka Kameyama, Marek A. Perkowski:
Adaptive Selection of Intelligent Processing Modules and its Applications. IC-AI 2010: 513-520 - [c66]Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama:
Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals. ISMVL 2010: 179-184
2000 – 2009
- 2009
- [j80]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Trans. Electron. 92-C(4): 539-549 (2009) - [j79]Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama:
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 403-416 (2009) - [c65]Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC 2009: 119-120 - [c64]Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama:
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA 2009: 145-150 - [c63]Masanori Hariyama, Keita Tanji, Michitaka Kameyama:
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. ERSA 2009: 263-266 - [c62]Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama:
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA 2009: 271-274 - [c61]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA 2009: 291-294 - [c60]Nobuaki Okada, Michitaka Kameyama:
Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. ISMVL 2009: 54-59 - [c59]Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama:
Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. ISMVL 2009: 233-238 - 2008
- [j78]Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama:
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. IEICE Trans. Electron. 91-C(4): 479-486 (2008) - [j77]Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Trans. Electron. 91-C(4): 517-525 (2008) - [j76]Masanori Hariyama, Shota Ishihara, Michitaka Kameyama:
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Trans. Electron. 91-C(9): 1419-1426 (2008) - [j75]Nobuaki Okada, Michitaka Kameyama:
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation. IEICE Trans. Electron. 91-C(9): 1437-1443 (2008) - [j74]Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama:
Memory Allocation for Multi-Resolution Image Processing. IEICE Trans. Inf. Syst. 91-D(10): 2386-2397 (2008) - [j73]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3596-3606 (2008) - [c58]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA 2008: 201-207 - [c57]Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama:
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA 2008: 309-310 - [c56]Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama:
FPGA implementation of a vehicle detection algorithm using three-dimensional information. IPDPS 2008: 1-5 - [c55]Nobuaki Okada, Michitaka Kameyama:
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. ISMVL 2008: 180-185 - 2007
- [j72]Michitaka Kameyama:
Special Section on VLSI Technology toward Frontiers of New Market. IEICE Trans. Electron. 90-C(10): 1849 (2007) - [j71]Tasuku Ito, Michitaka Kameyama:
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. J. Multiple Valued Log. Soft Comput. 13(4-6): 553-568 (2007) - [j70]Nobuaki Okada, Michitaka Kameyama:
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. J. Multiple Valued Log. Soft Comput. 13(4-6): 619-632 (2007) - [c54]Nobuaki Okada, Michitaka Kameyama:
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. ISMVL 2007: 25 - [c53]Tasuku Ito, Michitaka Kameyama:
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. ISMVL 2007: 39 - 2006
- [j69]Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama:
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. IEICE Trans. Electron. 89-C(11): 1551-1558 (2006) - [j68]Masanori Hariyama, Sho Ogata, Michitaka Kameyama:
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. IEICE Trans. Electron. 89-C(11): 1655-1661 (2006) - [c52]W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama:
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. APCCAS 2006: 1264-1267 - [c51]Masanori Hariyama, Michitaka Kameyama:
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. APCCAS 2006: 1803-1806 - [c50]Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama:
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. IPDPS 2006 - [c49]Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama:
Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture. ISMVL 2006: 6 - [c48]Haque Mohammad Munirul, Michitaka Kameyama:
Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit. ISMVL 2006: 13 - [c47]Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama:
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ISMVL 2006: 17 - [c46]Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi:
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. ISVLSI 2006: 193-198 - 2005
- [j67]Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama:
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. IEICE Trans. Inf. Syst. 88-D(7): 1486-1491 (2005) - [j66]Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3298-3305 (2005) - [j65]Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama:
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3516-3522 (2005) - [j64]Michitaka Kameyama, Takahiro Hanyu, Takafumi Aoki:
Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 407-436 (2005) - [j63]Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama:
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 481-497 (2005) - [j62]Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama:
Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 619-632 (2005) - [j61]Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama:
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. IEEE Trans. Computers 54(6): 642-650 (2005) - [c45]Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama:
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. IPDPS 2005 - [c44]Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi:
VLSI architecture based on packet data transfer scheme and its application. ISCAS (2) 2005: 1786-1789 - [c43]Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama:
Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer. ISMVL 2005: 114-119 - [c42]Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama:
Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic. ISMVL 2005: 120-125 - [c41]Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama:
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. ISVLSI 2005: 46-50 - 2004
- [j60]Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu:
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI. IEEE J. Solid State Circuits 39(6): 919-926 (2004) - [c40]Haque Mohammad Munirul, Michitaka Kameyama:
Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic. ISMVL 2004: 26-30 - [c39]Haque Mohammad Munirul, Michitaka Kameyama:
Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications. ISMVL 2004: 328-333 - [c38]Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. ISVLSI 2004: 243-248 - [c37]Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama:
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. ISVLSI 2004: 258-259 - 2003
- [j59]Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama:
Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization. J. Multiple Valued Log. Soft Comput. 9(1): 5-21 (2003) - [j58]Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama:
Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications. J. Multiple Valued Log. Soft Comput. 9(1): 23-42 (2003) - [c36]Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama:
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. ISMVL 2003: 99-104 - [c35]Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Dynamic Source-Coupled Logic. ISMVL 2003: 207-212 - 2002
- [c34]Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama:
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL 2002: 161-167 - [c33]Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama:
Fully Source-Coupled Logic Based Multiple-Valued VLSI. ISMVL 2002: 270-275 - [c32]Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama:
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. ISVLSI 2002: 95-100 - 2001
- [c31]Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama:
VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. ICRA 2001: 1168-1173 - [c30]Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama:
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. ISMVL 2001: 21-26 - [c29]Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran:
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. ISMVL 2001: 167-172 - 2000
- [j57]Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama:
Architecture of a high-performance stereo vision VLSI processor. Adv. Robotics 14(5): 329-332 (2000) - [j56]Michitaka Kameyama:
Editorial: Intelligent Integrated Systems for Human-Oriented Information Society. J. Robotics Mechatronics 12(5): 501 (2000) - [j55]Masanori Hariyama, Michitaka Kameyama:
Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture. J. Robotics Mechatronics 12(5): 521-526 (2000) - [j54]Masanori Hariyama, Michitaka Kameyama:
Path Planning Based on Distance Transformation and Its VLSI Implementation. J. Robotics Mechatronics 12(5): 527-533 (2000) - [j53]Hideki Kazama, Masanori Hariyama, Michitaka Kameyama:
Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction. J. Robotics Mechatronics 12(5): 534-540 (2000) - [c28]Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama:
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. ISMVL 2000: 382-390 - [c27]Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama:
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL 2000: 423-429 - [c26]Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama:
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL 2000: 438-446 - [c25]Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama:
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. PRDC 2000: 27-36
1990 – 1999
- 1999
- [j52]Yoshichika Fujioka, Michitaka Kameyama:
Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture. Syst. Comput. Jpn. 30(12): 43-51 (1999) - [c24]Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama:
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL 1999: 30-35 - [c23]Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama:
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1999: 275-279 - 1998
- [j51]Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama:
Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. Syst. Comput. Jpn. 29(11): 40-47 (1998) - [j50]Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama:
Design and evaluation of a digit-parallel multiple-valued content-addressable memory. Syst. Comput. Jpn. 29(11): 48-54 (1998) - [c22]Masanori Hariyama, Michitaka Kameyama:
Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. ICRA 1998: 3691-3696 - [c21]Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama:
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1998: 134-139 - [c20]Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama:
Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. ISMVL 1998: 270-275 - 1997
- [j49]Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama:
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. Syst. Comput. Jpn. 28(2): 54-61 (1997) - [j48]Koji Kobayashi, Michitaka Kameyama, Tatsuo Higuchi:
Communication network protocol for real-time distributed control and its LSI implementation. IEEE Trans. Ind. Electron. 44(3): 418-426 (1997) - [c19]Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama:
Low-power multiple-valued current-mode integrated circuit with current-source control and its application. ASP-DAC 1997: 413-418 - [c18]Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama:
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1997: 175-182 - 1996
- [j47]Michitaka Kameyama:
Editorial: Integration of Intelligence for Robotics in VLSI Chips. J. Robotics Mechatronics 8(6): 491 (1996) - [j46]Michitaka Kameyama:
Highly-Safe Intelligent Integrated Systems. J. Robotics Mechatronics 8(6): 492-495 (1996) - [j45]Michitaka Kameyama, Yoshichika Fujioka:
VLSI Processor System for Robotics. J. Robotics Mechatronics 8(6): 496-499 (1996) - [j44]Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama:
Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects. J. Robotics Mechatronics 8(6): 501-507 (1996) - [j43]Michitaka Kameyama, Masayuki Sasaki:
Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure. J. Robotics Mechatronics 8(6): 516-523 (1996) - [j42]Takahiro Hanyu, N. Kanagawa, Michitaka Kameyama:
Design of a one-transistor-cell multiple-valued CAM. IEEE J. Solid State Circuits 31(11): 1669-1674 (1996) - [j41]Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama:
Design of a one-transistor-cell multiple-valued CAM. IEEE J. Solid State Circuits 31(11): 1669-1674 (1996) - [j40]Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi:
Author's Reply. IEEE Trans. Computers 45(5): 639 (1996) - [c17]Masami Nakajima, Michitaka Kameyama:
Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. ISMVL 1996: 104-109 - [c16]Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama:
Quaternary Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1996: 224-229 - 1995
- [j39]Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama:
Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate. IEICE Trans. Inf. Syst. 78-D(8): 951-958 (1995) - [j38]Michitaka Kameyama:
Digital Control Parallel VLSI Processor. J. Robotics Mechatronics 7(5): 419 (1995) - [j37]Takahiro Hanyu, Michitaka Kameyama:
A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic. IEEE J. Solid State Circuits 30(11): 1239-1245 (1995) - [c15]M. Ryu, Michitaka Kameyama:
Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. ISMVL 1995: 20-27 - [c14]Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL 1995: 64-71 - [c13]Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama:
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. ISMVL 1995: 92-97 - 1994
- [j36]Michitaka Kameyama:
Editorial: Intelligent Integrated Systems for Robotics. J. Robotics Mechatronics 6(2): 119 (1994) - [j35]Michitaka Kameyama:
Next-Generation Intelligent Integrated Systems Based on Multiple-Valued Digital Processing. J. Robotics Mechatronics 6(2): 120-123 (1994) - [j34]Yoshichika Fujioka, Michitaka Kameyama, Tatsuo Higuchi:
Coordinate Transformation VLSI Processor for Redundant Manipulator Control. J. Robotics Mechatronics 6(2): 124-130 (1994) - [j33]Yoshifumi Sasaki, Michitaka Kameyama:
Design of a Model-Based Robot Vision VLSI Processor. J. Robotics Mechatronics 6(2): 131-136 (1994) - [j32]Masanori Hariyama, Michitaka Kameyama:
Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles. J. Robotics Mechatronics 6(2): 137-142 (1994) - [j31]Bumchul Kim, Michitaka Kameyama:
Latency Minimization of Parallel VLSI Processors for Robotics Using Integer Programming. J. Robotics Mechatronics 6(2): 143-149 (1994) - [j30]Shigeki Abe, Michitaka Kameyama, Tatsuo Higuchi:
Design of an Intelligent Fault-Tolerant System for Real-World Applications. J. Robotics Mechatronics 6(2): 150-154 (1994) - [j29]Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi:
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. IEEE Trans. Computers 43(1): 34-42 (1994) - [c12]Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL 1994: 19-26 - [c11]Masami Nakajima, Michitaka Kameyama:
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations. ISMVL 1994: 223-230 - 1993
- [j28]Shoui Kaqahito, Makoto Ishida, Tetsuro Nakamura, Kentaro Mizuno, Michitaka Kameyama, Tatsuo Higuchi:
Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations. Syst. Comput. Jpn. 24(5): 40-52 (1993) - [c10]Yoshichika Fujioka, Michitaka Kameyama:
2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control. ICRA (3) 1993: 149-154 - [c9]Masami Nakajima, Michitaka Kameyama:
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. ISMVL 1993: 283-288 - 1992
- [j27]Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi:
Interconnection-Free Biomolecular Computing. Computer 25(11): 41-50 (1992) - [j26]Michitaka Kameyama, Tadao Amada, Tatsuo Higuchi:
Highly parallel collision detection processor for intelligent robots. IEEE J. Solid State Circuits 27(4): 500-506 (1992) - [j25]Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi:
Design of an ultrahigher-valued biocomputing system based on set-valued logic networks. Syst. Comput. Jpn. 23(7): 35-44 (1992) - [c8]Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi:
Design of a Multiple-Valued VLSI Processor for Digital Control. ISMVL 1992: 322-329 - [c7]Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi:
Residue Arithmetic Based Multiple-Valued VLSI Image Processor. ISMVL 1992: 330-336 - [c6]Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi:
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. ISMVL 1992: 382-388 - 1991
- [j24]Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi:
Design of a robust fault-tolerant multiplier. Syst. Comput. Jpn. 22(2): 10-18 (1991) - [j23]Shugang Wei, Michitaka Kameyama, Tatsuo Higuchi:
Performance evaluation of a multivalued rsa encryption vlsi. Syst. Comput. Jpn. 22(7): 12-21 (1991) - [c5]Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi:
High-Performance VLSI Processor for Robot Inverse Dynamics Computation. ICCD 1991: 608-611 - [c4]Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi:
Design of Interconnection-Free Biomolecular Computing System. ISMVL 1991: 173-180 - 1990
- [j22]Michitaka Kameyama:
Editorial: Computer Architecture for Robotics. J. Robotics Mechatronics 2(6): 417 (1990) - [j21]Tadao Amada, Michitaka Kameyama, Tatsuo Higuchi:
Design of a Parallel Collision Detection Check VLSI Processor for Robot Manipulator. J. Robotics Mechatronics 2(6): 418-423 (1990) - [j20]Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi:
Design of a Matrix Multiply-Addition VLSI Processor for Robot control. J. Robotics Mechatronics 2(6): 424-430 (1990) - [j19]Tatsuo Higuchi, Michitaka Kameyama:
Robot Electronics System. J. Robotics Mechatronics 2(6): 471-473 (1990) - [j18]Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi:
Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems. IEEE J. Solid State Circuits 25(1): 125-131 (1990) - [j17]Michitaka Kameyama, Shugang Wei, Tatsuo Higuchi:
Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits. Syst. Comput. Jpn. 21(6): 21-31 (1990) - [j16]Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi:
Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation. Syst. Comput. Jpn. 21(8): 59-71 (1990) - [j15]Michitaka Kameyama, Takafumi Aoki, Tatsuo Higuchi:
Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model. Syst. Comput. Jpn. 21(9): 1-12 (1990) - [c3]Michitaka Kameyama:
Toward the Age of Beyond-Binary Electronics and Systems. ISMVL 1990: 162-166 - [c2]Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi:
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. ISMVL 1990: 355-362
1980 – 1989
- 1989
- [j14]Michitaka Kameyama, Tatsuo Higuchi:
VLSI Computer for Robotics. J. Robotics Mechatronics 1(1): 68-73 (1989) - [j13]Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi:
Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic. IEEE J. Solid State Circuits 24(5): 1404-1411 (1989) - [j12]Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi:
Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation. Syst. Comput. Jpn. 20(6): 69-79 (1989) - [c1]Michitaka Kameyama, Takao Matsumoto, Hideki Egami, Tatsuo Higuchi:
Implementation of a high performance LSI for inverse kinematics computation. ICRA 1989: 757-762 - 1988
- [j11]Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi:
A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. Computer 21(4): 43-56 (1988) - [j10]Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, Haruyasu Yamada:
A 32*32-bit multiplier using multiple-valued MOS current-mode circuits. IEEE J. Solid State Circuits 23(1): 124-132 (1988) - [j9]Xi Yue Huang, Michitaka Kameyama, Tatsuo Higuchi:
Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation. Syst. Comput. Jpn. 19(2): 64-73 (1988) - [j8]Michitaka Kameyama, Li Zheng, Tatsuo Higuchi:
Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System. Syst. Comput. Jpn. 19(12): 81-91 (1988) - 1987
- [j7]Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi:
Design and implementation of an nmos image processor based on quaternary logic. Syst. Comput. Jpn. 18(3): 92-106 (1987) - [j6]Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi:
Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic. Syst. Comput. Jpn. 18(4): 41-52 (1987) - [j5]Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi:
Design of micropower CMOS quaternary memory circuits. Syst. Comput. Jpn. 18(11): 61-69 (1987) - 1986
- [j4]Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi:
Design of low-power quaternary CMOS logic circuits. Syst. Comput. Jpn. 17(3): 93-101 (1986) - [j3]Nobuhiro Tomabechi, Michitaka Kameyama, Tatsuo Higuchi:
Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits. Syst. Comput. Jpn. 17(6): 76-84 (1986)
1970 – 1979
- 1977
- [j2]Tatsuo Higuchi, Michitaka Kameyama:
Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. IEEE Trans. Computers 26(12): 1212-1221 (1977) - [j1]Michitaka Kameyama, Tatsuo Higuchi:
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module. IEEE Trans. Computers 26(12): 1297-1302 (1977)
Coauthor Index
[j113] [j111] [j107] [c91] [j102] [j101] [j99] [c86] [j98] [j97] [j96] [c80] [c79] [j92] [j91] [j88] [j87] [c75] [j85] [j82] [j81] [c70] [c69] [c68] [j80] [j79] [c65] [c64] [c63] [c62] [c61] [j78] [j77] [j76] [j74] [j73] [c58] [c57] [c56] [j69] [j68] [c52] [c51] [c50] [c47] [c46] [j67] [j66] [j65] [j61] [c45] [c41] [c38] [c37] [c32] [c31] [j57] [j55] [j54] [j53] [c22] [j49] [j44] [j32]
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