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ORCIDNobuhiro Tomabechi
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2000 – 2009
- 2009
[c6]Nobuhiro Tomabechi, Yoshichika Fujioka:
Traveling-salesman game with multiple competitors/cooperators and simultaneous move search algorithm. ICE-GIC 2009: 223-230- 2005
- [c5]Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi:
VLSI architecture based on packet data transfer scheme and its application. ISCAS (2) 2005: 1786-1789 - 2002
- [j10]Nobuhiro Tomabechi, Teruki Ito:
Design of a high-speed RSA encryption processor based on the residue table for redundant binary numbers. Syst. Comput. Jpn. 33(5): 1-10 (2002) - 2001
- [c4]Nobuhiro Tomabechi, Teruki Ito:
Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers. ICECS 2001: 267-271 - 2000
- [j9]Yoshichika Fujioka, Nobuhiro Tomabechi:
Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units. Syst. Comput. Jpn. 31(12): 33-42 (2000) - [c3]Nobuhiro Tomabechi, Teruki Ito:
Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers. ISCAS 2000: 697-700
1990 – 1999
- 1999
- [c2]Nobuhiro Tomabechi:
Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems. DFT 1999: 40-45 - 1998
- [j8]Shyouji Kanazawa, Nobuhiro Tomabechi:
Redundancy design of a wafer scale two-dimensional FFT processor. Syst. Comput. Jpn. 29(10): 83-91 (1998) - 1997
- [j7]Nobuhiro Tomabechi, Shyouji Kanazawa:
Redundancy design of a wafer scale and high-speed FFT processor. Syst. Comput. Jpn. 28(6): 18-29 (1997) - [j6]Nobuhiro Tomabechi:
The effect of hardware needed for redundant interconnection lines and exchangingswitches on the yield of VLSI chips with redundan. Syst. Comput. Jpn. 28(8-9): 8-16 (1997) - [j5]Nobuhiro Tomabechi:
CAI oriented algorithm for Boolean-function minimization based on the ternaryKarnaugh map. Syst. Comput. Jpn. 28(12): 1-10 (1997) - 1996
- [j4]Yoshichika Fujioka, Nobuhiro Tomabechi:
Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length. J. Robotics Mechatronics 8(6): 524-530 (1996) - [j3]Nobuhiro Tomabechi:
WSI oriented design for highly reliable systems based on the residue number system. Syst. Comput. Jpn. 27(8): 19-28 (1996) - 1991
- [j2]Nobuhiro Tomabechi:
A defect recovery method for ulsi/ wsi arithmetic operation systems based on residue number systems. Syst. Comput. Jpn. 22(5): 13-20 (1991)
1980 – 1989
- 1989
- [c1]Nobuhiro Tomabechi:
Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems. ICCD 1989: 362-365 - 1986
- [j1]Nobuhiro Tomabechi, Michitaka Kameyama, Tatsuo Higuchi:
Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits. Syst. Comput. Jpn. 17(6): 76-84 (1986)
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