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ORCIDKunio Uchiyama
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2020 – today
- 2024
[c10]Atsushi Hasegawa, Makoto Ikeda, Ichiro Naka, Kunio Uchiyama:
SoC Platform for Heterogeneous Accelerator IPs SoC development platform for evaluation and demonstration. ISOCC 2024: 191-192- 2021
- [j14]Hiroshi Fuketa, Kunio Uchiyama:
Edge Artificial Intelligence Chips for the Cyberphysical Systems Era. Computer 54(1): 84-88 (2021)
2010 – 2019
- 2019
- [j13]Yoshihiro Shiroishi
, Kunio Uchiyama, Norihiro Suzuki:
Better Actions for Society 5.0: Using AI for Evidence-Based Policy Making That Keeps Humans in the Loop. Computer 52(11): 73-78 (2019) - 2018
- [j12]Yoshihiro Shiroishi, Kunio Uchiyama, Norihiro Suzuki:
Society 5.0: For Human Security and Well-Being. Computer 51(7): 91-95 (2018) - 2012
- [j11]Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama:
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Trans. Electron. 95-C(12): 1872-1882 (2012) - 2011
- [j10]Kunio Uchiyama:
Foreword. IEICE Trans. Electron. 94-C(4): 385 (2011) - 2010
- [j9]Kunio Uchiyama:
Foreword. IEICE Trans. Electron. 93-C(3): 215 (2010) - [c9]Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101
2000 – 2009
- 2009
- [j8]Kunio Uchiyama:
Foreword. IEICE Trans. Electron. 92-C(10): 1231 (2009) - 2008
- [j7]Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. IEEE J. Solid State Circuits 43(4): 902-910 (2008) - [c8]Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Software-cooperative power-efficient heterogeneous multi-core for media processing. ASP-DAC 2008: 736-741 - [c7]Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara:
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ISSCC 2008: 90-91 - 2007
- [c6]Kunio Uchiyama:
Power-Efficient Heterogeneous Multicore Technology for Digital Convergence. Asia-Pacific Computer Systems Architecture Conference 2007: 2-3 - [c5]Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara:
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. ISSCC 2007: 100-590 - 2005
- [j6]Kunio Uchiyama, Pradip Bose:
Guest Editors' Introduction: Energy-Efficient Design. IEEE Micro 25(5): 6-9 (2005) - [j5]Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai:
Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Syst. Comput. Jpn. 36(6): 39-48 (2005) - 2000
- [j4]Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama:
SH-5: The 64-Bit SuperH Architecture. IEEE Micro 20(4): 28-39 (2000)
1990 – 1999
- 1999
- [j3]Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama:
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. IEEE J. Solid State Circuits 34(11): 1492-1500 (1999) - 1998
- [j2]Fumio Arakawa, Osamu Nishii, Kunio Uchiyama, Norio Nakagawa:
SH4 RISC multimedia microprocessor. IEEE Micro 18(2): 26-34 (1998) - [c4]Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura:
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. DAC 1998: 246-249 - 1997
- [c3]Prasenjit Biswas, Andy Freeman, Kouji Yamada, Norio Nakagawa, Kunio Uchiyama:
Functional verification of the superscalar SH-4 microprocessor. COMPCON 1997: 115-120 - 1994
- [c2]Tetsuhiko Okada, Susumu Narita, Osamu Nishii, Noriharu Hiratsuka, Nobuyuki Hayashi, Mitsuo Asai, Shinji Fujiwara, Mikiko Satoh, Junichi Nishimoto, Hirokazu Aoki, Kunio Uchiyama, Shigeru Matsuo, Hidehito Takewa, Kouji Yamada, Masahiro Kainaga, Norio Nakagawa, Masanobu Yamagami, Hiroshi Takeda, Tsuneo Funabashi:
A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems. COMPCON 1994: 47-52 - 1993
- [j1]Kunio Uchiyama, Fumio Arakawa, Susumu Narita, Hirokazu Aoki, Ikuya Kawasaki, Shigezumi Matsui, Mitsuyoshi Yamamoto, Norio Nakagawa, Ikuo Kudo:
The Gmicro/500 superscalar microprocessor with branch buffers. IEEE Micro 13(5): 12-22 (1993) - [c1]Susumu Narita, Fumio Arakawa, Kunio Uchiyama, Ikuya Kawasaki:
Design Methodology for GMICROTM/500 TRON Microprocessor. ICCD 1993: 253-257
Coauthor Index
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