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ORCIDIEEE Journal of Solid-State Circuits, Volume 43
Volume 43, Number 1, January 2008
- David Money Harris, Sreedhar Natarajan, Ram K. Krishnamurthy, Siva G. Narendra:
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference. 3-5 - Umesh Gajanan Nawathe, Mahmudul Hassan, King C. Yen, Ashok Kumar, Aparna Ramachandran, David Greenhill:
Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip. 6-20 - Benjamin Stolt, Yonatan Mittlefehldt, Sanjay Dubey, Gaurav Mittal, Mike Lee, Joshua Friedrich, Eric Fluhr:
Design and Implementation of the POWER6 Microprocessor. 21-28 - Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Vasant Hoskote, Nitin Borkar, Shekhar Borkar:
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. 29-41 - José A. Tierno, Alexander V. Rylyakov, Daniel J. Friedman:
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. 42-51 - Ron Ho, Tarik Ono, Robert David Hopkins, Alex Chow, Justin Schauer, Frankie Y. Liu, Robert J. Drost:
High Speed and Low Energy Capacitively Driven On-Chip Wires. 52-60 - Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Vivek De, Tanay Karnik, Greg Taylor:
A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. 61-68 - Ying Su, Jeremy Holleman, Brian P. Otis:
A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations. 69-77 - Carlos Tokunaga
, David T. Blaauw, Trevor N. Mudge:
True Random Number Generator With a Metastability-Based Quality Control. 78-85 - John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. 86-95 - Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. 96-108 - Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno:
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. 109-120 - Seung-Jun Bae, Kwang-Il Park, Jeong-Don Ihm, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Yoon-Sik Park, Min-Sang Park, Hong-Kyong Lee, Sam-Young Bang, Gil-Shin Moon, Seokwon Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim, Ji-Hoon Lim, Jae-Sung Kim, Sunghoon Kim, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim, Soo-In Cho:
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. 121-131 - Corrado Villa, Daniele Vimercati, Stefan Schippers, Salvatore Polizzi, Andrea Scavuzzo, Maurizio Perroni, Maurizio Gaibotti, Mauro Luigi Sali:
A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface. 132-140 - Naveen Verma, Anantha P. Chandrakasan:
A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy. 141-149 - KwangJin Lee, Beak-Hyung Cho, Woo-Yeong Cho, Sangbeom Kang, Byung-Gil Choi, Hyung-Rok Oh, Changsoo Lee, Hye-Jin Kim, Joon-min Park, Qi Wang, Mu-Hui Park, Yu-Hwan Ro, Joon-Yong Choi, Ki-Sung Kim, Young-Ran Kim, In-Cheol Shin, Ki-won Lim, Ho-Keun Cho, ChangHan Choi, Won-ryul Chung, Du-Eung Kim, Yong-Jin Yoon, Kwang-Suk Yu, Gi-Tae Jeong, Hong-Sik Jeong, Choong-Keun Kwak, Chang-Hyun Kim, Kinam Kim:
A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput. 150-162 - Juergen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel:
Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V. 163-171 - Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr:
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. 172-179 - Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara:
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. 180-191 - Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Bart Vermeulen, Marc J. M. Heijligers:
Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis. 192-201 - Brucek Khailany, Ted Williams, Jim Lin, Eileen Peters Long, Mark Rygh, DeForest Tovey, William J. Dally:
A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing. 202-213 - Mark A. Anders, Sanu K. Mathew, Steven Hsu, Ram K. Krishnamurthy, Shekhar Borkar:
A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. 214-222 - Didier Lattard, Edith Beigné, Fabien Clermidy, Yves Durand, Romain Lemaire, Pascal Vivet, Friedbert Berens:
A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. 223-235 - Markus Hammes, Christian Kranz, Dietolf Seippel, Jens Kissing, Andreas Leyk:
Evolution on SoC Integration: GSM Baseband-Radio in 0.13 µm CMOS Extended by Fully Integrated Power Management Unit. 236-245 - Hélène Lhermet, Cyril Condemine, Marc Plissonnier, Raphael Salot, Patrick Audebert, Marion Rosset:
Efficient Power Management Circuit: From Thermal Energy Harvesting to Above-IC Microbattery Energy Storage. 246-255 - Yogesh K. Ramadass, Anantha P. Chandrakasan:
Minimum Energy Tracking Loop With Embedded DC-DC Converter Enabling Ultra-Low-Voltage Operation Down to 250 mV in 65 nm CMOS. 256-265 - Sunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, Hoi-Jun Yoo:
A Fully Integrated Digital Hearing Aid Chip With Human Factors Considerations. 266-274 - Alberto Fazzi, Roberto Canegallo, Luca Ciccarelli, Luca Magagni, Federico Natali, Erik Jung, Pier Luigi Rolandi, Roberto Guerrieri:
3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities. 275-284 - Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. 285-291 - Yoshiyuki Kurokawa, Takayuki Ikeda, Masami Endo, Hiroki Dembo, Daisuke Kawae, Takayuki Inoue, Munehiro Kozuma, Daisuke Ohgarane, Satoru Saito, Koji Dairiki, Hidekazu Takahashi, Yutaka Shionoiri, Tomoaki Atsumi, Takeshi Osada, Kei Takahashi, Takanori Matsuzaki, Hiroyuki Takashina, Yoshinari Yamashita, Shunpei Yamazaki:
UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems. 292-299 - Shailesh Rai, Brian P. Otis:
A 600 µW BAW-Tuned Quadrature VCO Using Source Degenerated Coupling. 300-305
Volume 43, Number 2, February 2008
- Bram Nauta:
New Associate Editor. 311 - Luca Picolli, Andrea Rossini, Piero Malcovati, Franco Maloberti, Fausto Borghetti, Andrea Baschirotto:
A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors. 312-320 - Jian Li, Xiaoyang Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo:
A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications. 321-329 - Tongyu Song, Zhiheng Cao, Shouli Yan:
A 2.7-mW 2-MHz Continuous-Time ΣΔ Modulator With a Hybrid Active-Passive Loop Filter. 330-341 - Yun-Shiang Shu, Bang-Sup Song:
A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering. 342-350 - Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar:
A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications. 351-360 - Jeongjin Roh, San-Ho Byun, Youngkil Choi, Hyungdong Roh, Yi-Gyeong Kim, Jong-Kee Kwon:
A 0.9-V 60-µW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range. 361-370 - Chih-Wen Lu, Lung-Chien Huang:
A 10-Bit LCD Column Driver With Piecewise Linear Digital-to-Analog Converters. 371-378 - Kyoungho Woo, Yong Liu, Eunsoo Nam, Donhee Ham:
Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Differing Bandwidths. 379-389 - Che-Fu Liang, Shin-Hua Chen, Shen-Iuan Liu:
A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems. 390-398 - Kuo-Hsing Cheng, Chia-Wei Su, Kai-Fei Chang:
A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation. 399-413 - Pavan Kumar Hanumolu, Volodymyr Kratyuk, Gu-Yeon Wei, Un-Ku Moon:
A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter. 414-424 - Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon:
A Wide-Tracking Range Clock and Data Recovery Circuit. 425-439 - Jun-De Jin, Shawn S. H. Hsu:
A 0.18-µm CMOS Balanced Amplifier for 24-GHz Applications. 440-445 - Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
A Low-Power SRAM Using Bit-Line Charge-Recycling. 446-459 - Willem Laflere, Michiel S. J. Steyaert, Jan Craninckx:
A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer. 460-467 - Russell A. Hershbarger, Wenyan Jia, Kiam M. Tey, Kiyoshi Fukahori, Paul J. Hurst, Manprit Kapoor:
A Programmable Impedance Matching Circuit for Voiceband Modems. 468-476 - Behzad Razavi:
A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider. 477-485 - Sven Mattisson, Hans Hagberg, Pietro Andreani:
Sensitivity Degradation in a Tri-Band GSM BiCMOS Direct-Conversion Receiver Caused by Transient Substrate Heating. 486-496 - Yukinori Akamine, Manabu Kawabe, Kazuyuki Hori, Takao Okazaki, Masumi Kasahara, Satoshi Tanaka:
ΔΣ PLL Transmitter With a Loop-Bandwidth Calibration System. 497-506 - Yong Hoon Kang, Jin-Kook Kim, Sang Won Hwang, Joon Young Kwak, Jun-Yong Park, Daeyong Kim, Chan Ho Kim, Jong-Yeol Park, Yong-Taek Jeong, Jong Nam Baek, Su Chang Jeon, Pyungmoon Jang, Sang Hoon Lee, You-Sang Lee, Min-Seok Kim, Jin-Yub Lee, Yun Ho Choi:
High-Voltage Analog System for a Mobile NAND Flash. 507-517 - Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim:
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing. 518-529 - Chao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh:
High-Speed and Low-Power Design Techniques for TCAM Macros. 530-540 - Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu:
A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology. 541-549 - Jun Zhou, David Kinniment, Charles E. Dike, Gordon Russell, Alexandre Yakovlev:
On-Chip Measurement of Deep Metastability in Synchronizers. 550-557 - Guillermo J. Serrano, Paul E. Hasler:
A Precision Low-TC Wide-Range CMOS Current Reference. 558-565 - Patrick Lichtsteiner, Christoph Posch, Tobi Delbrück:
A 128×128 120 dB 15 µs Latency Asynchronous Temporal Contrast Vision Sensor. 566-576
Volume 43, Number 3, March 2008
- Bram Nauta:
New Associate Editor. 578 - Jarkko Jussila, Pete Sivonen:
A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-µm CMOS. 579-587 - Xiaohua Fan, Heng Zhang, Edgar Sánchez-Sinencio:
A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA. 588-599 - Gang Liu, Peter Haldi, Tsu-Jae King Liu, Ali M. Niknejad:
Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off. 600-609 - Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda:
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. 610-618 - Jri Lee, Mingchung Liu:
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique. 619-630 - Feng Lin, Roman A. Royer, Brian Johnson, Brent Keeth:
A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM. 631-641 - Chih-Fan Liao, Shen-Iuan Liu:
40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS. 642-655 - Ahmad Mirzaei, Mohammad E. Heidari, Rahim Bagheri, Asad A. Abidi:
Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers. 656-671 - Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu:
An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process. 672-683 - Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. 684-694 - Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Dean Truong, Tinoosh Mohsenin, Bevan M. Baas:
AsAP: An Asynchronous Array of Simple Processors. 695-705 - Jérôme Dubois, Dominique Ginhac, Michel Paindavoine, Barthélémy Heyrman:
A 10 000 fps CMOS Sensor With Massively Parallel Image Processing. 706-717 - Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects. 718-728 - Ickjin Kwon, Yunseong Eo, Heemun Bang, Kyudon Choi, Sangyoon Jeon, Sungjae Jung, Donghyun Lee, Heungbae Lee:
A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader. 729-738
Volume 43, Number 4, April 2008
- Kazuo Yano, Katsu Nakamura:
Introduction to the Special Issue on the 2007 Symposium on VLSI Circuits. 755-756 - Mark Horowitz, Don Stark, Elad Alon:
Digital Circuit Design Trends. 757-761 - Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi:
Memory at VLSI Circuits Symposium. 762-768 - Minjae Lee, Asad A. Abidi:
A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue. 769-777 - Simon M. Louwsma, A. J. M. van Tuijl, Maarten Vertregt, Bram Nauta:
A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. 778-786 - Junhua Shen, Peter R. Kinget:
A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS. 787-795 - Scott D. Kulchycki, Roxana Trofin, Katelijn Vleugels, Bruce A. Wooley:
A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator. 796-804 - Matthew Z. Straayer, Michael H. Perrott:
A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer. 805-814 - Feng Su, Wing-Hung Ki, Chi-Ying Tsui:
Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications. 815-822 - Satoru Adachi, Woonghee Lee, Nana Akahane, Hiromichi Oshikubo, Koichi Mizobuchi, Shigetoshi Sugawa:
A 200-µV/e- CMOS Image Sensor With 100-ke- Full Well Capacity. 823-830 - Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho:
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System. 831-843 - Josh Wibben, Ramesh Harjani:
A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors. 844-854 - Belal Helal, Matthew Z. Straayer, Gu-Yeon Wei, Michael H. Perrott:
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance. 855-863 - Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou:
Resonant-Clock Latch-Based Design. 864-873 - Tony Tae-Hyoung Kim, Randy Persaud, Chris H. Kim:
Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits. 874-880 - Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd M. Austin, Dennis Sylvester, David T. Blaauw:
Exploring Variability and Performance in a Sub-200-mV Processor. 881-891 - Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto:
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. 892-901 - Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. 902-910 - Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara:
A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations. 911-918 - Ki-Tae Park, Myounggon Kang, Doogon Kim, Soonwook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, Kinam Kim:
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories. 919-928 - Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, Kiyoaki Iwasa, Michio Nakagawa, Masaki Fujiu, Takahiro Shimizu, Mitsuaki Honma, Satoru Hoshi, Toshimasa Kawaai, Kazunori Kanebako, Susumu Yoshikawa, Hideyuki Tabata, Atsushi Inoue, Toshiyuki Takahashi, Toshifumi Shano, Yukio Komatsu, Katsushi Nagaba, Mitsuhiko Kosakai, Noriaki Motohashi, Kazuhisa Kanazawa, Kenichi Imamiya, Hiroto Nakai, Menahem Lasser, Mark Murin, Avraham Meir, Arik Eyal, Mark Shlick:
A 70 nm 16 Gb 16-Level-Cell NAND flash Memory. 929-937 - Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu:
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. 938-945 - Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler:
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. 946-955 - Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek:
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches. 956-963 - Tatsuo Nakagawa, Goichi Ono, Ryosuke Fujiwara, Takayasu Norimatsu, Takahide Terada, Masayuki Miyazaki, Kei Suzuki, Kazuo Yano, Yuji Ogata, Akira Maeki, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura:
1-cc Computer: Cross-Layer Integration With UWB-IR Communication and Locationing. 964-973 - Ali Medi, Won Namgoong:
A High Data-Rate Energy-Efficient Interference-Tolerant Fully Integrated CMOS Frequency Channelized UWB Transceiver for Impulse Radio. 974-980 - Peter H. R. Popplewell, Victor Karam, Atif Shamim, John W. M. Rogers, Langis Roy, Calvin Plett:
A 5.2-GHz BFSK Transceiver Using Injection-Locking and an On-Chip Antenna. 981-990 - Qun Gu, Zhiwei Xu, Daquan Huang, Tim R. LaRocca, Ning-Yi Wang, William Hant, Mau-Chung Frank Chang:
A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases. 991-998 - Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz:
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. 999-1009 - Ganesh Balamurugan, Joseph T. Kennedy, Gaurab Banerjee, James E. Jaussi, Mozhgan Mansuri, Frank O'Mahony, Bryan Casper, Randy Mooney:
A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS. 1010-1019 - Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, Kazuya Masu:
A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications. 1020-1029 - Toshiya Mitomo, Ryuichi Fujimoto, Naoko Ono, Ryoichi Tachibana, Hiroaki Hoshino, Yoshiaki Yoshihara, Yukako Tsutsumi, Ichiro Seto:
A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer. 1030-1037 - Koichi Nose, Masayuki Mizuno:
A 0.016 mm2, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis. 1038-1046
Volume 43, Number 5, May 2008
- Bram Nauta:
New Associate Editor. 1051 - Jacques Christophe Rudell:
Overview for the Special Section on the 2007 Radio Frequency Integrated Circuits Symposium. 1052-1053 - Peter Haldi, Debopriyo Chowdhury, Patrick Reynaert, Gang Liu, Ali M. Niknejad:
A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS. 1054-1063 - Kyu Hwan An, Ockgoo Lee, Hyungwook Kim, Dong Ho Lee, Jeonghu Han, Ki Seok Yang, Younsuk Kim, Jaejoon Chang, Wangmyong Woo, Chang-Ho Lee, Haksun Kim, Joy Laskar:
Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers. 1064-1075 - Brian A. Floyd:
A 16-18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers. 1076-1086 - Ekaterina Laskin, Pascal Chevalier, Alain Chantre, Bernard Sautreuil, Sorin P. Voinigescu:
165-GHz Transceiver in SiGe Technology. 1087-1100 - Ali Afsahi, Jacob J. Rael, Arya Behzad, Hung-Ming Chien, Michael Pan, Stephen Au, Adedayo Ojo, C. Paul Lee, Seema Butala Anand, Kevin Chien, Stephen Wu, Rozi Roufoogaran, Alireza Zolfaghari, John C. Leete, Long H. Tran, Keith A. Carter, Mohammad Nariman, David W. K. Yeung, Walter Morton, Mark Gonikberg, Mukul Seth, Marcellus Forbes, Jay Pattin, Luis Gutierrez, Sumant Ranganathan, Ning Li, Eric Blecker, Jack Lin, Tom Kwan, Rose Zhu, Mark Chambers, Maryam Rofougaran, Ahmadreza Rofougaran, Jason Trachewsky, Pieter van Rooyen:
A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit. 1101-1118 - Junghwan Han, Ranjit Gharpurey:
Recursive Receiver Down-Converters With Multiband Feedback and Gain-Reuse. 1119-1131 - Jing-Hong Conan Zhan, Brent R. Carlton, Stewart S. Taylor:
A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS. 1132-1137 - Nebojsa Stanic, Ajay Balankutty, Peter R. Kinget, Yannis P. Tsividis:
A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply. 1138-1145 - Pradeep Basappa Khannur, Xuesong Chen, Dan Lei Yan, Dan Shen, Bin Zhao, M. Kumarasamy Raja, Ye Wu, Rendra Sindunata, Wooi Gan Yeoh, Rajinder Singh:
A Universal UHF RFID Reader IC in 0.18-µm CMOS Technology. 1146-1155 - Murat Demirkan, Stephen P. Bruss, Richard R. Spencer:
Design of Wide Tuning-Range CMOS VCOs Using Switched Coupled-Inductors. 1156-1163 - Wei-Hung Chen, Gang Liu, Zdravko Boos, Ali M. Niknejad:
A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation. 1164-1176 - Sudip Shekhar, Jeffrey S. Walling, Sankaran Aniruddhan, David J. Allstot:
CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits. 1177-1186 - Mikaël Cimino, Hervé Lapuyade, Yann Deval, Thierry Taris, Jean-Baptiste Bégueret:
Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA. 1187-1194 - Min-Gyu Kim, Gil-Cho Ahn, Pavan Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, Gabor C. Temes, Un-Ku Moon:
A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. 1195-1206 - Jafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp:
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications. 1207-1216 - Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu:
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector. 1217-1226 - Bob Schell, Yannis P. Tsividis:
A Low Power Tunable Delay Element Suitable for Asynchronous Delays of Burst Information. 1227-1234 - Samuel Palermo, Azita Emami-Neyestanak, Mark Horowitz:
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects. 1235-1246 - Seok-Hoon Kim, Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Kyusik Chung, Han Shin Lim, Yun-Gu Lee, HyunWook Park, Jong Beom Ra, Lee-Sup Kim:
A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine. 1247-1259 - Yuan Chen, Yu-Wei Lin, Yu-Chi Tsao, Chen-Yi Lee:
A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems. 1260-1273 - Luigi Panseri, Luca Romanò, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter. 1274-1286 - Triet Le, Kartikeya Mayaram, Terri S. Fiez:
Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks. 1287-1302 - Takamaro Kikkawa, Pran Kanai Saha, Nobuo Sasaki, Kentaro Kimoto:
Gaussian Monocycle Pulse Transmitter Using 0.18 µm CMOS Technology With On-Chip Integrated Antennas for Inter-Chip UWB Communication. 1303-1312 - Antonio J. López-Martín, Jaime Ramírez-Angulo, Ramón González Carvajal, Lucía Acosta:
CMOS Transconductors With Continuous Tuning Using FGMOS Balanced Output Current Scaling. 1313-1323 - Jeremy Holleman, Seth Bridges, Brian P. Otis, Chris Diorio:
A 3 µW CMOS True Random Number Generator With Adaptive Floating-Gate Offset Cancellation. 1324-1336
Volume 43, Number 6, June 2008
- Bram Nauta, Willy Sansen:
Retraction of Papers With Falsified Information. 1339 - Bram Nauta:
New Associate Editor. 1340 - Stephan C. Blaakmeer, Eric A. M. Klumperink, Domine M. W. Leenaerts, Bram Nauta:
Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling. 1341-1350 - Brad R. Jackson, Carlos E. Saavedra:
A CMOS Ku-Band 4x Subharmonic Mixer. 1351-1359 - Kwang-Jin Koh, Gabriel M. Rebeiz:
An X- and Ku-Band 8-Element Phased-Array Receiver in 0.18-µm SiGe BiCMOS Technology. 1360-1371 - Manuel Camus, Benoit Butaye, Luc Garcia, Mathilde Sié, Bruno Pellat, Thierry Parra:
A 5.4 mW/0.07 mm2 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard. 1372-1383 - Xuefeng Yu, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 µm SiGe BiCMOS Technology. 1384-1393 - Changhua Cao, Yanping Ding, Xiuge Yang, Jau-Jr Lin, Hsin-Ta Wu, Ashok K. Verma, Jenshan Lin, Frédérick Martin, Kenneth K. O:
A 24-GHz Transmitter With On-Chip Dipole Antenna in 0.13-µm CMOS. 1394-1402 - Andrea Bonfanti, Davide De Caro, Alfio Dario Grasso, Salvatore Pennisi, Carlo Samori, Antonio G. M. Strollo:
A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS. 1403-1413 - Jri Lee, Mingchung Liu, Huaide Wang:
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology. 1414-1426 - Keng-Jan Hsiao, Tai-Cheng Lee:
The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning. 1427-1435 - Friedel Gerfers, Gerrit W. den Besten, Pavel V. Petkov, Jim E. Conder, Andreas J. Koellmann:
A 0.2-2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer. 1436-1448 - Jun-De Jin, Shawn S. H. Hsu:
A 40-Gb/s Transimpedance Amplifier in 0.18-µm CMOS Technology. 1449-1457 - Doug Garrity, David LoCascio, Christopher Cavanagh, M. Nizam Kabir, Chris Guenther:
A Single Analog-to-Digital Converter That Converts Two Separate Channels (I and Q) in a Broadband Radio Receiver. 1458-1469 - Wei Miao, Qingyu Lin, Wancheng Zhang, Nan-Jian Wu:
A Programmable SIMD Vision Chip for Real-Time Vision Applications. 1470-1479 - Lin He, Yong Ping Xu, Moorthi Palaniapan:
A CMOS Readout Circuit for SOI Resonant Accelerometer With 4-µg Bias Stability and 20-µg/√Hz Resolution. 1480-1490 - Gary J. Ballantyne:
Comments on "On the Self-Generation of Electrical Soliton Pulses". 1491 - David S. Ricketts, Xiaofeng Li, Nan Sun, Kyoungho Woo, Donhee Ham:
Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]. 1492-1493 - Payam Heydari:
Correction to "Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA". 1493
Volume 43, Number 7, July 2008
- Andrea Baschirotto, Edoardo Charbon, Stefan Rusu:
Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007). 1507-1510 - Alan Chi Wai Wong, Ganesh Kathiresan, Chung Kei Thomas Chan, Omar El-Jamaly, Okundu C. Omeni, Declan McDonagh, Alison J. Burdett, Christofer Toumazou:
A 1 V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications. 1511-1521 - Iason Vassiliou, Kostis Vavelidis, Nikos Haralabidis, Aris Kyranas, Yiannis Kokolakis, Stamatis Bouras, George Kamoulakos, Charalambos Kapnistis, Spyros Kavadias, Nikos Kanakaris, Emmanouil Metaxakis, Christos Kokozidis, Hamed Peyravi:
A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications. 1522-1533 - Stefano D'Amico, Andrea Baschirotto, Marcello De Matteis, Nicola Ghittori, Andrea Vigna, Piero Malcovati:
A CMOS 5 nV/√Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN. 1534-1541 - Stefano Pellerano, Yorgos Palaskas, Krishnamurthy Soumyanath:
A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS. 1542-1552 - Yanyu Jin, Mihai A. T. Sanduleanu, John R. Long:
A Wideband Millimeter-Wave Power Amplifier With 20 dB Linear Power Gain and +8 dBm Maximum Saturated Output Power. 1553-1562 - Nitz Saputra, Mina Danesh, Alessandro Baiano, Ryoichi Ishihara, John R. Long, Nobuo Karaki, Satoshi Inoue:
An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration. 1563-1576 - Noriko Ide, Woonghee Lee, Nana Akahane, Shigetoshi Sugawa:
A Wide DR and Linear Response CMOS Image Sensor With Three Photocurrent Integrations in Photodiodes, Lateral Overflow Capacitors, and Column Capacitors. 1577-1587 - Christian Koch, Jürgen Oehm, Jannik Emde, Wolfram Budde:
Light Source Position Measurement Technique Applicable in SOI Technology. 1588-1593 - Daniel Durini, Werner Brockherde, Wiebke Ulfig, Bedrich J. Hosticka:
Time-of-Flight 3-D Imaging Pixel Structures in Standard CMOS Processes. 1594-1602 - Cheng Zhang, Kofi A. A. Makinwa:
Interface Electronics for a CMOS Electrothermal Frequency-Locked-Loop. 1603-1608 - Ali Heidary, Gerard C. M. Meijer:
Features and Design Constraints for an Optimized SC Front-End Circuit for Capacitive Sensors With a Wide Dynamic Range. 1609-1616 - Michael Wendt, Lenz Thoma, Bernhard Wicht, Doris Schmitt-Landsiedel:
A Configurable High-Side/Low-Side Driver With Fast and Equalized Switching Delay. 1617-1625 - Imran Ahmed, David A. Johns:
An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage. 1626-1637 - Imran Ahmed, David A. Johns:
A High Bandwidth Power Scalable Sub-Sampling 10-Bit Pipelined ADC With Embedded Sample and Hold. 1638-1647 - Ivano Galdi, Edoardo Bonizzoni, Piero Malcovati, Gabriele Manganaro, Franco Maloberti:
40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW. 1648-1656 - YuQing Yang, Terry Sculley, Jacob Abraham:
A Single-Die 124 dB Stereo Audio Delta-Sigma ADC With 111 dB THD. 1657-1665 - Stephan Henzler, Siegmar Koeppe, Dominik Lorenz, Winfried Kamp, Ronald Kuenemund, Doris Schmitt-Landsiedel:
A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion. 1666-1676 - Marian Verhelst, Wim Dehaene:
A Flexible, Ultra-Low-Energy 35 pJ/Pulse Digital Back-End for a QAC IR-UWB Receiver. 1677-1687 - Alexandre Valentian, Edith Beigné:
Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability. 1688-1698 - Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric A. Vittoz:
Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. 1699-1710
Volume 43, Number 8, August 2008
- Lawrence T. Clark, Ranjit Gharpurey, Payam Heydari:
Introduction to the Special Issue on the IEEE 2007 Custom Integrated Circuits Conference. 1714-1716 - Mehdi Khanpour, Keith W. Tang, Patrice Garcia, Sorin P. Voinigescu:
A Wideband W-Band Receiver Front-End in 65-nm CMOS. 1717-1730 - Matthias Locher, Jeroen Kuenen, Anton Daanen, Henk Visser, Berend Hendrik Essink, Peter Paul Vervoort, Rob Kopmeiners, Wilfred Alkema, William Redman-White, Richard A. H. Balmford, Rachid El Waffaoui:
A Versatile, Low Power, High Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC for WiBro/WiMAX (802.16e). 1731-1740 - Wenting Wang, Shuzuo Lou, Kay W. C. Chui, Sujiang Rong, Chi Fung Lok, Hui Zheng, Hin-Tat Chan, Sau-Wing Man, Howard C. Luong, Vincent K. N. Lau, Chi-Ying Tsui:
A Single-Chip UHF RFID Reader in 0.18 µm CMOS Process. 1741-1754 - Riccardo Brama, Luca Larcher, Andrea Mazzanti, Francesco Svelto:
A 30.5 dBm 48% PAE CMOS Class-E PA With Integrated Balun for RF Applications. 1755-1762 - Sander L. J. Gierkink:
A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator. 1763-1771 - Kentaro Yamamoto, Anthony Chan Carusone, Francis P. Dawson:
A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR. 1772-1782 - Takaya Yamamoto, Masumi Kasahara, Tatsuji Matsuura:
A 63 mA 112/94 dB DR IF Bandpass ΔΣ Modulator With Direct Feed-Forward Compensation and Double Sampling. 1783-1794 - Elad Alon, Mark Horowitz:
Integrated Regulation for Energy-Efficient Digital Circuits. 1795-1807 - Raymond E. Barnett, Jin Liu:
An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control. 1808-1815 - Robert M. Houle:
Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times. 1816-1825 - Joseph J. Nahas, Thomas W. Andre, Brad Garni, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino:
A 180 Kbit Embeddable MRAM Memory Module. 1826-1834 - Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang:
Power Reduction Techniques for LDPC Decoders. 1835-1845 - Ruwan N. S. Ratnayake, Aleksandar Kavcic, Gu-Yeon Wei:
A High-Throughput Maximum a Posteriori Probability Detector. 1846-1858 - Peter M. Levine, Ping Gong, Rastislav Levicky, Kenneth L. Shepard:
Active CMOS Sensor Array for Electrochemical Biomolecular Detection. 1859-1871
Volume 43, Number 9, September 2008
- Bruce Hecht:
Introduction to the Special Issue on the 2007 Bipolar/BiCMOS Circuits and Technology Meeting. 1875-1876 - Michael Möller:
Challenges in the Cell-Based Design of Very-High-Speed SiGe-Bipolar ICs at 100 Gb/s. 1877-1888 - Jonathan P. Comeau, Matthew A. Morton, Wei-Min Lance Kuo, Tushar K. Thrivikraman, Joel M. Andrews, Curtis M. Grens, John D. Cressler, John Papapolymerou, Mark Mitchell:
A Silicon-Germanium Receiver for X-Band Transmit/Receive Radar Modules. 1889-1896 - Li Wang, Srdjan Glisic, Johannes Borngräber, Wolfgang Winkler, Christoph Scheytt:
A Single-Ended Fully Integrated SiGe 77/79 GHz Receiver for Automotive Radar. 1897-1908 - Wanghua Wu, Mihai A. T. Sanduleanu, Xia Li, John R. Long:
17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks. 1909-1919 - Winfried Bakalski, Bernhard Sogl, Markus Zannoth, Michael Asam, Boris Kapfelsperger, Jörg Berkner, Bernd Eisener, Wolfgang Thomann, Siegfried Marcon, Wilfried Osterreicher, Ewa Napieralska, Erwin Rampf, Arpad L. Scholtz, Bernd-Ulrich Klepser:
A Quad-Band GSM/EDGE-Compliant SiGe-Bipolar Power Amplifier. 1920-1930 - Moo Sung Chae, Wentai Liu, Mohanasankar Sivaprakasam:
Design Optimization for Integrated Neural Recording Systems. 1931-1939 - Robert Berger, Dennis Rathman, Brian Tyrrell, E. J. Kohler, Michael K. Rose, R. Allen Murphy, Theodore S. Perry, Harry F. Robey, Franz A. Weber, David M. Craig, Antonio M. Soares, Stephen P. Vernon, Robert K. Reich:
A 64×64-Pixel CMOS Test Chip for the Development of Large-Format Ultra-High-Speed Snapshot Imagers. 1940-1950 - Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy:
An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process. 1951-1963 - Ya-Chun Lai, Shi-Yu Huang:
X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs. 1964-1971 - Oleksiy Tyshchenko, Ali Sheikholeslami:
Match Sensing Using Match-Line Stability in Content-Addressable Memories (CAM). 1972-1981 - Ayman H. Ismail, Mohamed I. Elmasry:
A 6-Bit 1.6-GS/sLow-Power Wideband Flash ADC Converter in 0.13-µm CMOS Technology. 1982-1990 - Mikko Varonen, Mikko Kärkkäinen, Mikko Kantanen, Kari A. I. Halonen:
Millimeter-Wave Integrated Circuits in 65-nm CMOS. 1991-2002 - Mingcui Zhou, Mehmet Rasit Yuce, Wentai Liu:
A Non-Coherent DPSK Data Receiver With Interference Cancellation for Dual-Band Transcutaneous Telemetries. 2003-2012 - Supisa Lerstaveesin, Manoj Gupta, David Kang, Bang-Sup Song:
A 48-860 MHz CMOS Low-IF Direct-Conversion DTV Tuner. 2013-2024 - Shao-Yi Chien, You-Ming Tsao, Chin-Hsiang Chang, Yu-Cheng Lin:
An 8.6 mW 25 Mvertices/s 400-MFLOPS 800-MOPS 8.91 mm2 Multimedia Stream Processor Core for Mobile Applications. 2025-2035 - Tsz Yin Man, Philip K. T. Mok, Mansun Chan:
A 0.9-V Input Discontinuous-Conduction-Mode Boost Converter With CMOS-Control Rectifier. 2036-2046 - Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Hoi-Jun Yoo:
A 195 mW/152 mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG. 2047-2056 - Francesco Carrara, Calogero D. Presti, Antonino Scuderi, Carmelo Santagati, Giuseppe Palmisano:
A Methodology for Fast VSWR Protection Implemented in a Monolithic 3-W 55% PAE RF CMOS Power Amplifier. 2057-2066 - Kok Lim Chan, Jianyu Zhu, Ian Galton:
Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs. 2067-2078 - Zhiheng Cao, Yunchu Li, Shouli Yan:
A 0.4 ps-RMS-Jitter 1-3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification. 2079-2089 - Behzad Razavi:
A Millimeter-Wave Circuit Technique. 2090-2098 - Anand Rao, Makram Mansour, Guneet Singh, Chee-How Lim, Rizwan Ahmed, David R. Johnson:
A 4-6.4 GHz LC PLL With Adaptive Bandwidth Control for a Forwarded Clock Link. 2099-2108 - Toshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu:
A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. 2109-2119 - Jri Lee, Ming-Shuan Chen, Huaide Wang:
Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data. 2120-2133 - Tiku Yu, Gabriel M. Rebeiz:
A 22-24 GHz4-Element CMOS Phased Array With On-Chip Coupling Characterization. 2134-2143 - E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Hae-Chang Lee, Qi Lin, Kyung Suk Oh, Frank Lambrecht, Vladimir Stojanovic, Jared Zerbe, Chih-Kong Ken Yang:
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric. 2144-2156 - Jackie Koon Lun Wong, E-Hung Chen, Chih-Kong Ken Yang:
Edge and Data Adaptive Equalization of Serial-Link Transceivers. 2157-2169 - Lei Lu, Zhangwen Tang, Pietro Andreani, Andrea Mazzanti, Ali Hajimiri:
Comments on "Comments on "A General Theory of Phase Noise in Electrical Oscillators"". 2170 - Lei Lu, Zhangwen Tang, Pietro Andreani, Andrea Mazzanti, Ali Hajimiri:
Author's Response. 2170
Volume 43, Number 10, October 2008
- Mounir Meghelli, Robert Shimon:
Introduction to the Special Section on the 2008 Compound Semiconductor Integrated Circuit Symposium (CSICS'08). 2175-2176 - Ricardo Andres Aroca, Sorin P. Voinigescu:
A Large Swing, 40-Gb/s SiGe BiCMOS Driver With Adjustable Pre-Emphasis for Data Transmission Over 75Ω Coaxial Cable. 2177-2186 - Beckie Chan, Bert K. Oyama, Cedric Monier, Augusto Gutierrez-Aitken:
An Ultra-Wideband 7-Bit 5-Gsps ADC Implemented in Submicron InP HBT Technology. 2187-2193 - Axel Tessmann, Ingmar Kallfass, Arnulf Leuther, Hermann Massler, Michael Kuri, Markus Riessle, Martin Zink, Rainer Sommer, Alfred Wahlen, Helmut Essen, Volker Hurm, Michael Schlechtweg, Oliver Ambacher:
Metamorphic HEMT MMICs and Modules for Use in a High-Bandwidth 210 GHz Radar. 2194-2205 - Sean T. Nicolson, Pascal Chevalier, Bernard Sautreuil, Sorin P. Voinigescu:
Single-Chip W-band SiGe HBT Transceivers and Receivers for Doppler Radar and Millimeter-Wave Imaging. 2206-2217 - Craig Steinbeiser, Thomas Landon, Charles Suckling, James Nelson, Joe Delaney, John Hitt, Larry Witkowski, Gary Burgin, Rached Hajji, Oleh Krutko:
250 W HVHBT Doherty With 57% WCDMA Efficiency Linearized to -55 dBc for 2c11 6.5 dB PAR. 2218-2228 - Bevin George Perumana, Rajarshi Mukhopadhyay, Sudipto Chakraborty, Chang-Ho Lee, Joy Laskar:
A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications. 2229-2238 - Byung-Wook Min, Gabriel M. Rebeiz:
Single-Ended and Differential Ka-Band BiCMOS Phased Array Front-Ends. 2239-2250 - Amirpouya Kavousian, David K. Su, Mohammad Hekmat, Alireza Shirvani, Bruce A. Wooley:
A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth. 2251-2258 - André van Bezooijen, Maurice A. de Jongh, Christophe Chanlo, Lennart C. H. Ruijs, Freek van Straten, Reza Mahmoudi, Arthur H. M. van Roermund:
A GSM/EDGE/WCDMA Adaptive Series-LC Matching Network Using RF-MEMS Switches. 2259-2268 - Hakan Dogan, Robert G. Meyer, Ali M. Niknejad:
Analysis and Design of RF CMOS Attenuators. 2269-2283 - Duho Kim, Kwang-Chun Choi, Young-Kwang Seo, Hyunchin Kim, Woo-Young Choi:
A 622-Mb/s Mixed-Mode BPSK Demodulator Using a Half-Rate Bang-Bang Phase Detector. 2284-2292 - Hui Zheng, Howard C. Luong:
Ultra-Low-Voltage 20-GHz Frequency Dividers Using Transformer Feedback in 0.18-µm CMOS Process. 2293-2302 - Kazuaki Deguchi, Naoko Suwa, Masao Ito, Toshio Kumamoto, Takahiro Miki:
A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS. 2303-2310 - Philip A. Godoy, Joel L. Dawson:
Chopper Stabilization of Analog Multipliers, Variable Gain Amplifiers, and Mixers. 2311-2321 - Luke Theogarajan:
A Low-Power Fully Implantable 15-Channel Retinal Stimulator Chip. 2322-2337 - Bo Zhai, Scott Hanson, David T. Blaauw, Dennis Sylvester:
A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM. 2338-2348
Volume 43, Number 11, November 2008
- Bram Nauta:
New Associate Editor. 2351 - Nicky Lu, Shyh-Jye Jou:
Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07). 2352-2353 - Seiji Mochizuki, Tetsuya Shibayama, Masaru Hase, Fumitaka Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, Hiroshi Ueda, Kazuyuki Ishikawa, Hiromi Watanabe:
A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS. 2354-2362 - Yoichi Yoshida, Noriyuki Miura, Tadahiro Kuroda:
A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array. 2363-2369 - Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Hoi-Jun Yoo:
A 195 mW, 9.1 MVertices/s Fully Programmable 3-D Graphics Processor for Low-Power Mobile Devices. 2370-2380 - Jung-Sik Kim, Kyung-Woo Nam, Chi Sung Oh, Han Gu Sohn, Donghyuk Lee, Sooyoung Kim, Jong-Wook Park, Yongjun Kim, Mi-Jo Kim, Jin-Guk Kim, Hocheol Lee, Jinhyoung Kwon, Dong Il Seo, Young-Hyun Jun, Kinam Kim:
A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array. 2381-2389 - David Levacq, Makoto Takamiya, Takayasu Sakurai:
Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time. 2390-2395 - Xu Wu, Pieter Palmers, Michiel S. J. Steyaert:
A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC. 2396-2403 - Shuzuo Lou, Howard C. Luong:
A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection. 2404-2412 - Chao-Chyun Chen, Shen-Iuan Liu:
An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line. 2413-2421 - Jonathan Borremans, Piet Wambacq, Charlotte Soens, Yves Rolain, Maarten Kuijk:
Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS. 2422-2433 - Krzysztof Dufrene, Zdravko Boos, Robert Weigel:
Digital Adaptive IIP2 Calibration Scheme for CMOS Downconversion Mixers. 2434-2445 - Harish Krishnaswamy, Hossein Hashemi:
A Variable-Phase Ring Oscillator and PLL Architecture for Integrated Phased Array Transceivers. 2446-2463 - Mark A. Ferriss, Michael P. Flynn:
A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme. 2464-2471 - Bob Schell, Yannis P. Tsividis:
A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation. 2472-2481 - David Hernandez-Garduno, José Silva-Martínez:
A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer. 2482-2491 - Chih-Fan Liao, Shen-Iuan Liu:
A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery. 2492-2502 - Antonio Giuseppe Maria Strollo, Davide De Caro, Nicola Petra:
A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 µm CMOS. 2503-2513 - Jiajing Wang, Benton H. Calhoun:
Techniques to Extend Canary-Based Standby VDD Scaling for SRAMs to 45 nm and Beyond. 2514-2523 - Giby Samson, Nagaraj Ananthapadmanabhan, Sayeed A. Badrudduza, Lawrence T. Clark:
Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories. 2524-2532 - Ming-Dou Ker, Cheng-Cheng Yen:
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test. 2533-2545 - David E. Schwartz, Edoardo Charbon, Kenneth L. Shepard:
A Single-Photon Avalanche Diode Array for Fluorescence Lifetime Imaging Microscopy. 2546-2557 - Seong-Jin Kim, Kwang-Hyun Lee, Sang-Wook Han, Euisik Yoon:
A CMOS Fingerprint System-on-a-Chip With Adaptable Pixel Networks and Column-Parallel Processors for Image Enhancement and Recognition. 2558-2567
Volume 43, Number 12, December 2008
- Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee:
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. 2587-2591 - Khiem Nguyen, Abhishek Bandyopadhyay, Bob Adams, Karl Sweetland, Paul Baginski:
A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique. 2592-2600 - Kyehyung Lee, Jeongseok Chae, Mitsuru Aniya, Koichi Hamashita, Kaoru Takasuka, Seiji Takeuchi, Gabor C. Temes:
A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR. 2601-2612 - Byung Geun Lee, Byung-Moo Min, Gabriele Manganaro, Jonathan W. Valvano:
A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC. 2613-2619 - B. Robert Gregoire, Un-Ku Moon:
An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain. 2620-2630 - Geert Van der Plas, Bob Verbruggen:
A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS. 2631-2640 - Brian P. Ginsburg, Anantha P. Chandrakasan:
Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS. 2641-2650 - Karen Scheir, Stephane Bronckers, Jonathan Borremans, Piet Wambacq, Yves Rolain:
A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS. 2651-2659 - Sanggeun Jeon, Yu-Jiu Wang, Hua Wang, Florian Bohn, Arun Natarajan, Aydin Babakhani, Ali Hajimiri:
A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS. 2660-2673 - Aydin Babakhani, David B. Rutledge, Ali Hajimiri:
Transmitter Architectures Based on Near-Field Direct Antenna Modulation. 2674-2692 - Jonathan Borremans, Andrea Bevilacqua, Stephane Bronckers, Morin Dehan, Maarten Kuijk, Piet Wambacq, Jan Craninckx:
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. 2693-2705 - Stephan C. Blaakmeer, Eric A. M. Klumperink, Domine M. W. Leenaerts, Bram Nauta:
The Blixer, a Wideband Balun-LNA-I/Q-Mixer Topology. 2706-2715 - Andrea Mazzanti, Pietro Andreani:
Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise. 2716-2729 - Daquan Huang, Tim R. LaRocca, Mau-Chung Frank Chang, Lorene Samoska, Andy Fung, Richard L. Campbell, Michael Andrews:
Terahertz CMOS Frequency Generator Using Linear Superposition Technique. 2730-2738 - Wei L. Chan, John R. Long:
A 56-65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS. 2739-2746 - Ichiro Aoki, Scott D. Kee, Rahul Magoon, Roberto Aparicio, Florian Bohn, Jeff Zachan, Geoff Hatcher, Donald McClymont, Ali Hajimiri:
A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier. 2747-2758 - Joachim Becker, Fabian Henrici, Stanis Trendelenburg, Maurits Ortmanns, Yiannos Manoli:
A Field-Programmable Analog Array of 55 Digitally Tunable OTAs in a Hexagonal Lattice. 2759-2768 - Johan F. Witte, Johan H. Huijsing, Kofi A. A. Makinwa:
A Current-Feedback Instrumentation Amplifier With 5 µV Offset for Bidirectional High-Side Current-Sensing. 2769-2775 - Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott:
A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. 2776-2786 - Kevin J. Wang, Ashok Swaminathan, Ian Galton:
Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL. 2787-2797 - Young-Jin Woo, Hanh-Phuc Le, Gyu-Ha Cho, Gyu-Hyeong Cho, Seong-Il Kim:
Load-Independent Control of Switching DC-DC Converters With Freewheeling Current Feedback. 2798-2808 - Wing-Yee Chu, Bertan Bakkaloglu, Sayfe Kiaei:
A 10 MHz Bandwidth, 2 mV Ripple PA Regulator for CDMA Transmitters. 2809-2819 - Murat Demirkan, Richard R. Spencer:
A Pulse-Based Ultra-Wideband Transmitter in 90-nm CMOS for WPANs. 2820-2828 - Oliver Werther, Mark S. Cavin, Angelika Schneider, Robert Renninger, Bo Liang, Long Bu, Yalin Jin, John Rogers, John Marcincavage:
A Fully Integrated 14 Band, 3.1 to 10.6 GHz 0.13 μm SiGe BiCMOS UWB RF Transceiver. 2829-2843 - Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking. 2844-2852 - Edward A. Keehr, Ali Hajimiri:
Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers. 2853-2867 - Ahmad Mirzaei, Hooman Darabi:
A Low-Power WCDMA Transmitter With an Integrated Notch Filter. 2868-2881 - Masoud Zargari, Lalitkumar Nathawad, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Richard Chang, Hakan Dogan, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Suni Mendis, Andrew Chang, Yashar Rajavi, Steve Hung-Min Jen, David K. Su, Bruce A. Wooley:
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. 2882-2895 - William W. Si, David Weber, Shahram Abdollahi-Alibeik, MeeLan Lee, Richard Chang, Hakan Dogan, Haitao Gan, Yashar Rajavi, Susan Luschas, Soner Özgür, Paul J. Husted, Masoud Zargari:
A Single-Chip CMOS Bluetooth v2.1 Radio SoC. 2896-2904 - Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz:
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth. 2905-2920 - Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo:
A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC. 2921-2928 - Hidemi Noguchi, Nobuhide Yoshida, Hiroaki Uchida, Manabu Ozaki, Shunichi Kanemitsu, Shigeki Wada:
A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback. 2929-2938 - Oscar E. Agazzi, Mario R. Hueda, Diego E. Crivelli, Hugo S. Carrer, Ali Nazemi, German C. Luna, Facundo A. Ramos, Ramiro R. Lopez, Carl R. Grace, Bilal Kobeissy, Cindra Abidin, Mohammad Kazemi, Mahyar Kargar, César Marquez, Sumant Ramprasad, Federico Bollo, Vladimir A. Posse, Stephen Wang, Georgios Asmanis, George Eaton, Norman Swenson, Tom Lindsay, Paul Voois:
A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at 10 Gb/s. 2939-2957 - Hyeon-Min Bae, Jonathan B. Ashbrook, Naresh R. Shanbhag, Andrew C. Singer:
Fast Power Transient Management for OC-192 WDM Add/Drop Networks. 2958-2966 - Sander L. J. Gierkink:
Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump. 2967-2976 - Cristiano Niclass, Claudio Favi, Theo Kluter, Marek Gersbach, Edoardo Charbon:
A 128 × 128 Single-Photon Image Sensor With Column-Level 10-Bit Time-to-Digital Converter Array. 2977-2989 - Keith Fife, Abbas El Gamal, H.-S. Philip Wong:
A Multi-Aperture Image Sensor With 0.7 µm Pixels in 0.11 µm CMOS Technology. 2990-3005 - Al-Thaddeus Avestruz, Wesley Santa, Dave Carlson, Randy Jensen, Scott Stanslaski, Alan Helfenstine, Tim Denison:
A 5 µW/Channel Spectral Analysis IC for Chronic Bidirectional Brain-Machine Interfaces. 3006-3024 - Refet Firat Yazicioglu, Patrick Merken, Robert Puers, Chris Van Hoof:
A 200 µW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems. 3025-3038 - Chinwuba D. Ezekwe, Bernhard E. Boser:
A Mode-Matching ΣΔ Closed-Loop Vibratory Gyroscope Readout Interface With a 0.004°/s/√Hz Noise Floor Over a 50 Hz Band. 3039-3048
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