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2020 – today
- 2024
[j43]Yu-Lun Hsu
, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation. IEEE Open J. Circuits Syst. 5: 189-198 (2024)- 2023
- [c60]Xiao-Juan Huang, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang, Sau-Gee Chen:
A MATE-GDBF Algorithm for Irregular Punctured LDPC Codes and Its Decoder Implementation. APCCAS 2023: 323-327 - 2022
- [j42]Li-Wei Liu, Mu-Hua Yuan, Yen-Chin Liao, Hsie-Chia Chang:
A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories. IEEE Open J. Circuits Syst. 3: 180-191 (2022) - [j41]Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications. IEEE Open J. Circuits Syst. 3: 228-236 (2022) - [c59]Shao Wen Cheng, Kai Jyun Hung, Hsie-Chia Chang, Yen-Chin Liao:
An Attention-based Neural Network on Multiple Speaker Diarization. AICAS 2022: 431-434 - [c58]Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
A Clustering-based ML Scheme for Capacity Approaching Soft Level Sensing in 3D TLC NAND. ICASSP 2022: 4078-4082 - 2021
- [c57]Ya-Yun Hou, Shaopeng Lai, Hung-Kun Chang, Yun-Wen Lu, Hsie-Chia Chang:
A 45.4x∼221.2x latency Improvement of SRP-5 Cryptographic Engine for Smart Grid Network. A-SSCC 2021: 1-3 - [c56]Chieh-Yu Lin, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications. ISCAS 2021: 1-5 - [c55]Sukhwan Lim, Yongpan Liu, Luca Benini, Tanay Karnik, Hsie-Chia Chang:
F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors. ISSCC 2021: 513-516 - [c54]Yu-En Hsu, Yen-Chin Liao, Hsie-Chia Chang:
A Two-Stage Path Planning Engine for Robot Navigation System. SoCC 2021: 218-223 - 2020
- [j40]Tony Chan Carusone, Mingoo Seok, Hsie-Chia Chang, Meng-Fan Chang:
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 55(1): 3-5 (2020) - [c53]Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang:
Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification. DATE 2020: 891-896 - [c52]Wei Chiang, Hsie-Chia Chang, Chen-Yi Lee:
An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j39]Yen-Chin Liao, Chien Lin, Hsie-Chia Chang, Shu Lin:
A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1219-1230 (2019) - [c51]Wei-Chien Kuo, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation. SoCC 2019: 113-117 - [c50]Yun-Wen Lu, Antoon Purnal, Simon Vandenhende, Chen-Yi Lee, Ingrid Verbauwhede, Hsie-Chia Chang:
A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR. VLSI-DAT 2019: 1-4 - 2018
- [c49]Po-Hsun Chang, Chen-Yang Lin, Chia-Hsiang Sun, Yen-Chin Liao, Hsie-Chia Chang:
A 188-Length Full Code Rate 333Mbps 1.08mm2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A. ISCAS 2018: 1-4 - [c48]Yen-Chin Liao, Hsie-Chia Chang, Shu Lin:
Scalable Globally-Coupled Low-Density Parity Check Codes. ISTC 2018: 1-5 - [c47]Yen-Chin Liao, Hsie-Chia Chang, Shu Lin:
Generalized Globally-Coupled Low-Density Parity-Check Codes. ITW 2018: 1-5 - [c46]Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee:
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. VLSI-DAT 2018: 1-4 - 2017
- [j38]Yu-Ming Huang, Hsie-Chia Chang, Hsiang-Pang Li:
Re-Polarization Processing in Extended Polar Codes. IEICE Trans. Commun. 100-B(10): 1765-1777 (2017) - [j37]Szu-Chi Chung, Chun-Yuan Yu, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee:
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2522-2531 (2017) - 2016
- [j36]Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 863-867 (2016) - [j35]Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang:
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1293-1304 (2016) - [c45]Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. A-SSCC 2016: 337-340 - 2015
- [j34]Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang:
An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 65-69 (2015) - [j33]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 507-516 (2015) - [j32]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 301-305 (2015) - [j31]Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2523-2532 (2015) - [j30]Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 88-97 (2015) - [j29]Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1235-1244 (2015) - [c44]Kelvin Yi-Tse Lai, Ming-Feng Shiu, Yi-Wen Lu, Yingchieh Ho, Yu-Chi Kao, Yu-Tao Yang, Gary Wang, Keng-Ming Liu, Hsie-Chia Chang, Chen-Yi Lee:
A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process. A-SSCC 2015: 1-4 - [c43]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. ESSCIRC 2015: 96-99 - [c42]Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee:
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. ISCAS 2015: 1450-1453 - [c41]Kuo-Kuang Yen, Yen-Chin Liao, Hsie-Chia Chang:
Design of LT code degree distribution with profiled output ripple size. SiPS 2015: 1-6 - 2014
- [j28]Yi-Min Lin, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee:
A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2110-2118 (2014) - [j27]Hsiu-Chi Chang, Hsie-Chia Chang:
Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes. IEEE Trans. Commun. 62(6): 1779-1789 (2014) - [j26]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 49-61 (2014) - [c40]Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee:
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. A-SSCC 2014: 229-232 - [c39]Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee:
A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring. A-SSCC 2014: 293-296 - [c38]Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. ISCAS 2014: 409-412 - [c37]Hsiu-Chi Chang, Hsie-Chia Chang:
Iterative multi-step decoding for a class of multi-step majority-logic decodable cyclic codes. ISTC 2014: 32-36 - [c36]Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee:
A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications. VLSIC 2014: 1-2 - 2013
- [j25]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes. IEEE Commun. Lett. 17(5): 976-979 (2013) - [j24]Hsiu-Chi Chang, Chih-Lung Chen, Hsie-Chia Chang:
An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes. IEEE Commun. Lett. 17(10): 1980-1983 (2013) - [j23]Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang:
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis. IEEE J. Solid State Circuits 48(11): 2662-2670 (2013) - [j22]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, John K. Zao, Hsie-Chia Chang:
Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection. IEEE Trans. Multim. 15(8): 2162-2175 (2013) - [j21]Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2160-2164 (2013) - [c35]Chi-Heng Yang, Yi-Hsun Chen, Hsie-Chia Chang:
An area-efficient BCH codec with echelon scheduling for NAND flash applications. ICC 2013: 4332-4336 - [c34]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
Processor with side-channel attack resistance. ISSCC 2013: 50-51 - [c33]Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang:
A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. ISSCC 2013: 222-223 - [c32]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes. WCSP 2013: 1-6 - 2012
- [j20]Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. IEEE J. Solid State Circuits 47(4): 817-831 (2012) - [j19]Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. IEEE J. Solid State Circuits 47(9): 2246-2257 (2012) - [j18]Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine. IEEE Trans. Circuits Syst. II Express Briefs 59-II(2): 103-107 (2012) - [j17]Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor. IEEE Trans. Circuits Syst. II Express Briefs 59-II(5): 287-291 (2012) - [c31]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Non-repetitive encoding with increased degree-1 encoding symbols for LT codes. APCCAS 2012: 655-658 - [c30]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor. CHES 2012: 548-564 - [c29]Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, Hsie-Chia Chang:
A fully parallel BCH codec with double error correcting capability for NOR flash applications. ICASSP 2012: 1605-1608 - [c28]Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee:
A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance. ISCAS 2012: 1456-1459 - [c27]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Stochastic decoding for LDPC convolutional codes. ISCAS 2012: 2621-2624 - [c26]Kuo-Kuang Yen, Chih-Lung Chen, Hsie-Chia Chang:
An improved LT encoding scheme with extended chain lengths. ISITA 2012: 11-15 - [c25]Yi-Hsun Chen, Chi-Heng Yang, Hsie-Chia Chang:
A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. VLSI-DAT 2012: 1-4 - [c24]Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A low cost DPA-resistant 8-bit AES core based on ring oscillators. VLSI-DAT 2012: 1-4 - 2011
- [j16]Cheng-Chi Wong, Hsie-Chia Chang:
High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1412-1420 (2011) - [j15]Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee:
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 682-686 (2011) - [c23]Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee:
A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. ESSCIRC 2011: 71-74 - [c22]Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systems. ESSCIRC 2011: 79-82 - [c21]Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit. ISCAS 2011: 713-716 - 2010
- [j14]Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang:
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electron. 6(4): 551-562 (2010) - [j13]Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. IEEE J. Solid State Circuits 45(2): 422-432 (2010) - [j12]Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. IEEE J. Solid State Circuits 45(11): 2330-2340 (2010) - [j11]Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 546-550 (2010) - [j10]Cheng-Chi Wong, Hsie-Chia Chang:
Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 566-570 (2010) - [c20]Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee:
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. APCCAS 2010: 1203-1206 - [c19]Jen-Wei Lee, Yao-Lin Chen, Chih-Yeh Tseng, Hsie-Chia Chang, Chen-Yi Lee:
A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance. ESSCIRC 2010: 206-209 - [c18]Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang:
A multiple code-rate turbo decoder based on reciprocal dual trellis architecture. ISCAS 2010: 1496-1499 - [c17]Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
An improved soft BCH decoder with one extra error compensation. ISCAS 2010: 3941-3944
2000 – 2009
- 2009
- [j9]Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. Circuits Syst. II Express Briefs 56-II(9): 734-738 (2009) - [j8]Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee:
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1960-1967 (2009) - [c16]Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. CICC 2009: 191-194 - [c15]Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit. ESSCIRC 2009: 404-407 - [c14]Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee:
A 11.5-Gbps LDPC decoder based on CP-PEG code construction. ESSCIRC 2009: 412-415 - 2008
- [j7]Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. IEEE J. Solid State Circuits 43(3): 684-694 (2008) - [c13]Yi Hsuan Wu, Yu Ting Liu, Hsiu-Chi Chang, Yen-Chin Liao, Hsie-Chia Chang:
Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints. ICC 2008: 4496-4500 - [c12]Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua:
Multi-mode message passing switch networks applied for QC-LDPC decoder. ISCAS 2008: 752-755 - [c11]Yi-Kai Lin, Chin-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang:
Structured LDPCcodes with low error floor based on PEG tanner graphs. ISCAS 2008: 1846-1849 - 2007
- [j6]Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu:
Self-Compensation Technique for Simplified Belief-Propagation Algorithm. IEEE Trans. Signal Process. 55(6-2): 3061-3072 (2007) - [c10]Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su:
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. CICC 2007: 273-276 - [c9]Hsiu-Chi Chang, Yen-Chin Liao, Hsie-Chia Chang:
Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems. SiPS 2007: 45-49 - 2006
- [j5]Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
A low power turbo/Viterbi decoder for 3GPP2 applications. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 426-430 (2006) - [c8]Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang:
A self-compensation fixed-width booth multiplier and its 128-point FFT applications. ISCAS 2006 - [c7]Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu:
Carry Estimation for Two's Complement Fixed-Width Multipliers. SiPS 2006: 345-350 - 2005
- [j4]Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
Design of a power-reduction Viterbi decoder for WLAN applications. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1148-1156 (2005) - [c6]Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 3.33Gb/s (1200,720) low-density parity check code decoder. ESSCIRC 2005: 211-214 - 2004
- [c5]Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
A dual mode channel decoder for 3GPP2 mobile wireless communications. ESSCIRC 2004: 483-486 - [c4]Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
A power and area efficient multi-mode FEC processor. ISCAS (2) 2004: 253-256 - [c3]Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang:
Multi-level memory systems using error control codes. ISCAS (2) 2004: 393-396 - 2003
- [j3]Hsie-Chia Chang, Chen-Yi Lee:
A Low-Power Design for Reed-Solomon Decoders. J. Circuits Syst. Comput. 12(2): 159-170 (2003) - 2001
- [j2]Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee:
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. IEEE J. Solid State Circuits 36(2): 229-238 (2001) - [c2]Hsie-Chia Chang, Chen-Yi Lee:
An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm. ISCAS (2) 2001: 649-652
1990 – 1999
- 1999
- [j1]Hsie-Chia Chang, C. Bernard Shung:
New serial architecture for the Berlekamp-Massey algorithm. IEEE Trans. Commun. 47(4): 481-483 (1999) - 1998
- [c1]Hsie-Chia Chang, C. Bernard Shung:
A (208, 192;8) Reed-Solomon decoder for DVD application. ICC 1998: 957-960
Coauthor Index
[c52] [c50] [c46] [j37] [j36] [c45] [j33] [j32] [j31] [j30] [j29] [c44] [c43] [c42] [j28] [j26] [c40] [c39] [c38] [c36] [j21] [c34] [j20] [j19] [j18] [j17] [c30] [c28] [c27] [c24] [j15] [c23] [c22] [c21] [j14] [j13] [j12] [j11] [c20] [c19] [c17] [j9] [j8] [c16] [c15] [c14] [j7] [c12] [c10] [j5] [j4] [c6] [c5] [c4] [j3] [j2] [c2]
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last updated on 2024-05-19 01:04 CEST by the dblp team
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