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ORCID31st ESSCIRC 2005: Grenoble, France
- Laurent Fesquet, Andreas Kaiser, Sorin Cristoloveanu, Michel Brillouët:
Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005. IEEE 2005, ISBN 0-7803-9205-1 - Horst L. Stormer:
"Silicon forever! Really?". 3-6 - Ralph K. Cavin III, Victor V. Zhirnov:
Future devices for information processing. 7-12 - Michael S. Shur
:
Terahertz technology: devices and applications. 13-21 - Eli Yablonovitch:
Silicon nano-photonics: where the photons meet the electrons. 23-25 - Christian Joachim:
Towards a molecule - computer? Resources and technologies to compute within a single molecule. 27-28 - Carlos Mazure, Andre-Jacques Auberton-Herve:
Engineering wafers for the nanotechnology era. 29-38 - Lawrence E. Larson, Peter M. Asbeck, Donald F. Kimball:
Digital control of RF power amplifiers for next-generation wireless communications. 39-44 - Bram Nauta, Anne-Johan Annema:
Analog/RF circuit design techniques for nanometerscale IC technologies. 45-53 - H.-S. Philip Wong:
Nanoelectronics: nanotubes, nanowires, molecules, and novel concepts. 55-61 - Lothar Risch:
Pushing CMOS beyond the roadmap. 63-68 - Berndt M. Gammel, Stefan J. Ruping:
Smart cards inside. 69-74 - Emmanuel Racape, Jean Michel Daga:
A PMOS-switch based charge pump, allowing lost cost implementation on a CMOS standard process. 77-80 - Siew Kuok Hoon, Norm Culp, Jun Chen, Franco Maloberti:
A PWM dual-output DC/DC boost converter in a 0.13μm CMOS technology for cellularphone backlight application. 81-84 - Luca Mensi, Luigi Colalongo, Anna Richelli, Zsolt Miklós Kovács-Vajna:
A new integrated charge pump architecture using dynamic biasing of pass transistors. 85-88 - Olivier Dupuis, Xiao Sun, Geert Carchon, Philippe Soussan, Mattias Ferndahl, Stefaan Decoutere, Walter De Raedt:
24 GHz LNA in 90nm RF-CMOS with high-Q above-IC inductors. 89-92 - Fernando Fortes, João Costa Freire, Domine Leenaerts, Reza Mahmoudi, Arthur H. M. van Roermund:
A 28.5 GHz monolithic cascode LNA with 70GHz fT SiGe HBTs. 93-96 - (Withdrawn) Notice of Violation of IEEE Publication PrinciplesA 12.5GHz SiGe BICMOS limiting amplifier using a dual offset cancellation loop. 97-100
- Thomas Finateu, Jean-Baptiste Bégueret, Yann Deval, Franck Badets:
GMSK modulation of subharmonic injection locked oscillators. 101-104 - Miguel A. Méndez, Diego Mateo, Xavier Aragonès, José Luis González:
Phase noise degradation of LC-tank VCOs due to substrate noise and package coupling. 105-108 - Mihai A. T. Sanduleanu, Razvan Ionita, Andrei Vladimirescu:
A 34GHz/1V prescaler in 90nm CMOS SOI. 109-112 - Yannis P. Tsividis, Glenn E. R. Cowan, Yee William Li, Kenneth L. Shepard:
Continuous-time DSPs, analog/digital computers and other mixed-domain circuits. 113-116 - Seth Bridges, Miguel E. Figueroa, David Hsu, Chris Diorio:
A reconfigurable VLSI learning array. 117-120 - Hideo Yamasaki, Tadashi Shibata:
A real-time image-feature-extraction and vector-generation VLSI employing arrayed-shift-register architecture. 121-124 - Hideo Yamasaki, Tadashi Shibata:
A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits. 125-128 - Olivier Charlon, Matthias Locher, Henk Visser, David Duperray, J. Cherr, Marc Judson, Alan L. Landesman, C. Hritz, Ulrich Kohlschuetter, Yifeng Zhang, C. Ramesh, Anton Daanen, Minzhan Gao, S. Haas, Vijay Maheshwari, Andreas Bury, Gunnar Nitsche, Artur Wrzyszcz, William Redman-White, Hamid Bonakdar, Rachid El Waffaoui, Mark Bracey:
A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and Bluetooth co-existence applications. 129-132 - Christoph Kienmayer, Mario Engl, Aandreas Desch, Ronald Thüringer, Mohit Berry, Marc Tiebout, Arpad L. Scholtz, Robert Weigel:
17 GHz receiver in TSLP package for WLAN/ISM applications in 0.13 μm CMOS. 133-136 - Changhua Cao, Haifeng Xu, Yu Su, Kenneth K. O:
An 18-GHz, 10.9-dBm fully-integrated power amplifier with 23.5% PAE in 130-nm CMOS. 137-140 - Ullrich R. Pfeiffer, David Goren, Brian A. Floyd, Scott K. Reynolds:
SiGe transformer matched power amplifier for operation at millimeter-wave frequencies. 141-144 - Stephan Henzler, Thomas Nirschi, Christian Pacha, Peter Spindler, Philip Teichmann, Michael Fulde, Jürgen Fischer, Matthias Eireiner, Thomas Fischer, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
Dynamic state-retention flip flop for fine-grained sleep-transistor scheme. 145-148 - Atul Katoch, Harry J. M. Veendrick:
Isodelay output driver design using step-wise charging for low power. 149-152 - Andrea Lodi, Luca Ciccarelli, Domenico Loparco, Roberto Canegallo, Roberto Guerrieri:
Low leakage design of LUT-based FPGAs. 153-156 - Keith A. Jenkins, Anup P. Jose, David F. Heidel:
An on-chip jitter measurement circuit with sub-picosecond resolution. 157-160 - Hendrik van der Ploeg, Maarten Vertregt, Marco Lammers:
A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications. 161-164 - Johnny Bjørnsen, Øystein Moldsvor, Trond Sæther, Trond Ytterdal:
A 220mW 14b 40MSPS gain calibrated pipelined ADC. 165-168 - Georgi I. Radulov, Patrick J. Quinn, Hans Hegt, Arthur H. M. van Roermund:
An on-chip self-calibration method for current mismatch in D/A converters. 169-172 - Remco van de Beek, Domine Leenaerts, Gerard van der Weide:
A fast-hopping single-PLL 3-band UWB synthesizer in 0.25μm SiGe BiCMOS. 173-176 - Adil Koukab, Yu Lei, Michel J. Declercq:
Multistandard carrier generation system for quad-band GSM/WCDMA (FDD-TDD)/WLAN (802.11 a-b-g) radio. 177-180 - Kun-Seok Lee, Eun-yung Sung, In-Chul Hwang, Byeong-Ha Park:
Fast AFC technique using a code estimation and binary search algorithm for wideband frequency synthesis. 181-184 - Ravindran Mohanavelu, Payam Heydari:
A novel 40-GHz flip-flop-based frequency divider in 0.18μm CMOS. 185-188 - Kuo-Hsing Cheng, Yu-Lung Lo:
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. 189-192 - Armin Tajalli, Paul Muller, Mojtaba Atarodi, Yusuf Leblebici:
A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology. 193-196 - Clive Bittlestone:
Design for manufacturing in the nanoscale era. 197-198 - Steven Hsu, Vishak Venkatraman, Sanu Mathew, Himanshu Kaul, Mark A. Anders, Saurabh Dighe, Wayne P. Burleson, Ram Krishnamurthy:
A 2GHz 13.6mW 12 × 9b multiplier for energy efficient FFT accelerators. 199-202 - Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller:
The vector fixed point unit of the synergistic processor element of the cell architecture processor. 203-206 - Ju-Ho Sohn, Jeong-Ho Woo, Ramchan Woo, Hoi-Jun Yoo:
A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications. 207-210 - Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 3.33Gb/s (1200,720) low-density parity check code decoder. 211-214 - David Perels, Simon Haene, Peter Luethi, Andreas Peter Burg, Norbert Felber, Wolfgang Fichtner, Helmut Bölcskei:
ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs. 215-218 - Raffaele Salerno, Marc Tiebout, Hermann Paule, Martin Streibl, Christoph Sandner, Klaus Kropf:
ESD-protected CMOS 3-5 GHz wideband LNA+PGA design for UWB. 219-222 - Mingxu Liu, Jan Craninckx:
A 5-GHz BiCMOS variable-gain low noise amplifier with inductorless low-gain branch. 223-226 - Namsoo Kim, Vladimir Aparin, Kenneth Barnett, Charles J. Persico:
A cellular-band CDMA 0.25μm CMOS LNA linearized using active post-distortion. 227-230 - Woonyun Kim, Sung-Gi Yang, Yeon-kug Moon, Jinhyuck Yu, Heeseon Shin, Woo-Seung Choo, Byeong-Ha Park:
IP2 calibrator using common mode feedback circuitry. 231-234 - Vladimir Aparin:
A modified LMS adaptive filter architecture with improved stability at RF. 235-238 - Vincent Rambeau, Hans Brekelmans, Marc Notten, Kevin Boyle, Jan van Sinderen:
Antenna and input stages of a 470-710 MHz silicon TV tuner for portable applications. 239-242 - Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen:
CAFFEINE: template-free symbolic model generation of analog circuits via canonical form functions and genetic programming. 243-246 - Agnese Bargagli-Stoffi, Jens Sauerbrey, Roland Thewes, Doris Schmitt-Landsiedel:
A 0.6V 100dB 5.2MHz transconductance amplifier realized in a multi-VT process. 247-250 - Franz Schlögl, Horst Zimmermann:
120nm CMOS OPAMP with 690 MHz fT and 128 dB DC gain. 251-254 - Rolf Becker, Willem H. Groeneweg:
A 1 watt audio amplifier in a standard digital 90-nm CMOS technology. 255-258 - Davide Vecchi, Cristiano Azzolini, Andrea Boni, Faouzi Chaahoub, Lorenzo Crespi:
100-MS/s 14-b track-and-hold amplifier in 0.18-μm CMOS. 259-262 - Yevgen Borokhovych, Hans Gustat, Bernd Tillack, Bernd Heinemann, Yuan Lu, Wei-Min Lance Kuo, Xiangtao Li, Ramkumar Krithivasan, John D. Cressler:
A low-power, 10GS/s track-and-hold amplifier in SiGe BiCMOS technology. 263-266 - Takayasu Norimatsu, Ryosuke Fujiwara, Masaru Kokubo, Masayuki Miyazaki, Yasuyuki Okuma, Miki Hayakawa, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura:
A novel UWB impulse-radio transmitter with all-digitally-controlled pulse generator. 267-270 - Lydi Smaini, Carlo Tinella, Didier Helal, Claude Stoecklin, Laurent Chabert, Christophe Devaucelle, Régis Cattenoz, Didier Belot:
Single-chip CMOS pulse generator for UWB systems. 271-274 - Hugo Veenstra, Edwin van der Heijden, Dave van Goor:
15-27 GHz pseudo-noise UWB transmitter for short-range automotive radar in a production SiGe technology. 275-278 - Namjun Cho, Seong-Jun Song, Sunyoung Kim, Shiho Kim, Hoi-Jun Yoo:
A 5.1-μW UHF RFID tag chip integrated with sensors for wireless environmental monitoring. 279-282 - Stefan Groiss, Michael Koeberle:
A high accurate logarithmic amplifier system with wide input range and extreme low temperature coefficient. 283-286 - Ovidiu Vermesan, Lars-Cyril Julin Blystad, Roy Bahr, Magnus Hjelstuen, Lionel Beneteau, Benoit Froelich:
A BiCMOS ultrasound front end signal processor for high temperature applications. 287-290 - David C. Keezer, Carl Gray, Ashraf Majid, Nafeez Taher:
Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components. 291-294 - Koichiro Noguchi, Makoto Nagata:
An on-chip multi-channel waveform monitor for mixed-signal VLSI diagnostics. 295-298 - Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen:
Memory testing improvements through different stress conditions. 299-302 - Bert Serneels, Michiel Steyaert, Wim Dehaene:
A 5.5 V SOPA line driver in a standard 1.2 V 0.13 μm CMOS technology. 303-306 - Roberto Rosales, Mike K. Jackson:
Silicon bipolar circuits for wideband FM CATV transmission. 307-310 - Suheng Chen, James Vandersand, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Mohammad M. Mojarradi:
SOI four-gate transistors (G4-FETs) for high voltage analog applications. 311-314 - Stefano D'Amico, Vito Giannini, Andrea Baschirotto:
A 1.2V-21dBm OIP3 4th-order active-gm-RC reconfigurable (UMTS/WLAN) filter with on-chip tuning designed with an automatic tool. 315-318 - Seyeob Kim, Bonkee Kim, Minsu Jeong, Junghwan Lee, Youngho Cho, Tae Wook Kim, Boeun Kim:
A 43dB ACR low-pass filter with automatic tuning for low-IF conversion DAB/T-DMB tuner IC. 319-322 - Sandro A. P. Haddad, Joël M. H. Karel, Ralf L. M. Peeters, Ronald L. Westra, Wouter A. Serdijn:
Ultra low-power analog Morlet wavelet filter in 0.18 μm BiCMOS technology. 323-326 - Hideaki Majima, Hiroki Ishikuro, Kenichi Agawa, Mototsugu Hamada:
A 1.2-V CMOS complex bandpass filter with a tunable center frequency. 327-330 - Aimad El Mourabit, Guo-Neng Lu, Patrick Pittet:
A low-frequency, sub 1.5-V micropower Gm-C filter based on subthreshold MIFG MOS transistors. 331-334 - Flavio Heer, Sadik Hafizovic, Wendy Franks, Tanja Ugniwenko, Axel W. Blau, Christiane Ziegler, Andreas Hierlemann:
CMOS microelectrode array for bidirectional interaction with neuronal networks. 335-338 - Ali Enteshari, Graham A. Jullien, Orly Yadid-Pecht, Karan V. I. S. Kaler:
All CMOS low power platform for dielectrophoresis bio-analysis. 339-342 - Martin Zimmermann, Tormod Volden, Kai-Uwe Kirstein, Sadik Hafizovic, Jan Lichtenberg, Andreas Hierlemann:
A CMOS-based sensor array system for chemical and biochemical applications. 343-346 - Roberto Canegallo, Mauro Mirandola, Alberto Fazzi, Luca Magagni, Roberto Guerrieri, Karin Kaschlun:
Electrical measurement of alignment for 3D stacked chips. 347-350 - Marco Grassi, Piero Malcovati, Andrea Baschirotto:
A 0.1% accuracy 100Ω-20MΩ dynamic range integrated gas sensor interface circuit with 13+4 bit digital output. 351-354 - Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De:
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. 355-358 - Antonio Pelella, Arthur Tuminaro, Ryan T. Freese, Yuen H. Chan:
A 8Kb domino read SRAM with hit logic and parity checker. 359-362 - Benton H. Calhoun, Anantha P. Chandrakasan:
Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS. 363-366 - Hieu Van Tran, William John Saiki, Jack Edward Frayer, Thuan Vu, Anh Ly, Sang Thanh Nguyen, Hung Quoc Nguyen, Douglas James Lee, Michael Stephen Briner:
A precision high voltage wave-shaper for multi-Gbit source side injection MLC NOR flash memory. 367-370 - Rajiv V. Joshi, Yuen H. Chan:
A novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI. 371-374 - Koen Cornelissens, Patrick Reynaert, Michiel Steyaert:
A 0.18μm CMOS switched capacitor voltage modulator. 375-378 - Justin P. Abbott, Calvin Plett, John W. M. Rogers:
A 1.2V CMOS multiplier for 10 Gbit/s equalization. 379-382 - Peter J. Langlois, John Taylor, Andreas Demosthenous:
Realization of a simple high-value grounded linear resistance in CMOS technology. 383-386 - Nathan Pletcher, Jan M. Rabaey:
A 100 μW, 1.9GHz oscillator with fully digital frequency tuning. 387-390 - Xiaoyan Wang, Ali Fard, Pietro Andreani:
Phase noise analysis and design of a 3-GHz bipolar differential colpitts VCO. 391-394 - Pierre Delatte, Gonzalo Picun, Laurent Demeus, Pascal Simon, Denis Flandre:
A low-power 5 GHz CMOS LC-VCO optimized for high-resistivity SOI substrates. 395-398 - Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita:
Physical random number generators for cryptographic application in mobile devices. 399-402 - G. Fraidy Bouesse, Marc Renaudin, Adrien Witon, Fabien Germain:
A clock-less low-voltage AES crypto-processor. 403-406 - Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Improving DPA security by using globally-asynchronous locally-synchronous systems. 407-410 - Masanori Furuta, Shoji Kawahito, Toru Inoue, Yukinari Nishikawa:
A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors. 411-414 - Roger Steadman, Gereon Vogtmeier, Armin Kemna, Salah Eddine Ibnou Quossai, Bedrich J. Hosticka:
A high dynamic range, high linearity CMOS current-mode image sensor for computed tomography. 415-418 - Guangbin Zhang, Hoi Lee, Jin Liu:
A 35nW/pixel 2D visual motion sensor. 419-422 - Michiel Steyaert, Frederique Gobert, Carolien Hermans, Patrick Reynaert, Bert Serneels:
Digital communication systems: the problem of analog interface circuits. 423-426 - Mihai A. T. Sanduleanu, Eduard Stikvoort:
A 10Gb/s, 3.3V, laser/modulator driver with high power efficiency. 427-430 - Carolien Hermans, Michiel Steyaert:
A 3.5Gbit/s post-amplifier in 0.18μm CMOS. 431-434 - Sami Kurtti, Juha Kostamovaara:
An integrated optical receiver with wide-range timing discrimination characteristics. 435-438 - Christophe Seidl, Harald Schatzmayr, Johannes Sturm, Stefan Groiß, Martin Leifhelm, D. Spitzer, H. Schaunig, Horst Zimmermann:
A programmable OEIC for laser applications in the range from 405nm to 780nm. 439-442 - Vincent Quiquempoix, Philippe Deval, Alexandre Barreto, Gabriele Bellini, Jerry Collings, János Márkus, José B. Silva, Gabor C. Temes:
A low-power 22-bit incremental ADC with 4 ppm INL, 2 ppm gain error and 2 μV DC offset. 443-446 - Trevor C. Caldwell, David A. Johns:
A time-interleaved continuous-time ΔΣ modulator with 20MHz signal bandwidth. 447-450 - Roberto Maurino, Christos Papavassiliou:
A 10mW 81dB cascaded multibit quadrature ΣΔ ADC with a dynamic element matching scheme. 451-454 - Wang Tung Cheng, Kong-Pang Pun, Chiu-Sing Choy, Cheong-Fat Chan:
A 75dB image rejection IF-input quadrature sampling SC ΣΔ modulator. 455-458 - T. S. Doorn, Ed van Tuijl, Daniël Schinkel, Anne-Johan Annema, Marco Berkhout, Bram Nauta:
An audio FIR-DAC in a BCD process for high power class-D amplifiers. 459-462 - Valentin A. Abramzon, Elad Alon, Bita Nezamfar, Mark Horowitz:
Scalable circuits for supply noise measurement. 463-466 - Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Autonomous di/dt noise control scheme for margin aware operation. 467-470 - Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir:
A built-in IDDQ testing circuit. 471-474 - Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
Optimally-placed twists in global on-chip differential interconnects. 475-478 - Nan Li, Makoto Ikeda, Kunihiro Asada:
Analysis of low noise three-phase asynchronous data transmission. 479-482 - Manuel Innocent, Guy Meynants:
Differential image sensor with high common mode rejection. 483-486 - David Stoppa, Lucio Pancheri, Mauro Scandiuzzo, Mattia Malfatti, Gianmaria Pedretti, Lorenzo Gonzo:
A single-photon-avalanche-diode 3D imager. 487-490 - Alexander Nemecek, Klaus Oberhauser, Horst Zimmermann:
Correlating PIN-photodetector with novel difference-integrator concept for range-finding applications. 491-494 - Mirko Gravati, Maurizio Valle, Giuseppe Ferri, Nicola Carlo Guerrini, Linder Reyes:
A novel current-mode very low power analog CMOS four quadrant multiplier. 495-498 - Kerem Akarvardar, Suheng Chen, Benjamin J. Blalock, Sorin Cristoloveanu, Pierre Gentil, Mohammad M. Mojarradi:
A novel four-quadrant analog multiplier using SOI four-gate transistors (G4-FETs). 499-502 - Alessandro Cabrini, Guido De Sandre, Laura Gobbi, Piero Malcovati, Marco Pasotti, Marco Poles, F. Rigoni, Guido Torelli:
A 1 V, 26 μW extended temperature range band-gap reference in 130-nm CMOS technology. 503-506 - Bernhard Goll, Horst Zimmermann:
A low-power 2-GSample/s comparator in 120 nm CMOS technology. 507-510 - Masahiro Ito, Taizo Yamawaki, Masumi Kasahara, Steve Williams:
Variable gain amplifier in polar loop modulation transmitter for EDGE. 511-514 - Jussi Ryynänen, Mikko Hotti, Ville Saari, Jarkko Jussila, Arto Malinen, Lauri Sumanen, Tero Tikka, Kari Halonen:
WCDMA multicarrier receiver for base-station applications. 515-518 - Bruno Pellat, Jean-Pierre Blanc, Franck Goussin, Davy Thevenet, Sandrine Majcherczak, Fabien Reaute, Didier Belot, Patrice Garcia, Pascal Persechini, Patrick Cerisier, Patrick Conti, Philippe Level, Michael Kraemer, Angelo Granata:
Fully-integrated WCDMA SiGeC BiCMOS transceiver. 519-522 - Jian Li, Jianyun Zhang, Bo Shen, Xiaoyang Zeng, Yawei Guo, Tingao Tang:
A 10BIT 30MSPS CMOS A/D converter for high performance video applications. 523-526 - Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. 527-530 - Seung-Chul Lee, Gyu-Hyun Kim, Jong-Kee Kwon, Jongdae Kim, Seung-Hoon Lee:
Offset and dynamic gain-mismatch reduction techniques for 10b 200ms/s parallel pipeline ADCs. 531-534 - Charles T. Peach, Ashoke Ravi, Rosie Bishop, Krishnamurthy Soumyanath, David J. Allstot:
A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS. 535-538
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