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ORCIDTadashi Shibata
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2010 – 2019
- 2016
[j28]Wenjun Xia, Yoshio Mita, Tadashi Shibata:
A Nearest Neighbor Classifier Employing Critical Boundary Vectors for Efficient On-Chip Template Reduction. IEEE Trans. Neural Networks Learn. Syst. 27(5): 1094-1107 (2016)- 2014
- [j27]Litian Sun, Tadashi Shibata:
Unsupervised Object Extraction by Contour Delineation and Texture Discrimination Based on Oriented Edge Features. IEEE Trans. Circuits Syst. Video Technol. 24(5): 780-788 (2014) - [j26]Hongbo Zhu, Tadashi Shibata:
A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture. IEEE Trans. Circuits Syst. Video Technol. 24(10): 1787-1799 (2014) - [c78]Zuoxun Hou, Hongbo Zhu, Nanning Zheng, Tadashi Shibata:
A single-chip 600-fps real-time action recognition system employing a hardware friendly algorithm. ISCAS 2014: 762-765 - 2013
- [j25]Ruihan Bao, Tadashi Shibata:
A hardware friendly algorithm for action recognition using spatio-temporal motion-field patches. Neurocomputing 100: 98-106 (2013) - [j24]Pushe Zhao, Hongbo Zhu, He Li, Tadashi Shibata:
A Directional-Edge-Based Real-Time Object Tracking System Employing Multiple Candidate-Location Generation. IEEE Trans. Circuits Syst. Video Technol. 23(3): 503-517 (2013) - [c77]Yitao Ma, Tadashi Shibata, Tetsuo Endoh:
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications. ISCAS 2013: 1248-1251 - [c76]Atsushi Shimada, Hongbo Zhu, Tadashi Shibata:
A VLSI DBSCAN processor composed as an array of micro agents having self-growing interconnects. ISCAS 2013: 2062-2065 - [c75]Pushe Zhao, Hongbo Zhu, Tadashi Shibata:
A multiple-candidate-regeneration-based object tracking system with enhanced learning capability by nearest neighbor classifier. ISCAS 2013: 2392-2395 - 2012
- [c74]Litian Sun, Tadashi Shibata:
Unsupervised object extraction by contour delineation and texture-based discrimination. EUSIPCO 2012: 1945-1949 - [c73]Renyuan Zhang, Tadashi Shibata:
Real-Time On-Line-Learning Support Vector Machine Based on a Fully-Parallel Analog VLSI Processor. ICAISC (2) 2012: 223-230 - [c72]Ruihan Bao, Tadashi Shibata:
A Hierarchical Action Recognition System Applying Fisher Discrimination Dictionary Learning via Sparse Representation. ICAISC (1) 2012: 468-476 - [c71]Pushe Zhao, Renyuan Zhang, Tadashi Shibata:
Real-Time Object Tracking Algorithm Employing On-Line Support Vector Machine and Multiple Candidate Regeneration. ICAISC (1) 2012: 617-625 - [c70]Shigetaka Morikawa, Tadashi Shibata:
Scene image recognition based on the sequence of local image vectors represented by oriented edges. ICASSP 2012: 1313-1316 - [c69]Mio Nishiyama, Tadashi Shibata:
Translation-invariant motion perception for multiple objects using grid partitioning representation. ICSPCS 2012: 1-8 - [c68]Hongbo Zhu, Tadashi Shibata:
A real-time motion-feature-extraction image processor employing digital-pixel-sensor-based parallel architecture. ISCAS 2012: 1612-1615 - [c67]Wenjun Xia, Tadashi Shibata:
Self-adaptive quasi-Gaussian circuits for analog on-chip-trainable multi-class classifiers. ISCAS 2012: 2893-2896 - 2011
- [c66]Ruihan Bao, Tadashi Shibata:
Spatio-temporal motion field descriptors for the hierarchical action recognition system. ICSPCS 2011: 1-6 - [c65]Robert Grou-Szabo, Tadashi Shibata:
A dominant-noise discrimination system for images corrupted by content-independent noises without a priori references. ICSPCS 2011: 1-6 - [c64]Wenjun Xia, Tadashi Shibata:
Critical Boundary Vector Concept in Nearest Neighbor Classifiers using k-Means Centers for Efficient Template Reduction. IJCCI (NCTA) 2011: 93-98 - [c63]Yitao Ma, Tetsuo Endoh, Tadashi Shibata:
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching. ISOCC 2011: 203-206 - 2010
- [j23]Hitoshi Hayakawa, Tadashi Shibata:
Block-matching-based motion field generation utilizing directional edge displacement. Comput. Electr. Eng. 36(4): 617-625 (2010) - [j22]Jia Hao, Tadashi Shibata:
An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations. IEICE Trans. Inf. Syst. 93-D(1): 94-106 (2010) - [j21]Jun Chen, Tadashi Shibata:
A Neuron-MOS-Based VLSI Implementation of Pulse-Coupled Neural Networks for Image Feature Generation. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1143-1153 (2010) - [j20]Kyunghee Kang, Tadashi Shibata:
An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1513-1524 (2010) - [c62]Trong Tu Bui, Tadashi Shibata:
A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques. DELTA 2010: 54-57 - [c61]Norihiro Takahashi, Tadashi Shibata:
A row-parallel cyclic-line-access edge detection CMOS image sensor employing global thresholding operation. ISCAS 2010: 625-628 - [c60]Zhuoli Sun, Kyunghee Kang, Tadashi Shibata:
A self-learning multiple-class classifier using multi-dimensional quasi-Gaussian analog circuits. ISCAS 2010: 2330-2333 - [c59]Hongbo Zhu, Pushe Zhao, Tadashi Shibata:
Directional-edge-based object tracking employing on-line learning and regeneration of multiple candidate locations. ISCAS 2010: 2630-2633
2000 – 2009
- 2009
- [j19]Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata:
A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter. Integr. 42(2): 254-261 (2009) - [j18]Kiyoto Ito, Benjamas Tongprasit, Tadashi Shibata:
A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(1): 114-123 (2009) - [j17]Norihiro Takahashi, Kazuhide Fujita, Tadashi Shibata:
A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensors. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(11): 2384-2392 (2009) - [c58]Tadashi Shibata:
Bio-inspired devices, circuits and systems. ESSCIRC 2009: 8-15 - [c57]Hongbo Zhu, Tadashi Shibata:
A real-time image recognition system using a global directional-edge-feature extraction VLSI processor. ESSCIRC 2009: 248-251 - [c56]Norihiro Takahashi, Tadashi Shibata:
A Non-subtraction Configuration of Self-similitude Architecture for Multiple-Resolution Edge-Filtering CMOS Image Sensor. ICANN (1) 2009: 391-400 - [c55]Mio Nishiyama, Tadashi Shibata:
Normalized scoring of Hidden Markov Models by on-line learning and its application to gesture-sequence perception. ICIP 2009: 3565-3568 - [c54]Yudai Fukuoka, Tadashi Shibata:
Block-matching-based CMOS Optical Flow Sensor using Only-nearest-neighbor Computation. ISCAS 2009: 1485-1488 - [c53]Kyunghee Kang, Tadashi Shibata:
An On-chip-trainable Gaussian-kernel Analog Support Vector Machine. ISCAS 2009: 2661-2664 - [c52]Kazuhide Fujita, Kiyoto Ito
, Tadashi Shibata:
A Single-motion-vector/Cycle-generation Optical Flow Processor Employing Directional-edge Histogram Matching. ISCAS 2009: 3022-3025 - [c51]Takuki Nakagawa, Tadashi Shibata:
A Real-time Image Feature Vector Generator Employing Functional Cache Memory for Edge Flags. ISCAS 2009: 3026-3029 - 2008
- [j16]Tadashi Shibata:
Special Section on Advanced Processors Based on Novel Concepts in Computation. IEICE Trans. Electron. 91-C(9): 1385 (2008) - [c50]Robert Grou-Szabo, Tadashi Shibata:
Blind image compression history determination using dynamic thresholding. ICASSP 2008: 1005-1008 - [c49]Norihiro Takahashi, Kazuhide Fujita, Tadashi Shibata:
An analog self-similitude edge-filtering processor for multiple-resolution image perception. ISCAS 2008: 1640-1643 - [c48]Hitoshi Hayakawa, Tadashi Shibata:
Spatiotemporal projection of motion field sequence for generating feature vectors in gesture perception. ISCAS 2008: 3526-3529 - 2007
- [j15]Kazumi Nakamatsu, Yoshio Mita, Tadashi Shibata:
An Intelligent Action Control System Based on Extended Vector Annotated Logic Program and its Hardware Implementation. Intell. Autom. Soft Comput. 13(3): 289-304 (2007) - [j14]Toshihiko Yamasaki, Tadashi Shibata:
A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection. IEEE J. Solid State Circuits 42(2): 422-430 (2007) - [j13]Hideo Yamasaki, Tadashi Shibata:
A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture. IEEE J. Solid State Circuits 42(9): 2046-2053 (2007) - [c47]Jia Hao, Tadashi Shibata:
A speed adaptive ego-motion detection system using EDGE-histograms produced by variable graduation method. EUSIPCO 2007: 1590-1594 - [c46]Yasufumi Suzuki, Tadashi Shibata:
Validating directional edge-based image feature representations in face recognition by spatial correlation-based clustering. EUSIPCO 2007: 1940-1944 - [c45]Kazuhide Fujita, Kiyoto Ito, Tadashi Shibata:
A Feature-Based Optical Flow Processor Architecture Featuring Single-Motion-Vector/Cycle Generation. SoC 2007: 1-4 - [c44]Kiyoto Ito, Tadashi Shibata:
Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture. SoC 2007: 1-4 - [c43]Hirotsugu Shikano, Kiyoto Ito, Kazuhide Fujita, Tadashi Shibata:
A Real-Time Learning Processor Based on K-means Algorithm with Automatic Seeds Generation. SoC 2007: 1-4 - 2006
- [c42]Daisuke Moriya, Yasufumi Suzuki, Tadashi Shibata, Masakazu Yagi, Kenji Takada:
Multi-view face detection and pose estimation employing edge-based feature vectors. EUSIPCO 2006: 1-5 - [c41]Yasufumi Suzuki, Tadashi Shibata:
Illumination-invariant face identification using edge-based feature vectors in pseudo-2D Hidden Markov Models. EUSIPCO 2006: 1-5 - [c40]Jia Hao, Tadashi Shibata:
A Vlsi-Implementation-Friendly EGO-Motion Detection Algorithm Based on Edge-Histogram Matching. ICASSP (2) 2006: 245-248 - [c39]Kiyoto Ito, Tadashi Shibata:
A time-domain gradient-detection architecture for VLSI analog motion sensors. ISCAS 2006 - [c38]Benjamas Tongprasit, Tadashi Shibata:
Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI. ISCAS 2006 - 2005
- [j12]Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata:
A low-power and compact CDMA matched filter based on switched-current technology. IEEE J. Solid State Circuits 40(4): 926-932 (2005) - [j11]Makoto Ogawa, Tadashi Shibata:
A delay-encoding-logic array processor for dynamic-programming matching of data sequences. IEEE J. Solid State Circuits 40(7): 1578-1582 (2005) - [c37]Hideo Yamasaki, Tadashi Shibata:
A real-time image-feature-extraction and vector-generation VLSI employing arrayed-shift-register architecture. ESSCIRC 2005: 121-124 - [c36]Hideo Yamasaki, Tadashi Shibata:
A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits. ESSCIRC 2005: 125-128 - [c35]Kunio Kawahara, Tadashi Shibata:
A new distance measure employing element-significance factors for robust image classification. EUSIPCO 2005: 1-4 - [c34]Yasufumi Suzuki, Tadashi Shibata:
Multiple-resolution edge-based feature representations for robust face segmentation and verification. EUSIPCO 2005: 1-4 - [c33]Benjamas Tongprasit, Kiyoto Ito, Tadashi Shibata:
A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering. ISCAS (3) 2005: 2389-2392 - [c32]Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata:
A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter. ISCAS (6) 2005: 5365-5368 - [c31]Yusuke Nakashita, Yoshio Mita, Tadashi Shibata:
An Analog Visual Pre-Processing Processor Employing Cyclic Line Access in Only-Nearest-Neighbor-Interconnects Architecture. NIPS 2005: 971-978 - 2004
- [c30]Makoto Ogawa, Tadashi Shibata:
A delay-encoding-logic array processor for dynamic programming matching. ESSCIRC 2004: 311-314 - [c29]Yasufumi Suzuki, Tadashi Shibata:
An edge-based face detection algorithm robust against illumination, focus, and scale variations. EUSIPCO 2004: 2279-2282 - [c28]Yasufumi Suzuki, Tadashi Shibata:
Multiple-clue face detection algorithm using edge-based feature vectors. ICASSP (5) 2004: 737-740 - [c27]Hideo Yamasaki, Tadashi Shibata:
A real-time VLSI median filter employing two-dimensional bit-propagating architecture. ISCAS (2) 2004: 349-352 - [c26]Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata:
Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters. ISCAS (1) 2004: 425-428 - [c25]Masayuki Umejima, Toshihiko Yamasaki, Tadashi Shibata:
A bump-circuit-based motion detector using projected-activity histograms. ISCAS (1) 2004: 749-752 - 2003
- [j10]Koji Okamoto, Takashi Morie, Akira Yamamoto, Kouichi Nagano, Koji Sushihara, Hiroyuki Nakahira, Ryusuke Horibe, Kazutoshi Aida, Toshihiko Takahashi, Minoru Ochiai, Akinobu Soneda, Toru Kakiage, Tamaki Iwasaki, Hiroshi Taniuchi, Tadashi Shibata, Takahiro Ochi, Masao Takiguchi, Takashi Yamamoto, Tadayoshi Seike, Akira Matsuzawa:
A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications. IEEE J. Solid State Circuits 38(11): 1981-1991 (2003) - [j9]Bernabé Linares-Barranco, Andreas G. Andreou, Giacomo Indiveri, Tadashi Shibata:
Guest editorial - Special issue on neural networks hardware implementations. IEEE Trans. Neural Networks 14(5): 976-979 (2003) - [j8]Masakazu Yagi, Tadashi Shibata:
An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems. IEEE Trans. Neural Networks 14(5): 1144-1161 (2003) - [j7]Toshihiko Yamasaki, Tadashi Shibata:
Analog soft-pattern-matching classifier using floating-gate MOS technology. IEEE Trans. Neural Networks 14(5): 1257-1265 (2003) - [c24]Teruyasu Taguchi, Makoto Ogawa, Tadashi Shibata:
An analog image processing LSI employing scanning line-parallel processing. ESSCIRC 2003: 65-68 - [c23]Qian-Rong Gu, Tadashi Shibata:
Speaker and text independent language identification using predictive error histogram vectors. ICASSP (1) 2003: 36-39 - [c22]Shantanu Chakrabartty, Masakazu Yagi, Tadashi Shibata, Gert Cauwenberghs:
Robust cephalometric landmark identification using support vector machines. ICASSP (2) 2003: 825-828 - [c21]Shantanu Chakrabartty, Masakazu Yagi, Tadashi Shibata, Gert Cauwenberghs:
Robust cephalometric landmark identification using support vector machines. ICME 2003: 429-432 - [c20]Masakazu Yagi, Hideo Yamasaki, Tadashi Shibata:
A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors. NIPS 2003: 1035-1042 - [c19]Masakazu Yagi, Tadashi Shibata, Chihiro Tanikawa, Kenji Takada:
A Robust Medical Image Recognition System Employing Edge-Based Feature Vector Representation. SCIA 2003: 534-540 - 2002
- [j6]Tadashi Shibata:
Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(3): 600-609 (2002) - [c18]Masakazu Yagi, Tadashi Shibata, Kenji Takada:
Human-perception-like image recognition system based on the Associative Processor architecture. EUSIPCO 2002: 1-4 - [c17]Masakazu Yagi, Tadashi Shibata:
A human-perception-like image recognition system based on PAP vector representation with multi resolution concept. ICASSP 2002: 1045-1048 - [c16]Masakazu Yagi, Tadashi Shibata:
An associative-processor-based mixed signal system for robust grayscale image recognition. ISCAS (5) 2002: 137-140 - [c15]Hiroe Kimura, Tadashi Shibata:
A motion-based analog VLSI saliency detector using quasi-two-dimensional hardware algorithm. ISCAS (3) 2002: 333-336 - [c14]Toshihiko Yamasaki, Teruyasu Taguchi, Tadashi Shibata:
Low-power CDMA analog matched filters based on floating-gate technology. ISCAS (5) 2002: 625-628 - [c13]Keng Hoong Wee, T. Yonezawa, Toshiyuki Nozawa, Tadashi Shibata, Tadahiro Ohmi:
A zone-programmed EEPROM with real-time write monitoring for analog data storage. ISCAS (4) 2002: 655-658 - [c12]Huaiyu Xu, Yoshio Mita, Tadashi Shibata:
Intelligent Internet Search Applications Based on VLSI Associative Processors. SAINT 2002: 230-237 - 2001
- [c11]Keng Hoong Wee, Toshiyuki Nozawa, Takemi Yonezawa, Yuichiro Yamashita, Tadashi Shibata, Tadahiro Ohmi:
High-precision analog EEPROM with real-time write monitoring. ISCAS (1) 2001: 105-108 - [c10]Toshihiko Yamasaki, Tadashi Shibata:
An analog similarity evaluation circuit featuring variable functional forms. ISCAS (3) 2001: 561-564 - [c9]Toshihiko Yamasaki, Atsushi Suzuki, Daisuke Kobayashi, Tadashi Shibata:
A fast self-convergent flash-memory programming scheme for MV and analog data storage. ISCAS (4) 2001: 930-933 - [c8]Toshihiko Yamasaki, Tadashi Shibata:
Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology. NIPS 2001: 1131-1138 - 2000
- [c7]Masakazu Yagi, Masayoshi Adachi, Tadashi Shibata:
A hardware-friendly soft-computing algorithm for image recognition. EUSIPCO 2000: 1-4
1990 – 1999
- 1999
- [j5]Akira Nakada, Tadashi Shibata, Masahiro Konda, Tatsuo Morimoto, Tadahiro Ohmi:
A fully parallel vector-quantization processor for real-time motion-picture compression. IEEE J. Solid State Circuits 34(6): 822-830 (1999) - [j4]Tadahiro Ohmi, Tadashi Shibata, Koji Kotani, Tsutomu Nakai, Akira Nakada, Ning Mei Yu, Masahiro Konda, Tatsuo Morimoto, Yuichiro Yamashita:
Association hardware for intelligent electronic systems. Syst. Comput. Jpn. 30(12): 52-62 (1999) - [c6]Atsuhiko Okada, Tadashi Shibata:
A neuron-MOS parallel associator for high-speed CDMA matched filter. ISCAS (2) 1999: 392-395 - 1998
- [j3]Koji Kotani, Tadashi Shibata, Tadahiro Ohmi:
CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters. IEEE J. Solid State Circuits 33(5): 762-769 (1998) - [c5]Tadashi Shibata:
Functional-Device-Based VLSI for Intelligent Electronic Systems. ISMVL 1998: 317-325 - [c4]Tadashi Shibata:
Right brain computing hardware: a psychological brain model on silicon. KES (3) 1998: 429-435 - [c3]Tatsuo Morimoto, Tadashi Shibata, Tadahiro Ohmi:
Neuron-MOS continuous-time winner-take-all circuit for intelligent data processing. KES (3) 1998: 436-441 - 1996
- [j2]Tadashi Shibata, Tadahiro Ohmi:
Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors. J. Robotics Mechatronics 8(6): 508-515 (1996) - 1995
- [j1]Tadashi Shibata, Hideo Kosaka, Hiroshi Ishii, Tadahiro Ohmi:
A neuron-MOS neural network using self-learning-compatible synapse circuits. IEEE J. Solid State Circuits 30(8): 913-922 (1995) - [c2]Tadashi Shibata, Tsutomu Nakai, Tatsuo Morimoto, Ryu Kaihara, Takeo Yamashita, Tadahiro Ohmi:
Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing. NIPS 1995: 685-691 - 1993
- [c1]Tadashi Shibata, Koji Kotani, Takeo Yamashita, Hiroshi Ishii, Hideo Kosaka, Tadahiro Ohmi:
Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors. NIPS 1993: 919-926
Coauthor Index
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