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ORCIDSoC 2007: Tampere, Finland
- International Symposium on System-on-Chip, SoC 2007, Tampere, Finland, November 20-21, 2007. IEEE 2007, ISBN 978-1-4244-1368-3
- Qiwei Zhang, André B. J. Kokkeler, Gerard J. M. Smit:
A System-level Design Method for Cognitive Radio on a Reconfigurable Multi-processor Architecture. 1-4 - Maher Assaad
, David R. S. Cumming:
CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC. 1-4 - Raimo Mäkelä, Olli Vainio:
Managing Concurrency by Supporting Object-oriented Programming with Hybrid Data-driven Control-flow Processor. 1-4 - Gilson I. Wirth, Christian Fayomi:
The Bulk Built In Current Sensor Approach for Single Event Transient Detection. 1-4 - Yang Qu, Juha-Pekka Soininen, Jari Nurmi:
A Configuration Locking Technique to Reduce the Configuration Overhead of Run-Time Reconfigurable Devices. 1-5 - Jakob Salzmann, Frank Sill, Dirk Timmermann:
Algorithm for Fast Statistical Timing Analysis. 1-4 - Jani Boutellier, Pekka Jääskeläinen, Olli Silvén:
Run-Time Scheduled Hardware Acceleration of MPEG-4 Video Decoding. 1-4 - Susanna Nordstrom, Lars Asplund:
Configurable Hardware/Software Support for Single Processor Real-Time Kernels. 1-4 - Steve Leibson:
Reduce SOC Energy Consumption through Processor ISA Extension. 1-4 - Kiyoto Ito, Tadashi Shibata:
Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture. 1-4 - Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni:
The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology. 1-4 - Martin Palkovic, Henk Corporaal, Francky Catthoor:
Heuristics for Scenario Creation to Enable General Loop Transformations. 1-4 - Hirotsugu Shikano, Kiyoto Ito, Kazuhide Fujita, Tadashi Shibata:
A Real-Time Learning Processor Based on K-means Algorithm with Automatic Seeds Generation. 1-4 - Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Wilfried Philips:
Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication. 1-4 - Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo Hämäläinen:
Optimal Subset Mapping And Convergence Evaluation of Mapping Algorithms for Distributing Task Graphs on Multiprocessor SoC. 1-6 - Tero Säntti, Joonas Tyystjärvi, Juha Plosila:
FPGA Prototype of the REALJava Co-Processor. 1-4 - Guido Schreiner:
Development of Complex SoC Devices Require New Design Technologies. 1 - W. A. Wiggers, Vincent Bakker, André B. J. Kokkeler, Gerard J. M. Smit:
Implementing the conjugate gradient algorithm on multi-core systems. 1-4 - Leos Kafka, Martin Danek, Ondrej Novák:
A Novel Emulation Technique that Preserves Circuit Structure and Timing. 1-4 - Simone Medardoni, Davide Bertozzi, Luca Benini, Enrico Macii:
Control and datapath decoupling in the design of a NoC switch: area, power and performance implications. 1-4 - Mark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan, John S. Thompson:
A New LMMSE Receiver Architecture With Dynamic Filter Length Optimisation. 1-4 - Claudio Mucci, Luca Vanzolini, Antonio Deledda, Fabio Campi, Gerard Gaillat:
Intelligent cameras and embedded reconfigurable computing: a case-study on motion detection. 1-4 - Salvatore Carta, Fabio Mereu, Andrea Acquaviva, Giovanni De Micheli:
MiGra: A Task Migration Algorithm for Reducing Temperature Gradient in Multiprocessor Systems on Chip. 1-6 - Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi:
A New Look at Reversible Logic Implementation of Decimal Adder. 1-4 - Philip K. F. Hölzenspies, Gerard J. M. Smit, Jan Kuper:
Mapping streaming applications on a reconfigurable MPSoC platform at run-time. 1-4 - Kazuhide Fujita, Kiyoto Ito, Tadashi Shibata:
A Feature-Based Optical Flow Processor Architecture Featuring Single-Motion-Vector/Cycle Generation. 1-4 - Henrik Fredriksson, Christer Svensson:
3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus. 1-4 - Marco D. Santambrogio, Matteo Giani, Seda Ogrenci Memik:
Managing Reconfigurable Resources in Heterogeneous Cores Using Portable Pre-Synthesized Templates. 1-4 - Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones:
Sensor Network-On-Chip. 1-4 - Majid Baghaei Nejad, Hannu Tenhunen, Lirong Zheng:
Power Management and Clock Generator for a Novel Passive UWB Tag. 1-4 - Rohit Jindal, Laurent Maillet-Contoz:
Rendezvous-based MoC for untimed TLM. 1 - Scott Hanson, Bo Zhai, David T. Blaauw, Dennis Sylvester:
Energy-Optimal Circuit Design. 1-4 - Mark Croft, Stephen Bailey:
Is Your Low Power Design Switched On? 1-4 - Gert Goossens:
Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systems. 1
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