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ORCIDMario R. Casu
Mario Roberto Casu
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2020 – today
- 2024
[j34]Luca Urbinati
, Mario R. Casu:
High-Level Design of Precision-Scalable DNN Accelerators Based on Sum-Together Multipliers. IEEE Access 12: 44163-44189 (2024)- [j33]Lorenzo Lagostina, Filippo Minnella, Jordi Cortadella, Mario R. Casu, Mihai T. Lazarescu, Luciano Lavagno:
Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2229-2233 (2024) - [c46]Edward Manca, Luca Urbinati, Mario R. Casu:
STAR: Sum-Together/Apart Reconfigurable Multipliers for Precision-Scalable ML Workloads. DATE 2024: 1-6 - 2023
- [j32]Filippo Minnella, Jordi Cortadella, Mario R. Casu, Mihai T. Lazarescu, Luciano Lavagno:
Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops. IEEE Access 11: 35830-35840 (2023) - [j31]Fabrizio Ottati, Chang Gao, Qinyu Chen, Giovanni Brignone, Mario R. Casu, Jason K. Eshraghian, Luciano Lavagno:
To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 1015-1025 (2023) - [c45]Luca Urbinati, Mario R. Casu:
Design-Space Exploration of Mixed-precision DNN Accelerators based on Sum-Together Multipliers. PRIME 2023: 377-380 - [i1]Fabrizio Ottati, Chang Gao, Qinyu Chen, Giovanni Brignone, Mario R. Casu, Jason K. Eshraghian, Luciano Lavagno:
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration. CoRR abs/2306.15749 (2023) - 2022
- [j30]Junnan Shan, Mihai T. Lazarescu, Jordi Cortadella, Luciano Lavagno, Mario R. Casu:
Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1186-1190 (2022) - [c44]Luca Urbinati, Mario R. Casu:
A Reconfigurable 2D-Convolution Accelerator for DNNs Quantized with Mixed-Precision. ApplePies 2022: 210-215 - [c43]Mohammad Amir Mansoori, Mario R. Casu:
Multi-objective Framework for Training and Hardware Co-optimization in FPGAs. ApplePies 2022: 273-278 - [c42]Mohammad Amir Mansoori, Mario R. Casu:
HLS-based dataflow hardware architecture for Support Vector Machine in FPGA. ISCAS 2022: 41-45 - [c41]Luca Urbinati, Mario R. Casu:
A Reconfigurable Depth-Wise Convolution Module for Heterogeneously Quantized DNNs. ISCAS 2022: 128-132 - 2021
- [j29]Osama Bin Tariq, Junnan Shan, Georgios Floros, Christos P. Sotiriou, Mario R. Casu, Mihai Teodor Lazarescu, Luciano Lavagno:
High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs. IEEE Access 9: 54286-54297 (2021) - [j28]Mohammad Amir Mansoori, Pan Lu, Mario R. Casu:
FPGA Acceleration of 3D FDTD for Multi- Antennas Microwave Imaging Using HLS. IEEE Access 9: 122696-122711 (2021) - [j27]Marco Ricci, Bernardita Stitic, Luca Urbinati, Giuseppe Di Guglielmo, Jorge A. Tobon Vasquez, Luca P. Carloni, Francesca Vipiana, Mario R. Casu:
Machine-Learning-Based Microwave Sensing: A Case Study for the Food Industry. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(3): 503-514 (2021) - [j26]Junnan Shan, Mihai T. Lazarescu, Jordi Cortadella, Luciano Lavagno, Mario R. Casu:
CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(2): 301-314 (2021) - [c40]Mohammad Amir Mansoori, Mario R. Casu:
Efficient Training and Hardware Co-design of Machine Learning Models. ApplePies 2021: 243-248 - 2020
- [j25]Jorge A. Tobon, Rosa Scapaticci, Giovanna Turvani, Gennaro Bellizzi, David O. Rodriguez-Duarte, Nadine Joachimowicz, Bernard Duchêne, Enrico Tedeschi, Mario R. Casu, Lorenzo Crocco, Francesca Vipiana:
A Prototype Microwave System for 3D Brain Stroke Imaging. Sensors 20(9): 2607 (2020) - [j24]Junnan Shan, Mihai T. Lazarescu, Jordi Cortadella, Luciano Lavagno, Mario R. Casu:
Power-Optimal Mapping of CNN Applications to Cloud-Based Multi-FPGA Platforms. IEEE Trans. Circuits Syst. 67-II(12): 3073-3077 (2020) - [c39]Luca Urbinati, Marco Ricci, Giovanna Turvani, Jorge A. Tobon Vasquez, Francesca Vipiana, Mario R. Casu:
A Machine-Learning Based Microwave Sensing Approach to Food Contaminant Detection. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c38]Junnan Shan, Mario R. Casu, Jordi Cortadella, Luciano Lavagno, Mihai T. Lazarescu:
Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms. DAC 2019: 3 - [c37]Mohammad Amir Mansoori, Mario R. Casu:
HLS-Based Flexible Hardware Accelerator for PCA Algorithm on a Low-Cost ZYNQ SoC. NORCAS 2019: 1-7 - [c36]Mohammad Amir Mansoori, Mario R. Casu:
Efficient FPGA Implementation of PCA Algorithm for Large Data using High Level Synthesis. PRIME 2019: 65-68 - 2018
- [j23]Francesco Dell'Anna, Tao Dong, Ping Li, Yumei Wen, Mehdi Azadmehr, Mario R. Casu, Yngvar Berg:
Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers. Sensors 18(4): 1245 (2018) - [c35]Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto:
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. DATE 2018: 1151-1154 - [c34]Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto:
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. ISCAS 2018: 1-5 - 2017
- [j22]Mario R. Casu, Paolo Giaccone:
Power-performance assessment of different DVFS control policies in NoCs. J. Parallel Distributed Comput. 109: 193-207 (2017) - [j21]Mario R. Casu, Marco Vacca, Jorge A. Tobon, Azzurra Pulimeno, Imran Sarwar, Raffaele Solimene, Francesca Vipiana:
A COTS-Based Microwave Imaging System for Breast-Cancer Detection. IEEE Trans. Biomed. Circuits Syst. 11(4): 804-814 (2017) - [j20]Daniele Jahier Pagliari, Mario R. Casu, Luca P. Carloni:
Accelerators for Breast Cancer Detection. ACM Trans. Embed. Comput. Syst. 16(3): 80:1-80:25 (2017) - [c33]José V. Escamilla, José Flich, Mario R. Casu:
ICARO-PAPM: Congestion Management with Selective Queue Power-Gating. HPCS 2017: 259-266 - 2016
- [c32]José V. Escamilla, Mario R. Casu, José Flich:
Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy. MCSoC 2016: 241-248 - 2015
- [j19]Mario R. Casu, Paolo Mantovani:
A synchronous latency-insensitive RISC for better than worst-case design. Integr. 48: 72-82 (2015) - [c31]Azzurra Pulimeno, Marco Vacca, Mario R. Casu, Jorge A. Tobon, Francesca Vipiana, Daniele Jahier Pagliari, Raffaele Solimene, Luca P. Carloni:
Microwave Imaging for Breast Cancer Detection: A COTS-Based Prototype. ApplePies 2015: 25-34 - [c30]Daniele Jahier Pagliari, Azzurra Pulimeno, Marco Vacca, Jorge A. Tobon, Francesca Vipiana, Mario R. Casu, Raffaele Solimene, Luca P. Carloni:
A low-cost, fast, and accurate microwave imaging system for breast cancer detection. BioCAS 2015: 1-4 - [c29]Mario R. Casu, Paolo Giaccone:
Rate-based vs delay-based control for DVFS in NoC. DATE 2015: 1096-1101 - [c28]Daniele Jahier Pagliari, Mario R. Casu, Luca P. Carloni:
Acceleration of microwave imaging algorithms for breast cancer detection via High-Level Synthesis. ICCD 2015: 475-478 - 2014
- [j18]Emilio G. Cota, Paolo Mantovani, Michele Petracca, Mario R. Casu, Luca P. Carloni:
Accelerator Memory Reuse in the Dark Silicon Era. IEEE Comput. Archit. Lett. 13(1): 9-12 (2014) - [j17]Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni:
Simulation and design of an UWB imaging system for breast cancer detection. Integr. 47(4): 548-559 (2014) - [j16]Mario R. Casu, Francesco Colonna, Marco Crepaldi, Danilo Demarchi, Mariagrazia Graziano, Maurizio Zamboni:
UWB microwave imaging for breast cancer detection: Many-core, GPU, or FPGA? ACM Trans. Embed. Comput. Syst. 13(3s): 109:1-109:22 (2014) - 2013
- [j15]Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni:
LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 647-651 (2013) - [j14]Francesco Colonna, Mariagrazia Graziano, Mario Roberto Casu, Xiaolu Guo, Maurizio Zamboni:
Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection. VLSI Design 2013: 861691:1-861691:11 (2013) - [c27]Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni:
Breast cancer detection based on an UWB imaging system: Receiver design and simulations. ICICDT 2013: 167-170 - [c26]Andrea Bianco, Mario R. Casu, Paolo Giaccone, Marco Ricca:
Joint delay and power control in single-server queueing systems. OnlineGreenComm 2013: 50-55 - [c25]Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni:
UWB receiver for breast cancer detection: Comparison between two different approaches. SoCC 2013: 55-60 - 2012
- [c24]Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni:
DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems. ASYNC 2012: 118-125 - [c23]Andrea Bianco, Paolo Giaccone, Mario Roberto Casu, Nanfang Li:
Exploiting space diversity and Dynamic Voltage Frequency Scaling in multiplane Network-on-Chips. GLOBECOM 2012: 3080-3085 - 2011
- [j13]Mario R. Casu:
Half-buffer retiming and token cages for synchronous elastic circuits. IET Comput. Digit. Tech. 5(4): 318-330 (2011) - [j12]Mario R. Casu, Massimo Ruo Roch, Sergio Tota, Maurizio Zamboni:
A NoC-based hybrid message-passing/shared-memory approach to CMP design. Microprocess. Microsystems 35(2): 261-273 (2011) - [c22]Mario R. Casu, Stefano Colazzo, Paolo Mantovani:
Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study. ACM Great Lakes Symposium on VLSI 2011: 163-168 - 2010
- [c21]Mario R. Casu:
Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming. ASYNC 2010: 128-137 - [c20]Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Rostagno, Maurizio Zamboni:
MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. DATE 2010: 45-50 - [c19]Massimo Cutrupi, Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano:
A flexible UWB Transmitter for breast cancer detection imaging systems. DATE 2010: 1076-1081
2000 – 2009
- 2009
- [j11]Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni:
A Fully Differential Digital CMOS UWB Pulse Generator. Circuits Syst. Signal Process. 28(5): 649-664 (2009) - [j10]Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni:
A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design. Integr. 42(1): 47-60 (2009) - [j9]Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni:
A Case Study for NoC-Based Homogeneous MPSoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 384-388 (2009) - [c18]Mario R. Casu, Luca Macchiarulo:
Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis. FMGALS@DATE 2009: 35-50 - 2008
- [j8]Mario R. Casu, Marco Crepaldi, Mariagrazia Graziano:
A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(5): 1368-1381 (2008) - 2007
- [j7]Mario R. Casu, Luca Macchiarulo:
Adaptive Latency-Insensitive Protocols. IEEE Des. Test Comput. 24(5): 442-452 (2007) - [c17]Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni:
An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. DATE 2007: 1424-1429 - [c16]Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni:
The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology. SoC 2007: 1-4 - [c15]Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni:
A methodology and a case-study for network-on-chip based MP-SoC architectures. Nano-Net 2007: 9 - 2006
- [j6]Mario R. Casu, Luca Macchiarulo:
Floorplanning With Wire Pipelining in Adaptive Communication Channels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2996-3004 (2006) - [c14]Sergio Tota, Mario R. Casu, Luca Macchiarulo:
Implementation analysis of NoC: a MPSoC trace-driven approach. ACM Great Lakes Symposium on VLSI 2006: 204-209 - 2005
- [j5]Mario R. Casu, Luca Macchiarulo:
Throughput-driven floorplanning with wire pipelining. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 663-675 (2005) - [j4]Mario R. Casu, Giuseppe Durisi:
Implementation aspects of a transmitted-reference UWB receiver. Wirel. Commun. Mob. Comput. 5(5): 537-549 (2005) - [c13]Mario R. Casu, Luca Macchiarulo:
A New System Design Methodology for Wire Pipelined SoC. DATE 2005: 944-945 - [c12]Mario R. Casu, Giuseppe Durisi, Sergio Benedetto:
On the implementation of a transmitted-reference UWB receiver. EUSIPCO 2005: 1-4 - [c11]Mario R. Casu, Luca Macchiarulo:
Floorplan assisted data rate enhancement through wire pipelining: a real assessment. ISPD 2005: 121-128 - 2004
- [j3]Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectron. J. 35(10): 849-857 (2004) - [j2]Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 349-358 (2004) - [c10]Mario R. Casu, Luca Macchiarulo:
A new approach to latency insensitive design. DAC 2004: 576-581 - [c9]Mario R. Casu, Luca Macchiarulo:
Issues in Implementing Latency Insensitive Protocols. DATE 2004: 1390-1391 - [c8]Mario R. Casu, Luca Macchiarulo:
On-Chip Transparent Wire Pipelining. ICCD 2004: 160-167 - [c7]Mario R. Casu, Luca Macchiarulo:
Floorplanning for throughput. ISPD 2004: 62-69 - 2003
- [j1]Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Coupled electro-thermal modeling and optimization of clock networks. Microelectron. J. 34(12): 1175-1185 (2003) - [c6]Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni:
Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS 2003: 90-100 - [c5]M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS 2003: 121-130 - 2002
- [c4]Mario R. Casu, Philippe Flatresse:
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. MTDT 2002: 163-167 - [c3]Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni:
Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS 2002: 198-208 - 2001
- [c2]Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni:
Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED 2001: 287-290 - 2000
- [c1]Mario Roberto Casu, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A high accuracy-low complexity model for CMOS delays. ISCAS 2000: 455-458
Coauthor Index
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