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Journal Articles
- 2024
[j125]Mike Shuo-Wei Chen
, Visvesh S. Sathe, Massimo Alioto, Jae-Sun Seo, Hidehiro Shiga:
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 59(1): 4-7 (2024)- [j124]Joydeep Basu, Luigi Fassio, Karim Ali, Massimo Alioto:
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation. IEEE J. Solid State Circuits 59(4): 1038-1049 (2024) - 2023
- [j123]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto:
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V. IEEE Access 11: 3584-3596 (2023) - [j122]Makoto Nagata, Massimo Alioto:
Guest Editorial IEEE 2022 European Solid-State Circuits Conference. IEEE J. Solid State Circuits 58(7): 1823-1824 (2023) - [j121]Hui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto:
Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design. IEEE J. Solid State Circuits 58(10): 2919-2930 (2023) - [j120]Orazio Aiello, Paolo Stefano Crovetti, Massimo Alioto:
Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1439-1449 (2023) - [j119]Massimo Alioto:
Opening of the 2023 Editorial Year - This Coda as Prelude of Next TVLSI Cycle With Sustained Growth. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 1-3 (2023) - 2022
- [j118]Thi-Nhan Pham, Quang-Kien Trinh, Ik-Joon Chang, Massimo Alioto:
STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 569-579 (2022) - [j117]Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto:
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security. IEEE J. Solid State Circuits 57(1): 153-166 (2022) - [j116]Massimo Alioto:
Editorial Opening of the 2022 TVLSI Editorial Year - Connecting Trends From Society to VLSI Systems. IEEE Trans. Very Large Scale Integr. Syst. 30(1): 1-4 (2022) - 2021
- [j115]Massimo Alioto:
From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs - Toward a Smarter, Greener World. IEEE Des. Test 38(5): 90-133 (2021) - [j114]Udari De Alwis, Massimo Alioto:
TempDiff: Feature Map-Level CNN Sparsity Enhancement at Near-Zero Memory Overhead via Temporal Difference. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 620-633 (2021) - [j113]Longyang Lin, Saurabh Jain, Massimo Alioto:
Sub-nW Microcontroller With Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor Nodes. IEEE J. Solid State Circuits 56(5): 1618-1629 (2021) - [j112]Sachin Taneja, Massimo Alioto:
PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion. IEEE J. Solid State Circuits 56(7): 2182-2192 (2021) - [j111]Saurabh Jain, Longyang Lin, Massimo Alioto:
±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing. IEEE J. Solid State Circuits 56(10): 2981-2992 (2021) - [j110]Sachin Taneja, Massimo Alioto:
Fully Synthesizable Unified True Random Number Generator and Cryptographic Core. IEEE J. Solid State Circuits 56(10): 3049-3061 (2021) - [j109]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto:
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW. IEEE J. Solid State Circuits 56(10): 3134-3144 (2021) - [j108]Viveka Konandur Rajanna, Massimo Alioto:
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications. IEEE J. Solid State Circuits 56(11): 3533-3543 (2021) - [j107]Pedro Toledo, Paolo Crovetti, Orazio Aiello, Massimo Alioto:
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting. IEEE Trans. Circuits Syst. I Regul. Pap. 68(9): 3693-3706 (2021) - [j106]Luigi Fassio, Francesco Settino, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto:
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1393-1397 (2021) - [j105]Orazio Aiello, Paolo Crovetti, Pedro Toledo, Massimo Alioto:
Rail-to-Rail Dynamic Voltage Comparator Scalable Down to pW-Range Power and 0.15-V Supply. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2675-2679 (2021) - [j104]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto:
A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3038-3042 (2021) - [j103]Pedro Toledo, Paolo Crovetti, Hamilton Klimach, Sergio Bampi, Orazio Aiello, Massimo Alioto:
A 300mV-Supply, Sub-nW-Power Digital-Based Operational Transconductance Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3073-3077 (2021) - [j102]Massimo Alioto:
Opening of the 2021 Editorial Year - Overture for a New Year of Change. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 1-2 (2021) - [j101]Massimo Alioto:
Second Quarter of the 2021 Editorial Year - A Year in Crescendo. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 815-842 (2021) - 2020
- [j100]Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto:
Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision. IEEE Access 8: 18951-18961 (2020) - [j99]Orazio Aiello, Paolo Crovetti, Massimo Alioto:
Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse Modulation. IEEE Access 8: 70890-70899 (2020) - [j98]Longyang Lin, Saurabh Jain, Massimo Alioto:
Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nW. IEEE J. Solid State Circuits 55(4): 967-976 (2020) - [j97]Saurabh Jain, Longyang Lin, Massimo Alioto:
Processor Energy-Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies. IEEE J. Solid State Circuits 55(10): 2670-2679 (2020) - [j96]Jinq Horng Teo, Shuai Cheng, Massimo Alioto:
Low-Energy Voice Activity Detection via Energy-Quality Scaling From Data Conversion to Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1378-1388 (2020) - [j95]Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto:
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation. IEEE Trans. Circuits Syst. 67-II(12): 3427-3431 (2020) - [j94]Massimo Alioto:
Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 1-2 (2020) - [j93]Saurabh Jain, Longyang Lin, Massimo Alioto:
Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 777-790 (2020) - [j92]Massimo Alioto:
Editorial on the Conclusion of the 2020 Editorial Year - The Climactic Finale of a Peculiar Year. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2479-2480 (2020) - 2019
- [j91]Orazio Aiello, Paolo Crovetti, Massimo Alioto:
Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS. IEEE Access 7: 126479-126488 (2019) - [j90]Muhammad Naveed Aman, Sachin Taneja, Biplab Sikdar, Kee Chaing Chua, Massimo Alioto:
Token-Based Security for the Internet of Things With Dynamic Energy-Quality Tradeoff. IEEE Internet Things J. 6(2): 2843-2859 (2019) - [j89]Orazio Aiello, Paolo Crovetti, Longyang Lin, Massimo Alioto:
A pW-Power Hz-Range Oscillator Operating With a 0.3-1.8-V Unregulated Supply. IEEE J. Solid State Circuits 54(5): 1487-1496 (2019) - [j88]Longyang Lin, Saurabh Jain, Massimo Alioto:
Reconfigurable Clock Networks for Wide Voltage Scaling. IEEE J. Solid State Circuits 54(9): 2622-2631 (2019) - [j87]Orazio Aiello, Paolo Stefano Crovetti, Massimo Alioto:
Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2865-2875 (2019) - [j86]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [j85]Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto:
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 964-968 (2019) - [j84]Massimo Alioto:
Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1485 (2019) - 2018
- [j83]Massimo Alioto, Mohsen Shahghasemi:
The Internet of Things on Its Edge: Trends Toward Its Tipping Point. IEEE Consumer Electron. Mag. 7(1): 77-87 (2018) - [j82]Massimo Alioto, Vivek De, Andrea Marongiu:
Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 361-368 (2018) - [j81]Massimo Alioto, Vivek De, Andrea Marongiu:
Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(4): 653-678 (2018) - [j80]Giulia Di Capua, Nuno Horta, Francisco V. Fernández, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi:
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017. Integr. 63: 273-274 (2018) - [j79]Yiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor. IEEE J. Solid State Circuits 53(2): 619-631 (2018) - [j78]Saurabh Jain, Longyang Lin, Massimo Alioto:
Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage Scaling. IEEE J. Solid State Circuits 53(2): 632-641 (2018) - [j77]Sachin Taneja, Anastacia B. Alvarez, Massimo Alioto:
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. IEEE J. Solid State Circuits 53(10): 2828-2839 (2018) - [j76]Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto:
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 1086-1095 (2018) - [j75]Kien Trinh Quang, Sergio Ruocco, Massimo Alioto:
Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1269-1278 (2018) - [j74]Kien Trinh Quang, Sergio Ruocco, Massimo Alioto:
Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3338-3348 (2018) - 2017
- [j73]Massimo Alioto, Giuseppe Scotti, Alessandro Trifiletti:
A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 2073-2085 (2017) - [j72]Massimo Alioto, Edgar Sánchez-Sinencio, Alberto L. Sangiovanni-Vincentelli:
Guest Editorial Special Issue on Circuits and Systems for the Internet of Things - From Sensing to Sensemaking. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2221-2225 (2017) - [j71]Saurabh Jain, Longyang Lin, Massimo Alioto:
Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy Point. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(12): 3115-3125 (2017) - [j70]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j69]Krishnendu Chakrabarty, Massimo Alioto, Rajiv V. Joshi:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2393 (2017) - 2016
- [j68]Kien Trinh Quang, Sergio Ruocco, Massimo Alioto:
Voltage Scaled STT-MRAMs Towards Minimum-Energy Write Access. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 305-318 (2016) - [j67]Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto:
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm. IEEE J. Solid State Circuits 51(3): 763-775 (2016) - [j66]Kien Trinh Quang, Sergio Ruocco, Massimo Alioto:
Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1652-1660 (2016) - [j65]Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
Approximate SRAMs With Dynamic Energy-Quality Management. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2128-2141 (2016) - [j64]Krishnendu Chakrabarty, Massimo Alioto:
Editorial First TVLSI Best AE and Reviewer Awards. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2613 (2016) - 2015
- [j63]Fabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS. IEEE J. Solid State Circuits 50(5): 1310-1323 (2015) - [j62]Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici:
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 458-467 (2015) - [j61]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 835-843 (2015) - [j60]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2035-2043 (2015) - [j59]Wenfeng Zhao, Yajun Ha, Massimo Alioto:
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1390-1401 (2015) - 2014
- [j58]Mihai Tache, Valeriu Beiu, Walid Ibrahim, Fekri Kharbash, Massimo Alioto:
Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates. J. Low Power Electron. 10(1): 137-148 (2014) - [j57]Laura Fick, David Fick, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS. IEEE J. Solid State Circuits 49(11): 2462-2473 (2014) - [j56]Laurent Artola, Guillaume Hubert, Massimo Alioto:
Comparative soft error evaluation of layout cells in FinFET technology. Microelectron. Reliab. 54(9-10): 2300-2305 (2014) - [j55]Massimo Alioto, Simone Bongiovanni, Milena Djukanovic, Giuseppe Scotti, Alessandro Trifiletti:
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 429-442 (2014) - [j54]Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto:
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1593-1605 (2014) - [j53]David Esseni, Manuel Guglielmini, Bernard Kapidani, Tommaso Rollo, Massimo Alioto:
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2488-2498 (2014) - [j52]Massimo Alioto, David Esseni:
Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2499-2512 (2014) - 2013
- [j51]Massimo Alioto, Elio Consoli, Jan M. Rabaey:
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions. IEEE J. Solid State Circuits 48(8): 1921-1932 (2013) - 2012
- [j50]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
From energy-delay metrics to constraints on the design of digital circuits. Int. J. Circuit Theory Appl. 40(8): 815-834 (2012) - [j49]Massimo Alioto:
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 3-29 (2012) - [j48]Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Mitsuhiro Togo, N. Horiguchi, Guido Groeseneken:
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements. IEEE Trans. Circuits Syst. II Express Briefs 59-II(7): 439-442 (2012) - [j47]Gaetano Palumbo, Melita Pennisi, Massimo Alioto:
A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2292-2300 (2012) - [j46]Massimo Alioto:
Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 849-852 (2012) - [j45]Davide Baccarin, David Esseni, Massimo Alioto:
Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1467-1472 (2012) - [j44]Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jérôme Mitard, Liesbeth Witters, Thomas Y. Hoffmann:
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1487-1495 (2012) - 2011
- [j43]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Optimized design of parallel carry-select adders. Integr. 44(1): 62-74 (2011) - [j42]Massimo Alioto:
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools. Microelectron. J. 42(1): 63-73 (2011) - [j41]Fabio Frustaci, Massimo Alioto, Pasquale Corsonello:
Tapered-Vth Approach for Energy-Efficient CMOS Buffers. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(11): 2698-2707 (2011) - [j40]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 725-736 (2011) - [j39]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 737-750 (2011) - [j38]Massimo Alioto:
Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 751-762 (2011) - [j37]Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer, Brice De Jaeger:
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1569-1582 (2011) - 2010
- [j36]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Simple and accurate modeling of the output transition time in nanometer CMOS gates. Int. J. Circuit Theory Appl. 38(10): 995-1012 (2010) - [j35]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
A Variability-Tolerant Feedback Technique for Throughput Maximization of Trbgs with Predefined Entropy. J. Circuits Syst. Comput. 19(4): 879-895 (2010) - [j34]Massimo Alioto, Stéphane Badel, Yusuf Leblebici:
Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff. Microelectron. J. 41(10): 669-679 (2010) - [j33]Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti:
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(2): 355-367 (2010) - [j32]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1273-1286 (2010) - [j31]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1583-1596 (2010) - [j30]Massimo Alioto:
Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1597-1607 (2010) - [j29]Massimo Alioto, Massimo Poli, Santina Rocchi:
Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms. IEEE Trans. Dependable Secur. Comput. 7(3): 226-239 (2010) - [j28]Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi:
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 232-245 (2010) - [j27]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 697-710 (2010) - [j26]Massimo Alioto, Massimo Poli, Santina Rocchi:
A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 711-724 (2010) - 2009
- [j25]Armin Tajalli, Massimo Alioto, Yusuf Leblebici:
Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 127-131 (2009) - [j24]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Analysis and Modeling of Energy Consumption in RLC Tree Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 278 (2009) - 2008
- [j23]Massimo Alioto, Gaetano Palumbo:
Power-Aware Design of Nanometer MCML Tapered Buffers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 16-20 (2008) - 2007
- [j22]Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
Mixed Full Adder topologies for high-performance low-power arithmetic circuits. Microelectron. J. 38(1): 130-139 (2007) - [j21]Tommaso Addabbo, Massimo Alioto, Ada Fort, Antonio Pasini, Santina Rocchi, Valerio Vignoli:
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(4): 816-828 (2007) - [j20]Massimo Alioto, Gaetano Palumbo:
Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers. IEEE Trans. Circuits Syst. II Express Briefs 54-II(6): 484-488 (2007) - [j19]Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Power-Delay-Area-Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(9): 1916-1928 (2007) - 2006
- [j18]Massimo Alioto, Gaetano Palumbo:
Design strategies of cascaded CML gates. IEEE Trans. Circuits Syst. II Express Briefs 53-II(2): 85-89 (2006) - [j17]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
A feedback strategy to improve the entropy of a chaos-based random bit generator. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2): 326-337 (2006) - [j16]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
Low-hardware complexity PRBGs based on a piecewise-linear chaotic map. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 329-333 (2006) - [j15]Massimo Alioto, Rosario Mita, Gaetano Palumbo:
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1165-1169 (2006) - [j14]Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Exploiting Hysteresys in MCML Circuits. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1170-1174 (2006) - [j13]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom Bits. IEEE Trans. Instrum. Meas. 55(5): 1451-1458 (2006) - [j12]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy Consumption in RC Tree Circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 452-461 (2006) - [j11]Massimo Alioto, Gaetano Palumbo:
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1322-1335 (2006) - 2005
- [j10]Massimo Alioto, Gaetano Palumbo:
Power-delay optimization of D-latch/MUX source coupled logic gates. Int. J. Circuit Theory Appl. 33(1): 65-86 (2005) - [j9]Massimo Alioto, Gaetano Palumbo:
Modelling and design considerations on CML gates under high-current effects. Int. J. Circuit Theory Appl. 33(6): 503-518 (2005) - 2004
- [j8]Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli:
An efficient implementation of PRNGs based on the digital sawtooth map. Int. J. Circuit Theory Appl. 32(6): 615-627 (2004) - [j7]Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Modeling and evaluation of positive-feedback source-coupled logic. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(12): 2345-2355 (2004) - [j6]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Evaluation of energy consumption in RC ladder circuits driven by a ramp input. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1094-1107 (2004) - 2003
- [j5]Massimo Alioto, Rosario Mita, Gaetano Palumbo:
Performance evaluation of the low-voltage CML D-latch topology. Integr. 36(4): 191-209 (2003) - 2002
- [j4]Massimo Alioto, Gaetano Palumbo, Salvatore Pennisi:
Modelling of source-coupled logic gates. Int. J. Circuit Theory Appl. 30(4): 459-477 (2002) - [j3]Massimo Alioto, Gaetano Palumbo:
Analysis and comparison on full adder block in submicron technology. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 806-823 (2002) - 2001
- [j2]Massimo Alioto, Gaetano Palumbo:
Power estimation in adiabatic circuits: a simple and accurate model. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 608-615 (2001) - 1999
- [j1]Massimo Alioto, Gaetano Palumbo:
Highly accurate and simple models for CML and ECL gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1369-1375 (1999)
Conference and Workshop Papers
- 2024
- [c181]Animesh Gupta, Japesh Vohra, Massimo Alioto:
CogniVision: A mW Power envelope SoC for Always-on Smart Vision in 40nm. HCS 2024: 1 - [c180]Marco Privitera, Andrea Ballo, Alfio Dario Grasso, Massimo Alioto:
A 15-nA quiescent current capacitor-less LDO for sub-1V μW-powered fully-harvested systems. ISCAS 2024: 1-5 - [c179]Japesh Vohra, Animesh Gupta, Massimo Alioto:
6.3 Imager with In-Sensor Event Detection and Morphological Transformations with 2.9pJ/pixel×frame Object Segmentation FOM for Always-On Surveillance in 40nm. ISSCC 2024: 104-106 - [c178]Ruijie Tao, Zhan Shi, Yidi Jiang, Duc-Tuan Truong, Eng Siong Chng, Massimo Alioto, Haizhou Li:
Multi-Stage Face-Voice Association Learning with Keynote Speaker Diarization. ACM Multimedia 2024: 11342-11347 - [c177]Anil Kumar Gundu, Luigi Fassio, Massimo Alioto:
E-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual-Function Harvesting from Breathing, and No High-Voltage CMOS Process. VLSI Technology and Circuits 2024: 1-2 - [c176]Animesh Gupta, Japesh Vohra, Massimo Alioto:
CogniVision: End-to-End SoC for Always-on Smart Vision with mW Power in 40nm. VLSI Technology and Circuits 2024: 1-2 - [c175]Animesh Gupta, Japesh Vohra, Viveka Konandur Rajanna, Massimo Alioto:
122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c174]Udari De Alwis, Zhongheng Xie, Massimo Alioto:
Temporal Similarity-Based Computation Reduction for Video Transformers in Edge Camera Nodes. AICAS 2023: 1-5 - [c173]Luigi Fassio, Hoang Hong Hanh, Massimo Alioto:
A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500\ \mu \mathrm{m}^{2}$, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nm. A-SSCC 2023: 1-3 - [c172]Karim Ali Ahmed, Ruiyuan Yang, Praveenakumar Shivappa Salamani, Viveka Konandur Rajanna, Massimo Alioto:
Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems. ESSCIRC 2023: 49-52 - [c171]Japesh Vohra, Karim Ali Ahmed, Massimo Alioto:
A 0.4V 12b Comparator Offset Injection Assisted SAR ADC achieving 0.425 fJ/conv-step. ESSCIRC 2023: 137-140 - [c170]Karim Ali Ahmed, Hayate Okuhara, Massimo Alioto:
55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes. ISSCC 2023: 102-103 - [c169]Joydeep Basu, Luigi Fassio, Karim Ali, Massimo Alioto:
Super-Cutoff Analog Building Blocks for pW/Stage Operation and Demonstration of 78-pW Battery-Less Light-Harvested Wake-Up Receiver down to Moonlight. VLSI Technology and Circuits 2023: 1-2 - [c168]Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto:
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm. VLSI Technology and Circuits 2023: 1-2 - [c167]Qiang Fang, Longyang Lin, Hui Zhang, Tianqi Wang, Massimo Alioto:
Voltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level Shuffling. VLSI Technology and Circuits 2023: 1-2 - [c166]Luigi Fassio, Orazio Aiello, Massimo Alioto:
38.4-pW, 0.14-mm2 Body-Driven Temperature-to-Digital Converter and Voltage Reference with 0.6-1.6-V Unregulated Supply for Battery-Less Systems. VLSI Technology and Circuits 2023: 1-2 - [c165]Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto:
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm. VLSI Technology and Circuits 2023: 1-2 - [c164]Hui Zhang, Longyang Lin, Qiang Fang, Udara Samurdhi Harshanga Kalingage, Massimo Alioto:
Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c163]Udari De Alwis, Massimo Alioto:
Temporal Redundancy-Based Computation Reduction for 3D Convolutional Neural Networks. AICAS 2022: 86-89 - [c162]Animesh Gupta, Viveka Konandur Rajanna, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovetti, Massimo Alioto:
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm. CICC 2022: 1-2 - [c161]Massimo Alioto:
From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWs. ESSCIRC 2022: 33-40 - [c160]Orazio Aiello, Massimo Alioto:
Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct Harvesting. ESSCIRC 2022: 381-384 - [c159]Udari De Alwis, Massimo Alioto:
Architecture for 3D Convolutional Neural Networks Based on Temporal Similarity Removal. ICECS 2022 2022: 1-4 - [c158]Qiang Fang, Longyang Lin, Yao Zu Wong, Hui Zhang, Massimo Alioto:
Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching. ISSCC 2022: 1-3 - [c157]Orazio Aiello, Paolo Crovetti, Massimo Alioto:
Conversion Time-Power Tradeoff in Capacitance-to-Digital Converters with Dual-Mode Logic. SBCCI 2022: 1-5 - [c156]Massimo Alioto:
Circuits and Architectures for Next-generation Attentive & Intelligent Systems. VLSI-DAT 2022: 1 - [c155]Karim Ali Ahmed, Longyang Lin, Praveenakumar Shivappa Salamani, Massimo Alioto:
Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested Systems. VLSI Technology and Circuits 2022: 50-51 - [c154]Hui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto:
On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design. VLSI Technology and Circuits 2022: 140-141 - [c153]Viveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto:
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks. VLSI Technology and Circuits 2022: 144-145 - 2021
- [c152]Udari De Alwis, Massimo Alioto:
TempDiff: Temporal Difference-Based Feature Map-Level Sparsity Induction in CNNs with <4% Memory Overhead. AICAS 2021: 1-4 - [c151]Qiang Fang, Massimo Alioto:
Last-Round and Joint First/Last-Round Power Analysis Attacks on PRESENT. AsianHOST 2021: 1-6 - [c150]Shifu Wu, K. De Silva, Snehlata Gutgutia, Bevan M. Baas, Massimo Alioto:
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution. A-SSCC 2021: 1-3 - [c149]Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto:
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1, 459 TOPS/W in 28nm. ESSCIRC 2021: 127-130 - [c148]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto:
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy. ESSCIRC 2021: 343-346 - [c147]Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto:
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1, 459 TOPS/W in 28nm. ESSDERC 2021: 127-130 - [c146]Thi-Nhan Pham, Kien Trinh Quang, Ik-Joon Chang, Massimo Alioto:
STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks. ISCAS 2021: 1-5 - [c145]Orazio Aiello, Paolo Crovetti, Massimo Alioto:
Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation. ISSCC 2021: 74-76 - [c144]Hirofumi Shinohara, Massimo Alioto, Ingrid Verbauwhede:
Session 36 Overview: Hardware Security Digital Architectures and Systems Subcommittee. ISSCC 2021: 496-497 - [c143]Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto:
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security. ISSCC 2021: 498-500 - [c142]Edoardo Charbon, Alicia Klinefelter, Massimo Alioto, Yao-Hong Liu, Munehiko Nagatani, Arijit Raychowdhury, Andreia Cathelin, Boris Murmann:
F4: Electronics for a Quantum World. ISSCC 2021: 525-528 - [c141]Prachi Agarwal, Viveka Konandur Rajanna, Toh Wei Da, Benjamin C. K. Tee, Massimo Alioto:
Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density. VLSI Circuits 2021: 1-2 - [c140]Longyang Lin, Karim Ali Ahmed, Praveenakumar Shivappa Salamani, Massimo Alioto:
Battery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-μW Peak Power Envelope. VLSI Circuits 2021: 1-2 - 2020
- [c139]Jinq Horng Teo, K. Ali, Massimo Alioto:
Voice Activity Detection with >83% Accuracy under SNR down to -3dB at $1.19\mu \mathrm{W}$ and 0.07mm2 in 40nm. A-SSCC 2020: 1-3 - [c138]Saurabh Jain, Longyang Lin, Massimo Alioto:
Automated Design of Reconfigurable Microarchitectures for Accelerators under Wide-Voltage Scaling. ISCAS 2020: 1 - [c137]Sachin Taneja, Massimo Alioto:
Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm. ISCAS 2020: 1-5 - [c136]Massimo Alioto:
Enabling Always-On Sensor Nodes Entirely Powered by Sustainable Energy Sources - Making Our World Smarter and Greener. iSES 2020: xxv-xxxiv - [c135]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto:
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm. VLSI Circuits 2020: 1-2 - [c134]Longyang Lin, Saurabh Jain, Massimo Alioto:
Multi-Sensor Platform with Five-Order-of-Magnitude System Power Adaptation down to 3.1nW and Sustained Operation under Moonlight Harvesting. VLSI Circuits 2020: 1-2 - 2019
- [c133]Saurabh Jain, Longyang Lin, Massimo Alioto:
Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD Scaling. A-SSCC 2019: 125-128 - [c132]Massimo Alioto, Sachin Taneja:
Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper). CICC 2019: 1-8 - [c131]Viveka Konandur Rajanna, Massimo Alioto:
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications. CICC 2019: 1-4 - [c130]Sachin Taneja, Massimo Alioto:
PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion. ESSCIRC 2019: 61-64 - [c129]Orazio Aiello, Paolo Crovetti, Massimo Alioto:
Minimum-Effort Design of Ultra-Low Power Interfaces for the Internet of Things. ICECS 2019: 105-106 - [c128]Marco Lanuzza, Raffaele De Rose, Felice Crupi, Massimo Alioto:
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. ICECS 2019: 158-161 - [c127]Jinq Horng Teo, Shuai Cheng, Massimo Alioto:
Energy-Quality Scalable Analog-to-Digital Conversion and Machine Learning Engine in a 51.9 nJ/frame Voice Activity Detector. ICECS 2019: 174-177 - [c126]Orazio Aiello, Paolo Crovetti, Ayushparth Sharma, Massimo Alioto:
Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort. ICECS 2019: 715-718 - [c125]Orazio Aiello, Paolo Crovetti, Massimo Alioto:
Wake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression Logic. ISCAS 2019: 1-5 - [c124]Massimo Alioto:
Thursday Keynote: Survival of The Fittest: Circuits and Architectures for Computation with Wide Power- Performance Adaptation Beyond Voltage Scaling. SoCC 2019: 1-3 - [c123]Longyang Lin, Saurabh Jain, Massimo Alioto:
Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW. VLSI Circuits 2019: 178- - 2018
- [c122]Shifu Wu, Snehlata Gutgutia, Massimo Alioto, Bevan M. Baas:
Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding. ACSSC 2018: 251-255 - [c121]Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto:
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. DATE 2018: 1151-1154 - [c120]Dingjuan Chua, Jieyi Gao, Massimo Alioto, Yong Ping Xu, Sangit Sasidhar:
Project-Based Learning in Digital Fundamentals Course Using FPGAs. FIE 2018: 1-5 - [c119]Orazio Aiello, Paolo Crovetti, Massimo Alioto:
Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V. ISCAS 2018: 1-5 - [c118]Kien Trinh Quang, Sergio Ruocco, Massimo Alioto:
Novel Time-Based Sensing Scheme for STT-MRAMs. ISCAS 2018: 1-5 - [c117]Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto:
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. ISCAS 2018: 1-5 - [c116]Longyang Lin, Saurabh Jain, Massimo Alioto:
A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing. ISSCC 2018: 44-46 - [c115]Orazio Aiello, Paolo Crovetti, Massimo Alioto:
A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply. VLSI Circuits 2018: 119-120 - 2017
- [c114]Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto:
EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS. A-SSCC 2017: 241-244 - [c113]Sachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto:
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm. A-SSCC 2017: 301-304 - [c112]Massimo Alioto:
Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing. DATE 2017: 127-132 - [c111]Massimo Alioto, Giuseppe Scotti, Alessandro Trifiletti:
Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric. ISCAS 2017: 1-4 - [c110]Darjn Esposito, Antonio G. M. Strollo, Massimo Alioto:
Power-precision scalable latch memories. ISCAS 2017: 1-4 - [c109]Longyang Lin, Kien Trinh Quang, Massimo Alioto:
Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffers. ISCAS 2017: 1-4 - [c108]Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto:
A variation-aware simulation framework for hybrid CMOS/spintronic circuits. ISCAS 2017: 1-4 - [c107]Longyang Lin, Saurabh Jain, Massimo Alioto:
26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage. ISSCC 2017: 440-441 - [c106]Massimo Alioto:
STT-MRAM memories for IoT applications: Challenges and opportunities at circuit level and above. VLSI-DAT 2017: 1 - 2016
- [c105]Somayeh Timarchi, Massimo Alioto:
Ultra-low voltage standard cell libraries: Design strategies and a case study. ICECS 2016: 520-523 - [c104]Saurabh Jain, Massimo Alioto:
A closed-form energy model for VLSI circuits under wide voltage scaling. ICECS 2016: 548-551 - [c103]Kien Trinh Quang, Sergio Ruocco, Massimo Alioto:
Boosted sensing for enhanced read stability in STT-MRAMs. ISCAS 2016: 1238-1241 - [c102]Kien Trinh Quang, Sergio Ruocco, Massimo Alioto:
STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling. ISCAS 2016: 2791-2794 - [c101]Yiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor. ISSCC 2016: 160-162 - [c100]Mahmood Khayatzadeh, Mehdi Saligane, Jingcheng Wang, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI. ISSCC 2016: 310-312 - [c99]Valentino Peluso, Andrea Calimera, Enrico Macii, Massimo Alioto:
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. VLSI-SoC 2016: 1-6 - [c98]Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto:
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping. VLSI-SoC (Selected Papers) 2016: 152-172 - 2015
- [c97]Massimo Alioto, Gaetano Palumbo, Elio Consoli:
PVT variations in differential flip-flops: A comparative analysis. ECCTD 2015: 1-4 - [c96]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Comparative analysis of the robustness of master-slave flip-flops against variations. ICECS 2015: 117-120 - [c95]Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici:
Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. ISCAS 2015: 157-160 - [c94]Kien Trinh Quang, Sergio Ruocco, Massimo Alioto:
Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance. ISCAS 2015: 2313-2316 - [c93]Wenfeng Zhao, Yajun Ha, Massimo Alioto:
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. ISCAS 2015: 2349-2352 - [c92]Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto:
14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm. ISSCC 2015: 1-3 - [c91]Massimo Alioto, Gaetano Palumbo, Elio Consoli:
Variability budgetin pulsed flip-flops. NEWCAS 2015: 1-4 - [c90]Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse. PATMOS 2015: 132-139 - [c89]Mahmood Khayatzadeh, Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS. VLSIC 2015: 270- - 2014
- [c88]Massimo Alioto:
Ultra-low power design approaches for IoT. Hot Chips Symposium 2014: 1-57 - [c87]Fabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS. ISSCC 2014: 244-245 - [c86]Massimo Alioto, Simone Bongiovanni, Giuseppe Scotti, Alessandro Trifiletti:
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher. MIXDES 2014: 241-246 - [c85]David Esseni, Massimo Alioto:
Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits. NEWCAS 2014: 321-324 - [c84]Massimo Alioto, David Esseni:
Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits. SBCCI 2014: 32:1-32:6 - 2013
- [c83]Yen-Po Chen, Yoonmyung Lee, Jae-Yoon Sim, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
45pW ESD clamp circuit for ultra-low power applications. CICC 2013: 1-4 - [c82]Valeriu Beiu, Azam Beg, Walid Ibrahim, Fekri Kharbash, Massimo Alioto:
Enabling sizing for enhancing the static noise margins. ISQED 2013: 278-285 - [c81]Bozena Kaminska, Bernard Courtois, Massimo Alioto:
New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyond. VTS 2013: 1 - 2012
- [c80]Massimo Alioto, Elio Consoli, Jan M. Rabaey:
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS. CICC 2012: 1-4 - [c79]Suyoung Bang, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems. CICC 2012: 1-4 - [c78]Jesse Richmond, Mervin John, Louis P. Alarcón, Wenting Zhou, Wen Li, Tsung-Te Liu, Massimo Alioto, Seth Sanders, Jan M. Rabaey:
Active RFID: Perpetual wireless communications platform for sensors. ESSCIRC 2012: 434-437 - [c77]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
A simple keeper topology to reduce delay variations in nanometer domino logic. ISCAS 2012: 1576-1579 - [c76]Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey:
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. ISSCC 2012: 482-484 - 2011
- [c75]Massimo Alioto:
Impact of NMOS/PMOS imbalance in Ultra-Low Voltage CMOS standard cells. ECCTD 2011: 536-539 - [c74]Fabio Frustaci, Pasquale Corsonello, Massimo Alioto:
Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers. ECCTD 2011: 592-595 - [c73]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
DET FF topologies: A detailed investigation in the energy-delay-area domain. ISCAS 2011: 563-566 - [c72]Milena Djukanovic, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti, Massimo Alioto:
Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations. ISCAS 2011: 2043-2046 - [c71]Fabio Frustaci, Pasquale Corsonello, Massimo Alioto:
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology. ISCAS 2011: 2075-2078 - [c70]Davide Baccarin, David Esseni, Massimo Alioto:
A novel back-biasing low-leakage technique for FinFET forced stacks. ISCAS 2011: 2079-2082 - [c69]Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken, Jérôme Mitard, Liesbeth Witters, Thomas Y. Hoffmann:
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. ISCAS 2011: 2249-2252 - 2010
- [c68]Massimo Alioto, Paolo Bennati, Roberto Giorgi:
Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. ISCAS 2010: 37-40 - [c67]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. ISCAS 2010: 321-324 - [c66]Massimo Alioto:
Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits. ISCAS 2010: 1468-1471 - [c65]Paolo Magnone, Felice Crupi, Massimo Alioto, Ben Kaczer:
Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits. ISCAS 2010: 1699-1702 - [c64]Michael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna, Massimo Alioto:
Design metrics for RTL level estimation of delay variability due to intradie (random) variations. ISCAS 2010: 2498-2501 - [c63]Massimo Alioto:
Analysis of layout density in FinFET standard cells and impact of fin technology. ISCAS 2010: 3204-3207 - [c62]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. PATMOS 2010: 62-72 - 2009
- [c61]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design. ECCTD 2009: 61-64 - [c60]Massimo Alioto, Elio Consoli, Gaetano Palumbo, Melita Pennisi:
Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits. ECCTD 2009: 779-782 - [c59]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Analysis of the impact of random process variations in CMOS tapered buffers. ICECS 2009: 57-60 - [c58]Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti:
Leakage Power Analysis attacks: Theoretical analysis and impact of variations. ICECS 2009: 85-88 - [c57]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Optimum clock slope for flip-flops within a clock domain: Analysis and a case study. ICECS 2009: 275-278 - [c56]Massimo Alioto, Stéphane Badel, Yusuf Leblebici:
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff. ISCAS 2009: 1285-1288 - [c55]Massimo Alioto:
Understanding Loading Effects of RC Uniform Interconnects. ISCAS 2009: 2269-2272 - [c54]Massimo Alioto, Yusuf Leblebici:
Analysis and Design of Ultra-low Power Subthreshold MCML Gates. ISCAS 2009: 2557-2560 - [c53]Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits. ISCAS 2009: 3150-3153 - 2008
- [c52]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Analysis of the impact of process variations on static logic circuits versus fan-in. ICECS 2008: 137-140 - [c51]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy evaluation in RLC tree circuits with exponential input. ICECS 2008: 578-581 - [c50]Massimo Alioto, Gaetano Palumbo:
Power-delay optimization in MCML tapered buffers. ISCAS 2008: 141-144 - [c49]Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer:
Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148 - [c48]Massimo Alioto, Luca Fondelli, Santina Rocchi:
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs. ISCAS 2008: 1572-1575 - [c47]Massimo Alioto, Massimo Poli, Gaetano Palumbo:
Explicit energy evaluation in RLC tree circuits with ramp inputs. ISCAS 2008: 2865-2868 - [c46]Massimo Alioto, Massimo Poli, Santina Rocchi:
A general model for differential power analysis attacks to static logic circuits. ISCAS 2008: 3346-3349 - [c45]Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici:
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS 2008: 21-30 - [c44]Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi:
Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. PATMOS 2008: 31-41 - [c43]Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. PATMOS 2008: 136-145 - 2007
- [c42]Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms. ECCTD 2007: 368-371 - [c41]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy consumption in RLC tree circuits. ECCTD 2007: 771-774 - [c40]Massimo Alioto, Gaetano Palumbo:
Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders. ECCTD 2007: 799-802 - [c39]Massimo Alioto:
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic. ICECS 2007: 431-434 - [c38]Massimo Alioto, Massimo Poli, Gaetano Palumbo:
Efficient and Accurate Models of Output Transition Time in CMOS Logic. ICECS 2007: 1264-1267 - [c37]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map. ISCAS 2007: 693-696 - [c36]Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks. ISCAS 2007: 861-864 - [c35]Massimo Alioto, Gaetano Palumbo:
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. ISCAS 2007: 2998-3001 - [c34]Massimo Alioto, Gaetano Palumbo:
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. ISCAS 2007: 3255-3258 - [c33]Massimo Alioto, Gaetano Palumbo:
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. ISCAS 2007: 3732-3735 - 2006
- [c32]Massimo Alioto, Gaetano Palumbo:
Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders. ICECS 2006: 518-521 - [c31]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
Efficient Post-Processing Module for a Chaos-based Random Bit Generator. ICECS 2006: 1224-1227 - [c30]Massimo Alioto, Rosario Mita, Gaetano Palumbo:
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers. ICECS 2006: 1308-1311 - [c29]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
A technique to design high entropy chaos-based true random bit generators. ISCAS 2006 - [c28]Massimo Alioto, Gaetano Palumbo:
Delay uncertainty due to supply variations in static and dynamic full adders. ISCAS 2006 - [c27]Massimo Alioto, Gaetano Palumbo:
Nanometer MCML gates: models and design considerations. ISCAS 2006 - [c26]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. ISCAS 2006 - [c25]Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Analysis and design of MCML gates with hysteresis. ISCAS 2006 - [c24]Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. PATMOS 2006: 593-602 - [c23]Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli:
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. PATMOS 2006: 624-633 - 2005
- [c22]Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli:
Long period pseudo random bit generators derived from a discretized chaotic map. ISCAS (2) 2005: 892-895 - [c21]Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
An approach to the design of PFSCL gates. ISCAS (3) 2005: 2437-2440 - [c20]Massimo Alioto, Gaetano Palumbo:
Design techniques for low-power cascaded CML gates. ISCAS (5) 2005: 4685-4688 - [c19]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. PATMOS 2005: 355-363 - 2004
- [c18]Tommaso Addabbo, Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli:
Hardware-efficient PRBGs based on 1-D piecewise linear chaotic maps. ICECS 2004: 242-245 - [c17]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
A gate-level strategy to design Carry Select Adders. ISCAS (2) 2004: 465-468 - [c16]Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli:
Positive-Feedback Source-Coupled Logic: a delay model. ISCAS (2) 2004: 641-644 - 2003
- [c15]Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli:
Analysis and design of digital PRNGS based on the discretized sawtooth map. ICECS 2003: 427-430 - [c14]Massimo Alioto, Gaetano Palumbo:
Design of MUX, XOR and D-latch SCL gates. ISCAS (5) 2003: 261-264 - 2002
- [c13]Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
Design guidelines for bipolar frequency dividers. ICECS 2002: 521-524 - [c12]Massimo Alioto, Rosario Mita, Gaetano Palumbo:
Analysis and comparison of low-voltage CML D-latch. ICECS 2002: 737-740 - [c11]Massimo Alioto, Gaetano Palumbo:
Power-delay trade-offs in SCL gates. ISCAS (3) 2002: 249-252 - [c10]Massimo Alioto, Gaetano Palumbo, Massimo Poli:
An Approach to Energy Consumption Modeling in RC Ladder Circuits. PATMOS 2002: 239-246 - [c9]Massimo Alioto, Gaetano Palumbo:
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. PATMOS 2002: 429-437 - 2001
- [c8]Massimo Alioto, Gaetano Palumbo, Salvatore Pennisi:
Delay estimation of SCL gates with output buffer. ICECS 2001: 719-722 - [c7]Massimo Alioto, Gaetano Palumbo:
Optimized design of high fan-in multiplexers using switches with driving capability. ICECS 2001: 737-740 - [c6]Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
CML ring oscillators: oscillation frequency. ISCAS (4) 2001: 112-115 - 2000
- [c5]Massimo Alioto, Gaetano Palumbo:
High-speed bipolar MUX modeling and design. ISCAS 2000: 1-4 - [c4]Massimo Alioto, Gaetano Palumbo:
Evaluation of power consumption in adiabatic circuits. ISCAS 2000: 629-632 - [c3]Massimo Alioto, Gaetano Palumbo:
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. PATMOS 2000: 265-275 - 1998
- [c2]Massimo Alioto, Gaetano Palumbo:
Novel Simple Models Of Cml Propagation Delay. Great Lakes Symposium on VLSI 1998: 270-274 - [c1]Massimo Alioto, Gaetano Palumbo:
Design of CML gate with the best propagation delay. ICECS 1998: 287-290
Editorship
- 2017
- [e2]Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar:
30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017. IEEE 2017, ISBN 978-1-5386-4034-0 [contents] - 2016
- [e1]Karan S. Bhatia, Massimo Alioto, Danella Zhao, Andrew Marshall, Ramalingam Sridhar:
29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016. IEEE 2016, ISBN 978-1-5090-1367-8 [contents]
Informal and Other Publications
- 2018
- [i1]Sachin Taneja, Massimo Alioto:
Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems. CoRR abs/1811.08507 (2018)
Coauthor Index
Paolo Crovetti
aka: Paolo Stefano Crovetti
aka: Paolo Stefano Crovetti
[j80] [j61] [j60] [j54] [j50] [j47] [j43] [j40] [j39] [j36] [j32] [j31] [j27] [j24] [j23] [j22] [j20] [j18] [j15] [j12] [j11] [j10] [j9] [j6] [j5] [j4] [j3] [j2] [j1] [c97] [c96] [c91] [c77] [c76] [c73] [c67] [c62] [c61] [c60] [c59] [c57] [c53] [c52] [c51] [c50] [c47] [c43] [c41] [c40] [c38] [c35] [c34] [c33] [c32] [c30] [c28] [c27] [c26] [c20] [c19] [c17] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
Quang-Kien Trinh
aka: Kien Trinh Quang
aka: Kien Trinh Quang
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