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ORCIDISSCC 2014: San Francisco, CA, USA
- 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014. IEEE 2014, ISBN 978-1-4799-0918-6
- Mark Horowitz:
1.1 Computing's energy problem (and what we can do about it). 10-14 - Ming-Kai Tsai:
1.2 Cloud 2.0 clients and connectivity - Technology and challenges. 15-19 - Erik H. M. Heijne:
1.3 How chips pave the Road to the Higgs particle and the attoworld beyond. 22-28 - Susie J. Wee:
1.4 The next generation of networked experiences. 29-35 - Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Shiva Kotagiri, Lijun Li, Christopher J. Abel, Freeman Zhong:
2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. 38-39 - Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao:
2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS. 40-41 - Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee:
2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS. 42-43 - Jun Won Jung, Behzad Razavi:
2.4 A 25Gb/s 5.8mW CMOS equalizer. 44-45 - Rui Bai, Samuel Palermo, Patrick Yin Chiang:
2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS. 46-47 - Dong Hoon Baek, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface. 48-49 - Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology. 50-51 - Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, Ken Chang:
2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS. 52-53 - Giovanni Marzin, Salvatore Levantino
, Carlo Samori, Andrea L. Lacaita:
2.9 A Background calibration technique to control bandwidth in digital PLLs. 54-55 - Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka:
3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier. 58-59 - Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori:
3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE. 60-61 - Brecht François, Patrick Reynaert:
3.3 A transformer-coupled true-RMS power detector in 40nm CMOS. 62-63 - Ercan Kaymaksut, Patrick Reynaert:
3.4 A dual-mode transformer-based doherty LTE power amplifier in 40nm CMOS. 64-65 - Michiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
3.5 A 1.0-to-2.5GHz beamforming receiver with constant-Gm vector modulator consuming. 66-67 - David Murphy, Hooman Darabi, Hao Xu:
3.6 A noise-cancelling receiver with enhanced resilience to harmonic blockers. 68-69 - In-Young Lee, Sang-Sung Lee, Donggu Im, Seungjin Kim, Jeongki Choi, Sang-Gug Lee, Jinho Ko:
3.7 A fully integrated TV tuner front-end with 3.1dB NF, >+31dBm OIP3, >83dB HRR3/5 and >68dB HRR7. 70-71 - Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski:
3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver. 1-3 - Fujian Lin, Pui-In Mak, Rui Paulo Martins:
3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF. 74-75 - Chen Kong Teh, Atsushi Suzuki, Manabu Yamada, Mototsugu Hamada, Yasuo Unekawa:
4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control. 78-79 - Min Kyu Song, Joseph Sankman, Dongsheng Ma:
4.2 A 6A 40MHz four-phase ZDS hysteretic DC-DC converter with 118mV droop and 230ns response time for a 5A/5ns load transient. 80-81 - Danzhu Lu, Yao Qian, Zhiliang Hong:
4.3 An 87%-peak-efficiency DVS-capable single-inductor 4-output DC-DC buck converter with ripple-based adaptive off-time control. 82-83 - Lin Cheng, Yonggen Liu, Wing-Hung Ki:
4.4 A 10/30MHz Wide-duty-cycle-range buck converter with DDA-based Type-III compensator and fast reference-tracking responses for DVS applications. 84-85 - Kapil Kesarwani, Rahul Sangwan, Jason T. Stauth:
4.5 A 2-phase resonant switched-capacitor converter delivering 4.3W at 0.6W/mm2 with 85% efficiency. 86-87 - Loai G. Salem, Patrick P. Mercier:
4.6 An 85%-efficiency fully integrated 15-ratio recursive switched-capacitor DC-DC converter with 0.1-to-2.2V output voltage range. 88-89 - Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Peter Buchmann, Pier Andrea Francese:
4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS. 90-91 - Ravi Karadi, Gerard Villar Pique:
4.8 3-phase 6/1 switched-capacitor DC-DC boost converter providing 16V at 7mA and 70.3% efficiency in 1.1mm3. 92-93 - Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler:
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. 96-97 - Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich:
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. 98-99 - Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich:
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor. 100-101 - Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang:
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. 102-103 - Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox:
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. 104-105 - Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger:
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. 106-107 - Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De:
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. 108-109 - Alfred Yeung, Hamid Partovi, Qawi Harvard, Luca Ravezzi, John Ngai, Russell Homer, M. Ashcraft, Greg Favor:
5.8 A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology. 110-111 - Nasser A. Kurd, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Manoj Lal, Anant Deval, Jonathan Douglas, Ali M. El-Husseini, Ankireddy Nalamalpu, Timothy M. Wilson, Matthew Merten, Srinivas Chennupaty, Wilfred Gomes, Rajesh Kumar:
5.9 Haswell: A family of IA 22nm processors. 112-113 - Dinesh Maheshwari:
6.1 memory and system architecture for 400Gb/s networking and beyond. 116-117 - Yutaka Miyamoto, Masahito Tomizawa:
6.2 High-capacity scalable optical communication for future Optical Transport Network. 118-119 - Christophe Erdmann, Donnacha Lowney, Adrian Lynam, Aidan Keady, John McGrath, Edward Cullen, Daire Breathnach, Denis Keane, Patrick Lynch, Marites De La Torre, Ronnie De La Torre, Peng Lim, Anthony Collins, Brendan Farley, Liam Madden:
6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters. 120-121 - JungChak Ahn, Kyungho Lee, Yitae Kim, Heegeun Jeong, Bumsuk Kim, Hongki Kim, Jongeun Park, Taesub Jung, Wonje Park, Taeheon Lee, Eunkyung Park, Sangjun Choi, Gyehun Choi, Haeyong Park, Yujung Choi, Seungwook Lee, Yunkyung Kim, Y. J. Jung, Donghyuk Park, Seungjoo Nah, Youngsun Oh, Mihye Kim, Yooseung Lee, Youngwoo Chung, Ihara Hisanori, Joon-Hyuk Im, Daniel-K J Lee, Byunghyun Yim, GiDoo Lee, Heesang Kown, Sungho Choi, Jeonsook Lee, Dongyoung Jang, Youngchan Kim, Tae Chan Kim, Hiroshige Goto, Chi-Young Choi, Duckhyung Lee, Gab-soo Han:
7.1 A 1/4-inch 8Mpixel CMOS image sensor with 3D backside-illuminated 1.12μm pixel with front-side deep-trench isolation and vertical transfer gate. 124-125 - Seokjun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon:
7.2 243.3pJ/pixel bio-inspired time-stamp-based 2D optic flow sensor for artificial compound eyes. 126-127 - Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang:
7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. 128-129 - Sang-Man Han, Taishi Takasawa, Tomoyuki Akahori, Keita Yasutomi, Keiichiro Kagawa, Shoji Kawahito:
7.4 A 413×240-pixel sub-centimeter resolution Time-of-Flight CMOS image sensor with in-pixel background canceling using lateral-electric-field charge modulators. 130-131 - Keita Yasutomi, Takahiro Usui, Sang-Man Han, Taishi Takasawa, Keiichiro Kagawa, Shoji Kawahito:
7.5 A 0.3mm-resolution Time-of-Flight CMOS range imager with column-gating clock-skew calibration. 132-133 - Andrew D. Payne, Andy Daniel, Anik Mehta, Barry Thompson, Cyrus S. Bamji, Dane Snow, Hideaki Oshima, Larry Prather, Mike Fenton, Lou Kordus, Patrick O'Connor, Rich McCauley, Sheethal Nayak, Sunil Acharya, Swati Mehta, Tamer A. Elkhatib, Thomas Meyer, Tod O'Dwyer, Travis Perry, Vei-Han Chan, Vincent Wong, Vishali Mogallapu, William Qian, Zhanping Xu:
7.6 A 512×424 CMOS 3D Time-of-Flight image sensor with multi-frequency photo-demodulation up to 130MHz and 2GS/s ADC. 134-135 - Kyeongha Kwon, Jong-Hyeok Yoon, Soon-Won Kwon, Jaehyeok Yang, Joon-Yeong Lee, Hyosup Won, Hyeon-Min Bae:
8.1 A 6Gb/s transceiver with a nonlinear electronic dispersion compensator for directly modulated distributed-feedback lasers. 138-139 - Hiroshi Morita, Koki Uchino, Eiji Otani, Hiizu Ohtorii, Takeshi Ogura, Kazunao Oniki, Shuichi Oka, Shusaku Yanagawa, Hideyuki Suzuki:
8.2 A 12×5 two-dimensional optical I/O array for 600Gb/s chip-to-chip interconnect in 65nm CMOS. 140-141 - Enrico Mammei, Fabrizio Loi, Francesco Radice, Angelo Dati, Melchiorre Bruccoleri, Matteo Bassi, Andrea Mazzanti:
8.3 A power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS. 142-143 - Tsung-Ching Huang, Tao-Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Fu-Lung Hsueh:
8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS. 144-145 - Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult:
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. 146-147 - Hui Pan, Yuan Yao, Mostafa Hammad, Junhua Tan, Karim Abdelhalim, Evelyn Wenting Wang, Rick C. J. Hsu, Jenny Yu, Joseph N. Y. Aziz, Derek Tam, Ichiro Fujimori:
8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS. 148-149 - Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu:
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. 150-151 - Sui Huang, Jun Cao, Michael M. Green:
8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS. 152-153 - Yukito Tsunoda, Mariko Sugawara, Hideki Oku, Satoshi Ide, Kazuhiro Tanaka:
8.9 A 40Gb/s VCSEL over-driving IC with group-delay-tunable pre-emphasis for optical interconnection. 154-155 - Wee Liang Lien, Tieng Yi Choke, Ying Chow Tan, Ming Kong, Eng-Chuan Low, Dan Ping Li, Liming Jin, Huajiang Zhang, Chin Heng Leow, Soong Lin Chew, Uday Dasgupta, Chee-Hong Yong, Tianbao Gao, Geok Teng Ong, Wee Guan Tan, Weimin Shu, Chee-Lee Heng, Osama Shana'a:
9.1 A self-calibrating NFC SoC with a triple-mode reconfigurable PLL and a single-path PICC-PCD receiver in 0.11μm CMOS. 158-159 - Shuli Geng, Dang Liu, Yanfeng Li, Huiying Zhuo, Woogeun Rhee, Zhihua Wang:
9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications. 160-161 - Fei Chen, Yu Li, Dang Liu, Woogeun Rhee, Jongjin Kim, Dong-Wook Kim, Zhihua Wang:
9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability. 162-163 - Zhicheng Lin, Pui-In Mak, Rui Paulo Martins:
9.4 A 0.5V 1.15mW 0.2mm2 Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components. 164-165 - Yao-Hong Liu, Ao Ba, Johan H. C. van den Heuvel, Kathleen Philips, Guido Dolmans, Harmke de Groot:
9.5 A 1.2nJ/b 2.4GHz receiver with a sliding-IF phase-to-digital converter for wireless personal/body-area networks. 166-167 - Jiao Cheng, Nan Qi, Patrick Yin Chiang, Arun Natarajan:
9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS. 168-169 - Maja Vidojkovic, Xiongchuan Huang, Xiaoyan Wang, Cui Zhou, Ao Ba, Maarten Lont, Yao-Hong Liu, Pieter Harpe, Ming Ding, Ben Busze, Nauman F. Kiyani, Kouichi Kanda, Shoichi Masui, Kathleen Philips, Harmke de Groot:
9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications. 170-171 - Vamshi Krishna Chillara, Yao-Hong Liu, Bindi Wang, Ao Ba, Maja Vidojkovic, Kathleen Philips, Harmke de Groot, Robert Bogdan Staszewski:
9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications. 172-173 - Martin Saint-Laurent, Paul Bassett, Ken Lin, Yuhe Wang, Son Le, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Willie Anderson:
10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications. 176-177 - Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Noriaki Maeda, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores. 178-179 - Alice Wang, Tsung-Yao Lin, Shichin Ouyang, Wei-Hung Huang, Jidong Wang, Shu-Hsin Chang, Sheng-Ping Chen, Chun-Hsiung Hu, J. C. Tai, Koan-Sin Tan, Meng-Nan Tsou, Ming-Hsien Lee, Gordon Gammie, Chi-Wei Yang, Chih-Chieh Yang, Yeh-Chi Chou, Shih-Hung Lin, Wuan Kuo, Chi-Jui Chung, Lee-Kee Yong, Chia-Wei Wang, Kin Hooi Dia, Cheng-Hsing Chien, You-Ming Tsao, N. K. Singh, Rolf Lagerquist, Chih-Cheng Chen, Uming Ko:
10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor. 180-181 - Gyeonghoon Kim, Youchang Kim, Kyuho Jason Lee, Seongwook Park, Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Sungpill Choi, Jinwook Oh, Hoi-Jun Yoo:
10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications. 182-183 - Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi:
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. 184-185 - Christian Bachmann, Gert-Jan van Schaik, Ben Busze, Mario Konijnenburg, Yan Zhang, Jan Stuyt, Maryam Ashouei, Guido Dolmans, Tobias Gemmeke, Harmke de Groot:
10.6 A 0.74V 200μW multi-standard transceiver digital baseband in 40nm LP-CMOS for 2.4GHz Bluetooth Smart / ZigBee / IEEE 802.15.6 personal area networks. 186-187 - Benedikt Noethen, Oliver Arnold, Esther P. Adeva, Tobias Seifert, Erik Fischer, Steffen Kunze, Emil Matús, Gerhard P. Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, J.-U. Schlusler, Stefan Scholze, Dennis Walter, René Schüffny:
10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. 188-189 - Michael Breschel, Peter Almers, Fredrik Angsmark, Alberth Arvidsson, Harald Bauer, Kees van Berkel, Joaquin Canovas, Minh Do, Anders Ekelund, Torsten Larsson, Bo Lincoln, Magnus Malmberg, Masao Naruse, Masashi Onishi, Christer Östberg, Jean-Paul Smeets, Mario Vergara Escobar, Juergen Voelkl, Emma Wittenmark:
10.8 A multi-standard 2G/3G/4G Cellular modem supporting carrier aggregation in 28nm CMOS. 190-191 - Pieter Harpe, Eugenio Cantatore, Arthur H. M. van Roermund:
11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR. 194-195 - Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, Hsin-Shu Chen:
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. 196-197 - Frank M. Yaul, Anantha P. Chandrakasan:
11.3 A 10b 0.6nW SAR ADC with data-dependent energy savings using LSB-first successive approximation. 198-199 - Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult:
11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS. 200-201 - Yong Lim, Michael P. Flynn:
11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers. 202-203 - Dong-Young Chang, Carlos E. Muñoz, Denis C. Daly, Soon-Kyun Shin, Kevin Guay, Thomas Thurston, Hae-Seung Lee, Kush Gulati, Matthew Z. Straayer:
11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. 204-205 - Hans Van de Vel, Joost Briaire, Corné Bastiaansen, Pieter C. W. van Beek, Govert Geelen, Harrie Gunnink, Yongjie Jin, Mustafa Kaba, Kerong Luo, Edward J. F. Paulus, Bang Pham, William Relyveld, Peter Zijlstra:
11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS with. 206-207 - Richard J. Przybyla, Hao-Yen Tang, Stefon E. Shelton, David A. Horsley, Bernhard E. Boser:
12.1 3D ultrasonic gesture recognition. 210-211 - Yingzhe Hu, Liechao Huang, Warren Rieutort-Louis, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma:
12.2 3D gesture-sensing system for interactive displays based on extended-range capacitive sensing. 212-213 - Mutsumi Hamaguchi, Akira Nagao, Masayuki Miyamoto:
12.3 A 240Hz-reporting-rate 143×81 mutual-capacitance touch-sensing analog front-end IC with 37dB SNR for 1mm-diameter stylus. 214-215 - Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata:
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. 216-217 - Hongjae Jang, Hyungcheol Shin, Seunghoon Ko, Ilhyun Yun, Kwyro Lee:
12.5 2D Coded-aperture-based ultra-compact capacitive touch-screen controller with 40 reconfigurable channels. 218-219 - Hyunsoo Ha, Dennis Sylvester, David T. Blaauw, Jae-Yoon Sim:
12.6 A 160nW 63.9fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes. 220-221 - Kamran Souri, Youngcheol Chae, Frank Thus, Kofi A. A. Makinwa:
12.7 A 0.85V 600nW all-CMOS temperature sensor with an inaccuracy of ±0.4°C (3σ) from -40 to 125°C. 222-223 - Ali Heidary, Guijie Wang, Kofi A. A. Makinwa, Gerard C. M. Meijer:
12.8 A BJT-based CMOS temperature sensor with a 3.6pJ·K2-resolution FoM. 224-225 - Samira Zali Asl, Shouvik Mukherjee, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, P. Galle, Meghan Phadke, Charles Grosjean, Jim Salvia, Haechang Lee, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon:
12.9 A 1.55×0.85mm2 3ppm 1.0μA 32.768kHz MEMS-based oscillator. 226-227 - Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang:
13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. 230-231 - Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang, Jaeho Park, Sunghyun Park, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyu-Hong Kim, Jintae Kim, Young-Keun Lee, Kee Sup Kim, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi:
13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications. 232-233 - Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii:
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. 234-235 - Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa, Kenji Hashimoto, Ichiro Wakiyama, Shinji Miyano, Takehiko Hojo:
13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current. 236-237 - Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang:
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. 238-239 - Koji Nii, Teruhiko Amano, Naoya Watanabe, Minoru Yamawaki, Kenji Yoshinaga, Mihoko Wada, Isamu Hayashi:
13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. 240-241 - Bharan Giridhar, Nathaniel Ross Pinckney, Dennis Sylvester, David T. Blaauw:
13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS. 242-243 - Fabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS. 244-245 - Dixian Zhao, Patrick Reynaert:
14.1 A 0.9V 20.9dBm 22.3%-PAE E-band power amplifier with broadband parallel-series power combiner in 40nm CMOS. 248-249 - Vito Giannini, Davide Guermandi, Qixian Shi, Kristof Vaesen, Bertrand Parvais, Wim Van Thillo, André Bourdoux, Charlotte Soens, Jan Craninckx, Piet Wambacq:
14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS. 250-251 - Shailesh Kulkarni, Patrick Reynaert:
14.3 A Push-Pull mm-Wave power amplifier with. 252-253 - Seyed Yahya Mortazavi, Kwang-Jin Koh:
14.4 A Class F-1/F 24-to-31GHz power amplifier with 40.7% peak PAE, 15dBm OP1dB, and 50mW Psat in 0.13μm SiGe BiCMOS. 254-255 - Ullrich R. Pfeiffer, Yan Zhao, Janus Grzyb, Richard Al Hadi, Neelanjan Sarmah, Wolfgang Forster, Holger Rücker, Bernd Heinemann:
14.5 A 0.53THz reconfigurable source array with up to 1mW radiated power for terahertz imaging applications in 0.13μm SiGe BiCMOS. 256-257 - Yahya M. Tousi, Ehsan Afshari:
14.6 A scalable THz 2D phased array with +17dBm of EIRP at 338GHz in 65nm bulk CMOS. 258-259 - Pei-Yuan Chiang, Zheng Wang, Omeed Momeni, Payam Heydari:
14.7 A 300GHz frequency synthesizer with 7.9% locking range in 90nm SiGe BiCMOS. 260-261 - Muhammad Adnan, Ehsan Afshari:
14.8 A 247-to-263.5GHz VCO with 2.6mW peak output power and 1.14% DC-to-RF efficiency in 65nm Bulk CMOS. 262-263 - Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. 266-267 - Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park:
15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. 268-269 - Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang:
15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO. 270-271 - Ahmed Elkholy, Amr Elshazly, Saurabh Saxena, Guanghua Shu, Pavan Kumar Hanumolu:
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. 272-273 - Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De:
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. 276-277 - Sanu K. Mathew, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, Rachael J. Parker, Ram K. Krishnamurthy, Vivek De:
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. 278-279 - Kaiyuan Yang, David Fick, Michael B. Henry, Yoonmyung Lee, David T. Blaauw, Dennis Sylvester:
16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS. 280-281 - Teng Yang, Seongjong Kim, Peter R. Kinget, Mingoo Seok:
16.4 0.6-to-1.0V 279μm2, 0.92μW temperature sensor with less than +3.2/-3.4°C error for on-chip dense thermal monitoring. 282-283 - Haifeng Ma, Ronan A. R. van der Zee, Bram Nauta:
17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation. 286-287 - Zushu Yan, Pui-In Mak, Man-Kay Law, Rui Paulo Martins, Franco Maloberti:
17.2 A 0.0013mm2 3.6μW nested-current-mirror single-stage amplifier driving 0.15-to-15nF capacitive loads with >62° phase margin. 288-289 - Wanyuan Qu, Jong-Pil Im, Hyun-Sik Kim, Gyu-Hyeong Cho:
17.3 A 0.9V 6.3μW multistage amplifier driving 500pF capacitive load with 1.34MHz GBW. 290-291 - Giorgio Ferrari, Davide Bianchi, Angelo Rottigni, Marco Sampietro:
17.4 CMOS impedance analyzer for nanosamples investigation operating up to 150MHz with Sub-aF resolution. 292-293 - Fabio Sebastiano, Federico Butti, Robert H. M. van Veldhoven, Paolo Bruschi:
17.5 A 0.07mm2 2-channel instrumentation amplifier with 0.1% gain matching in 0.16μm CMOS. 294-295 - Patrik Amò, Matthieu Thomas, Vladimir Molata, Tomás Jerábek:
17.6 Envelope modulator for multimode transmitters with AC-coupled multilevel regulators. 296-297 - Keng-Jan Hsiao:
17.7 A 1.89nW/0.15V self-charged XO for real-time clock generation. 298-299 - Danielle Griffith, Per Torstein Røine, James Murdock, Ryan Smith:
17.8 A 190nW 33kHz RC oscillator with ±0.21% temperature stability and 4ppm long-term stability. 300-301 - Jayanth Kuppambatti, Baradwaj Vigraham, Peter R. Kinget:
17.9 A 0.6V 70MHz 4th-order continuous-time Butterworth filter with 55.8dB SNR, 60dB THD at +2.8dBm output signal power. 302-303 - Wei-Chung Chen, Yi-Ping Su, Yu-Huei Lee, Chin-Long Wey, Ke-Horng Chen:
17.10 0.65V-input-voltage 0.6V-output-voltage 30ppm/°C low-dropout regulator with embedded voltage reference for low-power biomedical systems. 304-305 - Yan Lu, Wing-Hung Ki, C. Patrick Yue:
17.11 A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems. 306-307 - Amre El-Hoiydi, Francois Callias, Yves Oesch, Christoph Kuratli, Robert Kvacek:
18.1 A 1V 3mA 2.4GHz wireless digital audio communication SoC for hearing-aid applications in 0.18μm CMOS. 310-311 - Marcus Yip, Rui Jin, Hideko Heidi Nakajima, Konstantina M. Stankovic, Anantha P. Chandrakasan:
18.2 A fully-implantable cochlear implant SoC with piezoelectric middle-ear sensor and energy-efficient stimulation in 0.18μm HVCMOS. 312-313 - Nick Van Helleputte, Mario Konijnenburg, Hyejung Kim, Julia Pettine, Dong-Woo Jee, Arjan Breeschoten, Alonso Morgado, Tom Torfs, Harmke de Groot, Chris Van Hoof, Refet Firat Yazicioglu:
18.3 A multi-parameter signal-acquisition SoC for connected personal health applications. 314-315 - Sunjoo Hong, Kwonjoon Lee, Unsoo Ha, Hyunki Kim, Yongsu Lee, Youchang Kim, Hoi-Jun Yoo:
18.4 A 4.9mΩ-sensitivity mobile electrical impedance tomography IC for early breast-cancer detection system. 316-317 - Taehwan Roh, Kiseok Song, Hyunwoo Cho, Dongjoo Shin, Unsoo Ha, Kwonjoon Lee, Hoi-Jun Yoo:
18.5 A 2.14mW EEG neuro-feedback processor with transcranial electrical stimulation for mental-health management. 318-319 - Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-Lung Lin, Ho-Ming Tong:
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. 320-321 - Po-Hung Kuo, Jian-Yu Hsieh, Yi-Chun Huang, Yu-Jie Huang, Rong-Da Tsai, Tao Wang, Hung-Wei Chiu, Shey-Shi Lu:
18.7 A remotely controlled locomotive IC driven by electrolytic bubbles and wireless powering. 322-323 - Mark Helm, Jae-Kwan Park, Ali Ghalam, Jason Guo, Chang-Wan Ha, Cairong Hu, Heonwook Kim, Kalyan Kavalipurapu, Eric Lee, Ali Mohammadzadeh, Dan Nguyen, Vipul Patel, Ted Pekny, Bill Saiki, Daesik Song, Jeff Tsai, Vimon Viajedor, Luyen Vu, Tinwai Wong, Jung Hee Yun, Ramin Ghodsi, Andrea D'Alessandro, Domenico Di Cicco, Violante Moschiano:
19.1 A 128Gb MLC NAND-Flash device using 16nm planar cell. 326-327 - Sungdae Choi, Duckju Kim, Sungwook Choi, Byungryul Kim, Sunghyun Jung, Kichang Chun, Namkyeong Kim, Wanseob Lee, Taisik Shin, Hyunjong Jin, Hyunchul Cho, Sunghoon Ahn, Yonghwan Hong, Ingon Yang, Byoungyoung Kim, Pil-Seon Yoo, Youngdon Jung, Jinwoo Lee, Jae-Hyeon Shin, Taeyun Kim, Kunwoo Park, Jinwoong Kim:
19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology. 328-329 - Konosuke Watanabe, Kenichiro Yoshii, Nobuhiro Kondo, Ken-ichi Maeda, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki:
19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. 330-331 - Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chorng-Jung Lin, Ku-Feng Lin, Yu-Der Chih, Sreedhar Natarajan, Tsung-Yung Jonathan Chang:
19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme. 332-333 - Ki-Tae Park, Jin-Man Han, Dae-Han Kim, Sangwan Nam, Kihwan Choi, Minsu Kim, Pansuk Kwak, Doosub Lee, Yoon-Hee Choi, Kyung-Min Kang, Myung-Hoon Choi, Dong-Hun Kwak, Hyun Wook Park, Sang-Won Shim, Hyun-Jun Yoon, Doo-Hyun Kim, Sang-Won Park, Kangbin Lee, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jeunghwan Park, Jinho Ryu, Donghyun Kim, Kyunghwa Yun, Joonsoo Kwon, Seunghoon Shin, Dongkyu Youn, Won-Tae Kim, Taehyun Kim, Sung-Jun Kim, Sungwhan Seo, Hyunggon Kim, Dae-Seok Byeon, Hyang-Ja Yang, Moosung Kim, Myong-Seok Kim, Jinseon Yeon, Jae-hoon Jang, Han-Soo Kim, Woonkyung Lee, Duheon Song, Sungsoo Lee, Kyehyun Kyung, Jeong-Hyuk Choi:
19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming. 334-335 - Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi:
19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers. 336-337 - Rich Fackenthal, Makoto Kitagawa, Wataru Otsuka, Kirk Prall, Duane Mills, Keiichi Tsutsui, Johnny Javanifard, Kerry Tedrow, Tomohito Tsushima, Yoshiyuki Shibahara, Glen Hush:
19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology. 338-339 - Tom Redant, Tuba Ayhan, Nico De Clercq, Marian Verhelst, Patrick Reynaert, Wim Dehaene:
20.1 A 40nm CMOS receiver for 60GHz discrete-carrier indoor localization achieving mm-precision at 4m range. 342-343 - Michael Boers, Iason Vassiliou, Saikat Sarkar, Sean T. Nicolson, Ehsan Adabi, Bagher Afshar, Bevin G. Perumana, Theodoros Chalvatzis, Spyros Kavadias, Padmanava Sen, Wei Liat Chan, Alvin Hsing-Ting Yu, Ali Parsa, Med Nariman, Seunghwan Yoon, Alfred Grau Besoli, Chryssoula A. Kyriazidou, Gerasimos Zochios, Namik Kocaman, Adesh Garg, Hans Eberhart, Phil Yang, Hongyu Xie, Hea Joung Kim, Alireza Tarighat Mehrabani, David Garrett, Andrew J. Blanksby, Mong Kuan Wong, Durai Pandian Thirupathi, Siukai Mak, Radha Srinivasan, Amir Ibrahim, Ersin Sengul, Vincent Roussel, Po-Chao Huang, Tsuifang Yeh, Murat Mese, Jesus A. Castaneda, Brima Ibrahim, Tirdad Sowlati, Maryam Rofougaran, Ahmadreza Rofougaran:
20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity. 344-345 - Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa:
20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. 346-347 - Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura:
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. 348-349 - Ming He, Renaldi Winoto, Xiang Gao, Wayne Loeb, David Signoff, Wai Lau, Yuan Lu, Donghong Cui, Kun-Seok Lee, Sai-Wang Tam, Philip Godoy, Yung Chen, Sanghoon Joo, Changhui Hu, Arvind Anumula Paramanandam, Xiaoyue Wang, Chi-Hung Lin, Li Lin:
20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput. 350-351 - Jin Zhou, Peter R. Kinget, Harish Krishnaswamy:
20.6 A blocker-resilient wideband receiver with low-noise active two-point cancellation of >0dBm TX leakage and TX noise in RX band for FDD/Co-existence. 352-353 - Ming-Da Tsai, Chih-Fan Liao, Chi-Yun Wang, Yi-Bin Lee, Bosen Tzeng, Guang-Kaai Dehng:
20.7 A multi-band inductor-less SAW-less 2G/3G-TD-SCDMA cellular receiver in 40nm CMOS. 354-355 - Joung Won Park, Behzad Razavi:
20.8 A 20mW GSM/WCDMA receiver with RF channel selection. 356-357 - Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC. 360-361 - Po-Chun Huang, Wei-Sung Chang, Tai-Cheng Lee:
21.2 A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise. 362-363 - Taegeun Yoo, Yun-Hwan Jung, Hong Chang Yeoh, Yong Sin Kim, Sung-Mo Kang, Kwang-Hyun Baek:
21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS. 364-365 - Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk, Piet Wambacq:
21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS. 366-367 - Mazhareddin Taghivand, Kamal Aggarwal, Ada S. Y. Poon:
21.5 A 3.24-to-8.45GHz low-phase-noise mode-switching oscillator. 368-369 - Luca Fanori, Thomas Mattsson, Pietro Andreani:
21.6 A 2.4-to-5.3GHz dual-core CMOS VCO with concentric 8-shaped coils. 370-371 - Keping Wang, Jabeom Koo, Richard C. Ruby, Brian P. Otis:
21.7 A 1.8mW PLL-free channelized 2.4GHz ZigBee receiver utilizing fixed-LO temperature-compensated FBAR resonator. 372-373 - Ahmad Mirzaei, Mohyee Mikhemar, Hooman Darabi:
21.8 A pulling mitigation technique for direct-conversion transmitters. 374-375 - Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici:
22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. 378-379 - Vanessa Hung-Chu Chen, Lawrence T. Pileggi:
22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI. 380-381 - Stéphane Le Tual, Pratap Narayan Singh, Christophe Curis, Pierre Dautriche:
22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology. 382-383 - Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee:
22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration. 384-385 - Nicolas Le Dortz, Jean-Pierre Blanc, Thierry Simon, Sarah Verhaeren, Emmanuel Rouat, Pascal Urard, Stéphane Le Tual, Dimitri Goguet, Caroline Lelandais-Perrault, Philippe Bénabès:
22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS. 386-388 - Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, Akira Matsuzawa:
22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers. 388-389 - Brian Brandt, Daniel R. McMahill, Miaochen Wu, Paul Kalthoff, Ajay Kuckreja, Geir S. Ostrem:
22.7 A 14b 4.6GS/s RF DAC in 0.18μm CMOS for cable head-end systems. 390-391 - Jungmoon Kim, Philip K. T. Mok, Chulwoo Kim:
23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement. 394-395 - Saurav Bandyopadhyay, Patrick P. Mercier, Andrew C. Lysaght, Konstantina M. Stankovic, Anantha P. Chandrakasan:
23.2 A 1.1nW energy harvesting system with 544pW quiescent power for next-generation implants. 396-397 - Wanyeong Jung, Sechang Oh, Suyoung Bang, Yoonmyung Lee, Dennis Sylvester, David T. Blaauw:
23.3 A 3nW fully integrated energy harvester based on self-oscillating switched-capacitor DC-DC converter. 398-399 - Suhwan Kim, Gabriel A. Rincón-Mora:
23.4 Dual-source single-inductor 0.18μm CMOS charger-supply with nested hysteretic and adaptive on-time PWM control. 400-401 - Young-Sub Yuk, Seungchul Jung, Hui-Dong Gwon, Sukhwan Choi, Si-Duk Sung, Tae-Hwang Kong, Sung-Wan Hong, Jun-Han Choi, Min-Yong Jeong, Jong-Pil Im, Seung-Tak Ryu, Gyu-Hyeong Cho:
23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface. 402-403 - Sandip Uprety, Hoi Lee:
23.6 A 43V 400mW-to-21W global-search-based photovoltaic energy harvester with 350μs transient time, 99.9% MPPT efficiency, and 94% power efficiency. 404-405 - Minseob Shim, Jungmoon Kim, Junwon Jung, Chulwoo Kim:
23.7 Self-powered 30μW-to-10mW Piezoelectric energy-harvesting system with 9.09ms/V maximum power point tracking time. 406-407 - Yousr Ismail, Haechang Lee, Sudhakar Pamarti, Chih-Kong Ken Yang:
23.8 A 34V charge pump in 65nm bulk CMOS technology. 408-409 - Rikky Muller, Hanh-Phuc Le, Wen Li, Peter Ledochowitsch, Simone Gambini, Toni Björninen, Aaron C. Koralek, Jose M. Carmena, Michel M. Maharbiz, Elad Alon, Jan M. Rabaey:
24.1 A miniaturized 64-channel 225μW wireless electrocorticographic neural sensor. 412-413 - Hyung-Min Lee, Ki-Yong Kwon, Wen Li, Maysam Ghovanloo:
24.2 A power-efficient switched-capacitor stimulating system for electrical/optical deep-brain stimulation. 414-415 - Dongsuk Jeon, Yen-Po Chen, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Grant H. Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis. 416-417 - Long Yan, Pieter Harpe, Masato Osawa, Yasunari Harada, Kosei Tamiya, Chris Van Hoof, Refet Firat Yazicioglu:
24.4 A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. 418-419 - Kea-Tiong Tang, Shih-Wen Chiu, Chung-Hung Shih, Chia-Ling Chang, Chia-Min Yang, Da-Jeng Yao, Jen-Huo Wang, Chien-Ming Huang, Hsin Chen, Kwuang-Han Chang, Chih-Cheng Hsieh, Ting-Hau Chang, Meng-Fan Chang, Chia-Min Wang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu:
24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia. 420-421 - Pramod Murali, Igor I. Izyumin, Daniel Cohen, Jun-Chau Chien, Ali M. Niknejad, Bernhard E. Boser:
24.6 A CMOS micro-flow cytometer for magnetic label detection and classification. 422-423 - Jiawei Xu, Ben Busze, Hyejung Kim, Kofi A. A. Makinwa, Chris Van Hoof, Refet Firat Yazicioglu:
24.7 A 60nV/√Hz 15-channel digital active electrode system for portable biopotential signal acquisition. 424-425 - Ji-Yong Um, Eun-Woo Song, Yoon-Jee Kim, Seong-Eun Cho, Min-Kyun Chae, Jongkeun Song, Bae-Hyung Kim, Seunghun Lee, Jihoon Bang, Youngil Kim, Kyungil Cho, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area. 426-427 - Tae-Young Oh, Hoeju Chung, Young-Chul Cho, Jang-Woo Ryu, Kiwon Lee, Changyoung Lee, Jin-Il Lee, Hyoung-Joo Kim, Min-Soo Jang, Gong-Heum Han, Kihan Kim, Daesik Moon, Seung-Jun Bae, Joon-Young Park, Kyung-Soo Ha, Jaewoong Lee, Su-Yeon Doo, Jung-Bum Shin, Chang-Ho Shin, Kiseok Oh, Doo-Hee Hwang, Taeseong Jang, Chulsung Park, Kwang-Il Park, Jung-Bae Lee, Joo-Sun Choi:
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation. 430-431 - Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Hongjung Kim, Ju Young Kim, Young Jun Park, Jae Hwan Kim, Dae Suk Kim, Heat Bit Park, Jin Wook Shin, Jang Hwan Cho, Ki Hun Kwon, Min Jeong Kim, Jaejin Lee, Kunwoo Park, Byong-Tae Chung, Sung-Joo Hong:
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV. 432-433 - Hyun-Woo Lee, Junyoung Song, Sangah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jin-Youp Cha, Jaeil Kim, Hoon Choi, Seung-Wook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jin-Hee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byong-Tae Chung, Sung-Joo Hong:
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. 434-435 - Vishnu Balan, Olakanmi Oluwole, Gregory Kodani, Charlie Zhong, Sanjeev Maheswari, Ratnakar Dadi, Arif Amin, Gautam Bhatia, Peter Mills, Ahmed Ragab, Ming-Ju Edward Lee:
26.1 A 130mW 20Gb/s half-duplex serial link in 28nm CMOS. 438-439 - James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Tawfiq Musah, Gökçe Keskin, Sudip Shekhar, Joseph T. Kennedy, Shreyas Sen, Rajesh Inti, Mozhgan Mansuri, Michael Leddige, Bryce Horine, Clark Roberts, Randy Mooney, Bryan Casper:
26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS. 440-441 - Anant Singh, Dario Albino Carnelli, Altay Falay, Klaas L. Hofstra, Fabio Licciardello, Kia Salimi, Hugo Santos, Amin Shokrollahi, Roger Ulrich, Christoph Walter, John Fox, Peter Hunt, John Keay, Richard Simpson, Andrew Stewart, Giuseppe Surace, Harm S. Cronie:
26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology. 442-443 - Tzu-Chien Hsueh, Ganesh Balamurugan, James E. Jaussi, Sami Hyvonen, Joseph T. Kennedy, Gökçe Keskin, Tawfiq Musah, Sudip Shekhar, Rajesh Inti, Shreyas Sen, Mozhgan Mansuri, Clark Roberts, Bryan Casper:
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS. 444-445 - Young-Hoon Song, Hae-Woong Yang, Hao Li, Patrick Yin Chiang, Samuel Palermo:
26.5 An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS. 446-447 - Shang-Ping Chen, Chih-Chien Hung, Qui-Ting Chen, Sheng-Ming Chang, Ming-Shi Liou, Bo-Wei Hsieh, Hsiang-I Huang, Brian Liu, Yan-Bin Luo:
26.6 A 2.667Gb/s DDR3 memory interface with asymmetric ODT on wirebond package and single-side-mounted PCB. 448-449 - Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack:
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. 452-453 - Michael Price, James R. Glass, Anantha P. Chandrakasan:
27.2 A 6mW 5K-Word real-time speech recognizer using WFST models. 454-455 - Nele Reynders, Wim Dehaene:
27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS. 456-457 - Omid Abari, Ezzeldin Hamed, Haitham Hassanieh, Abhinav Agarwal, Dina Katabi, Anantha P. Chandrakasan, Vladimir Stojanovic:
27.4 A 0.75-million-point fourier-transform chip for frequency-sparse signals. 458-459 - Cheng C. Wang, Fang-Li Yuan, Tsung-Han Yu, Dejan Markovic:
27.5 A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing. 460-461 - Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou:
27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder. 462-463 - Matthew Weiner, Milovan Blagojevic, Sergey Skotnikov, Andreas Burg, Philippe Flatresse, Borivoje Nikolic:
27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI. 464-465 - Yejoong Kim, Wanyeong Jung, Inhee Lee, Qing Dong, Michael B. Henry, Dennis Sylvester, David T. Blaauw:
27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications. 466-467 - Mikko Englund, Kim B. Östman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Kimmo Koli, Jussi Ryynänen:
28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS. 470-471 - YuLi Hsueh, Lan-Chou Cho, Chih-Hsien Shen, Yi-Chien Tsai, Tzu-Chan Chueh, Tao-Yao Chang, Jui-Lin Hsu, Jing-Hong Conan Zhan:
28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and. 472-473 - Yu-Hsien Kao, Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ping-Hsuan Hsieh, Ta-Shun Chu:
28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS. 474-475 - Radha S. Rajan, Shanthi Pavan:
29.1 A 5mW CT ΔΣ ADC with embedded 2nd-order active filter and VGA achieving 82dB DR in 2MHz BW. 478-479 - Yunzhi Dong, Richard Schreier, Wenhua Yang, Sudhir Korrapati, Ali Sheikholeslami:
29.2 A 235mW CT 0-3 MASH ADC achieving -167dBFS/Hz NSD with 53MHz BW. 480-481 - Ahmed M. Abdelatty Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, David Jarman, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Ho-Young Lee:
29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration. 482-483 - Kris Myny, Steve Smout, Maarten Rockele, Ajay Bhoolokam, Tung Huei Ke, Soeren Steudel, Koji Obata, B. M. Marín-Santibáñez, Duy-Vu Pham, Arne Hoppe, Aashini Gulati, F. Rodríguez González, Brian Cobb, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans:
30.1 8b Thin-film microprocessor using a hybrid oxide-organic complementary technology with inkjet-printed P2ROM memory. 486-487 - Jan Genoe, Koji Obata, Marc Ameys, Kris Myny, Tung Huei Ke, Manoj Nag, Soeren Steudel, Sarah Schols, Joris Maas, Ashutosh Tripathi, Jan-Laurens P. J. van der Steen, Tim J. Ellis, Gerwin H. Gelinck, Paul Heremans:
30.2 Digital PWM-driven AMOLED display on flex reducing static power consumption. 488-489 - Hiroshi Fuketa, Kazuaki Yoshioka, Tomoyuki Yokota, Wakako Yukita, Mari Koizumi, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance. 490-491 - Vincenzo Fiore, Egidio Ragonese, Sahel Abdinia, Stéphanie Jacob, Isabelle Chartier, Romain Coppard, Arthur H. M. van Roermund, Eugenio Cantatore, Giuseppe Palmisano:
30.4 A 13.56MHz RFID tag with active envelope detection in an organic complementary TFT technology. 492-493 - Shuichi Nagai, Yasuhiro Yamada, Noboru Negoro, Hiroyuki Handa, Yuji Kudoh, Hiroaki Ueno, Masahiro Ishida, Nobuyuki Otuska, Daisuke Ueda:
30.5 A GaN 3×3 matrix converter chipset with Drive-by-Microwave technologies. 494-495 - Atsutake Kosuge, Shu Ishizuka, Lechang Liu, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%. 496-497 - Junghyup Lee, Vishal Vinayak Kulkarni, Ho Chee Keong, Jia Hao Cheong, Peng Li, Jun Zhou, Wei-Da Toh, Xin Zhang, Yuan Gao, Kuang-Wei Cheng, Xin Liu, Minkyu Je:
30.7 A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications. 498-499 - Timothy D. Gathman, Kristian N. Madsen, James Chingwei Li, Thomas C. Oh, James F. Buckwalter:
30.8 A 30GS/s double-switching track-and-hold amplifier with 19dBm IIP3 in an InP BiCMOS technology. 1-3 - Takeshi Aoki, Yuki Okamoto, Takashi Nakagawa, Masataka Ikeda, Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki:
30.9 Normally-off computing with crystalline InGaZnO-based FPGA. 502-503 - Junjie Lu, Steven R. Young, Itamar Arel, Jeremy Holleman:
30.10 A 1TOPS/W analog deep machine-learning engine with floating-gate storage in 0.13μm CMOS. 504-505 - Xicheng Jiang, Piero Malcovati, Vladimir Stojanovic, Tetsuya Lizuka:
F1: Digitally assisted analog and analog-assisted digital in high-performance scaled CMOS process. 510-511 - Yusuke Oike, Makoto Ikeda, Albert Theuwissen, Johannes Solhusvik, Jonathan Chang, Tadahiro Kuroda:
F2: 3D stacking technologies for image sensors and memories. 512-513 - Eric Fluhr, Michael Polley, Se-Hyun Yang, Vasantha Erraguntla, Tobias Noll, Kees van Berkel:
F3: Adaptive design techniques for energy efficiency. 514-515 - Marc Tiebout, Brian A. Floyd, Mike Keaveney, Pierre Busson, Kenichi Okada:
F4: Mm-Wave advances for active safety and communication systems. 516-517 - Woogeun Rhee, Gangadhar Burra, Kazutami Arimoto, Pieter Harpe, Brian Otis, David Ruffieux:
F5: Low-power radios for sensor networks. 518-519 - Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon:
F6: Energy-efficient I/O design for next-generation systems. 520-521 - Leland Chang, Ajith Amerasekera, Takashi Hashimoto:
ES2: Data centers to support tomorrow's cloud. 523 - Refet Firat Yazicioglu, Sam Kavusi, Chris Van Hoof:
ES3: Wearable wellness devices: Fashion, health, and informatics. 525 - Willy Sansen:
SC1: Biomedical and sensor interface circuits. 528
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