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ORCIDPervez M. Aziz
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Journal Articles
- 2014
[j4]Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong:
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. IEEE J. Solid State Circuits 49(12): 3091-3103 (2014)- 2011
- [j3]Freeman Zhong, Shaolei Quan, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang:
A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS. IEEE J. Solid State Circuits 46(12): 3126-3139 (2011) - 2001
- [j2]Pervez M. Aziz, Srinivasan Surendran:
Symbol rate timing recovery for higher order partial response channels. IEEE J. Sel. Areas Commun. 19(4): 635-648 (2001) - 1996
- [j1]Pervez M. Aziz, Henrik V. Sorensen, Jan Van der Spiegel:
An overview of sigma-delta converters. IEEE Signal Process. Mag. 13(1): 61-84 (1996)
Conference and Workshop Papers
- 2014
- [c9]Pervez M. Aziz, Hiroshi Kimura, Amaresh V. Malipatil, Shiva Kotagiri, Gordon Chan, Hairong Gao:
Shift register multi-phase clock based downsampled floating tap DFE for serial links. ISCAS 2014: 2469-2472 - [c8]Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Shiva Kotagiri, Lijun Li, Christopher J. Abel, Freeman Zhong:
2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. ISSCC 2014: 38-39 - 2013
- [c7]Pervez M. Aziz, Amaresh V. Malipatil:
Analysis of a class of decimated clock/data recovery architectures for serial links. ISCAS 2013: 1175-1178 - 2012
- [c6]Pervez M. Aziz, Hiroshi Kimura, Amaresh V. Malipatil, Shiva Kotagiri:
A class of downsampled floating tap DFE architectures with application to serial links. ISCAS 2012: 325-328 - 2011
- [c5]Pervez M. Aziz, Amaresh V. Malipatil:
Adaptation algorithms for a class of continuous time analog equalizers with application to serial links. ISCAS 2011: 1383-1386 - [c4]Shaolei Quan, Freeman Zhong, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang:
A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS. ISSCC 2011: 348-350 - 1999
- [c3]Pervez M. Aziz, Necip Sayiner, Viswanath Annampedu:
A rate 16/17 punctured MTR block code. ICC 1999: 1643-1647 - 1995
- [c2]Pervez M. Aziz, Henrik V. Sorensen, Jan Van der Spiegel:
Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta Systems. ISCAS 1995: 641-644 - 1994
- [c1]Pervez M. Aziz, Henrik V. Sorensen, Jan Van der Spiegel:
Multi band sigma delta analog to digital conversion. ICASSP (3) 1994: 249-252
Coauthor Index
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