"A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End ..."

Hiroshi Kimura et al. (2014)

> Home

Details and statistics

DOI: 10.1109/JSSC.2014.2349974

access: open

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/jssc/KimuraAJSKNGJHLZKKCSGZLWMLAZ14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/KimuraAJSKNGJHLZKKCSGZLWMLAZ14
Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong:
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. IEEE J. Solid State Circuits 49(12): 3091-3103 (2014)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.