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2020 – today
- 2024
[j54]Jae-Hyun Chung
, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu:
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. IEEE J. Solid State Circuits 59(8): 2481-2491 (2024)- [j53]Dong-Hun Lee, Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. IEEE J. Solid State Circuits 59(10): 3232-3241 (2024) - [j52]Lizhen Zhang, Bo Gao, Kun-Woo Park, Kent Edrian Lozada, Raymond Mabilangan, Hyeongjin Kim, Jianhui Wu, Seung-Tak Ryu:
DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation. IEEE Open J. Circuits Syst. 5: 349-364 (2024) - [j51]Ji-Wook Kwon, Dong-Hwan Jin, Min-Jae Seo, Seung-Tak Ryu:
An M-Metric Readout Circuit for MLC Phase-Change Memory With a Comparator-Based Push-Pull Bit-Line Driver. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4658-4662 (2024) - [c37]Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Chang-Un Park, Kun-Woo Park, Kwan-Hoon Song, Young-Hun Moon, Min-Jae Seo, Seung-Tak Ryu:
A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF. VLSI Technology and Circuits 2024: 1-2 - [c36]Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c35]Kent Edrian Lozada, Dong-Hun Lee, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. A-SSCC 2023: 1-3 - [c34]Jae-Hyun Chung, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Min-Jae Seo, Seung-Tak Ryu:
An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. CICC 2023: 1-2 - [c33]Chang-Un Park, Jae-Hyun Chung, Seung-Tak Ryu:
A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration. CICC 2023: 1-2 - 2022
- [j50]Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu:
A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique. IEEE J. Solid State Circuits 57(9): 2791-2801 (2022) - [j49]Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, Seung-Tak Ryu:
A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3635-3639 (2022) - [c32]Dong-Jin Chang, Seung-Tak Ryu:
A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs. VLSI Technology and Circuits 2022: 174-175 - 2021
- [j48]Dong-Jin Chang, Byeong-Gyu Nam, Seung-Tak Ryu:
MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs. IEEE Access 9: 117554-117564 (2021) - [j47]Dong-Ryeol Oh, Kyoung-Jun Moon, Won-Mook Lim, Ye-Dam Kim, Eun-Ji An, Seung-Tak Ryu:
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS. IEEE J. Solid State Circuits 56(4): 1216-1226 (2021) - [j46]Dong-Jin Chang, Michael Choi, Seung-Tak Ryu:
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration. IEEE J. Solid State Circuits 56(9): 2691-2700 (2021) - [c31]Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Dong-Jin Chang, Seung-Tak Ryu:
A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization. A-SSCC 2021: 1-3 - [c30]Seung-Yong Lim, Raymond Mabilangan, Dong-Jin Chang, Young-Jae Cho, Michael Choi, Seung-Tak Ryu:
An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation. A-SSCC 2021: 1-3 - 2020
- [j45]Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Seung-Tak Ryu:
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. IEEE J. Solid State Circuits 55(10): 2660-2669 (2020) - [j44]Yi-Ju Roh, Dong-Jin Chang, Seung-Tak Ryu:
A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision. IEEE Trans. Circuits Syst. 67-II(12): 2833-2837 (2020) - [j43]Kyoung-Jun Moon, Dong-Ryeol Oh, Michael Choi, Seung-Tak Ryu:
A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC. IEEE Trans. Circuits Syst. 67-II(12): 2843-2847 (2020) - [j42]Dong-Jin Chang, Byeong-Gyu Nam, Seung-Tak Ryu:
Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron. IEEE Trans. Circuits Syst. 67-I(12): 5189-5199 (2020) - [j41]Dong-Shin Jo, Ba-Ro-Saim Sung, Min-Jae Seo, Woo-Cheol Kim, Seung-Tak Ryu:
A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration. IEEE Trans. Circuits Syst. II Express Briefs 67-II(4): 610-614 (2020) - [c29]Jongpal Kim, Wonseok Lee, Junyeub Suh, Hyungwoo Lee, Kyu-Il Lee, Ho Young Ahn, Min-Jae Seo, Seung-Tak Ryu, Kirill Y. Aristovich, David S. Holder, Sang Joon Kim:
A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section. EMBC 2020: 4012-4015 - [c28]Dong-Ryeol Oh, Kyoung-Jun Moon, Won-Mook Lim, Ye-Dam Kim, Eun-Ji An, Seung-Tak Ryu:
An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j40]Chang-Kyo Lee, Seung-Tak Ryu:
Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC. IET Circuits Devices Syst. 13(8): 1277-1283 (2019) - [j39]Dong-Ryeol Oh, Jong-In Kim, Dong-Shin Jo, Woo-Chul Kim, Dong-Jin Chang, Seung-Tak Ryu:
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration. IEEE J. Solid State Circuits 54(1): 288-297 (2019) - [j38]Dong-Hwan Jin, Ji-Wook Kwon, Min-Jae Seo, Mi-Young Kim, Min-Chul Shin, Seokjoon Kang, Junghyuk Yoon, Taek-Seung Kim, Seung-Tak Ryu:
A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers. IEEE J. Solid State Circuits 54(6): 1812-1823 (2019) - [j37]Kyoung-Jun Moon, Dong-Shin Jo, Wan Kim, Michael Choi, Hyung-Jong Ko, Seung-Tak Ryu:
A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS. IEEE J. Solid State Circuits 54(9): 2532-2542 (2019) - [c27]Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Dong-Jin Chang, Won-Mook Lim, Jae-Hyun Chung, Chang-Un Park, Eun-Ji An, Seung-Tak Ryu:
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. A-SSCC 2019: 189-192 - [c26]Min-Jae Seo, Ye-Dam Kim, Jae-Hyun Chung, Seung-Tak Ryu:
A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. VLSI Circuits 2019: 72- - [c25]Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim, Seung-Tak Ryu:
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. VLSI Circuits 2019: 138- - 2018
- [j36]Il-Hoon Jang, Min-Jae Seo, Sang-Hyun Cho, Jae-Keun Lee, Seung-Yeob Baek, Sunwoo Kwon, Michael Choi, Hyung-Jong Ko, Seung-Tak Ryu:
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. IEEE J. Solid State Circuits 53(4): 1139-1148 (2018) - [j35]Hyun-Wook Kang, Hyeok-Ki Hong, Wan Kim, Seung-Tak Ryu:
A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme. IEEE J. Solid State Circuits 53(9): 2584-2594 (2018) - [j34]Tsung-Hsien Lin, Chia-Hsiang Yang, Seung-Tak Ryu:
Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 53(10): 2739-2740 (2018) - [j33]Dong-Jin Chang, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu:
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 281-285 (2018) - [j32]Si-Nai Kim, Woo-Cheol Kim, Min-Jae Seo, Seung-Tak Ryu:
A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs. IEEE Trans. Circuits Syst. II Express Briefs 65-II(9): 1154-1158 (2018) - [j31]Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Sun-Il Hwang, Jong-Pal Kim, Seung-Tak Ryu:
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3617-3627 (2018) - [j30]Min-Jae Seo, Yi-Ju Roh, Dong-Jin Chang, Wan Kim, Ye-Dam Kim, Seung-Tak Ryu:
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1904-1908 (2018) - [c24]Matt Straayer, Seung-Tak Ryu, Un-Ku Moon:
Session 14 overview: High-resolution ADCs: Data converter subcommittee. ISSCC 2018: 228-229 - 2017
- [j29]Hyeon-June Kim, Sun-Il Hwang, Jae-Hyun Chung, Jong-Ho Park, Seung-Tak Ryu:
A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction. IEEE J. Solid State Circuits 52(9): 2488-2497 (2017) - [j28]Tim Piessens, Seung-Tak Ryu, Chih-Ming Hung, Alyosha C. Molnar, Mounir Meghelli:
Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 52(12): 3115-3118 (2017) - [j27]Dong-Jin Chang, Wan Kim, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu:
Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 322-332 (2017) - [c23]Kostas Doris, David Robertson, Seung-Tak Ryu, Seng-Pan U:
F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX. ISSCC 2017: 515-517 - [c22]Ki-Hoon Seo, Il-Hoon Jang, Kyung-Jun Noh, Seung-Tak Ryu:
An incremental zoom sturdy MASH ADC. MWSCAS 2017: 1013-1016 - 2016
- [j26]Wan Kim, Hyeok-Ki Hong, Yi-Ju Roh, Hyun-Wook Kang, Sun-Il Hwang, Dong-Shin Jo, Dong-Jin Chang, Min-Jae Seo, Seung-Tak Ryu:
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. IEEE J. Solid State Circuits 51(8): 1826-1839 (2016) - [j25]Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu:
A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs. IEEE J. Solid State Circuits 51(10): 2262-2273 (2016) - [j24]Hyun-Wook Kang, Hyeok-Ki Hong, Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn, Seung-Tak Ryu:
A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs. IEEE Trans. Circuits Syst. II Express Briefs 63-II(6): 518-522 (2016) - [j23]Si-Nai Kim, Mee-Ran Kim, Ba-Ro-Saim Sung, Hyun-Wook Kang, Min-Hyung Cho, Seung-Tak Ryu:
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm2. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 794-798 (2016) - [c21]Kwantae Kim, Minseo Kim, Hyunwoo Cho, Kwonjoon Lee, Seung-Tak Ryu, Hoi-Jun Yoo:
A 54-μW fast-settling arterial pulse wave sensor for wrist watch type system. ISCAS 2016: 1082-1085 - [c20]Kostas Doris, Alyosha C. Molnar, Xicheng Jiang, Seung-Tak Ryu:
F2: Data-converter calibration and dynamic-matching techniques. ISSCC 2016: 495-497 - 2015
- [j22]Hyun-Wook Kang, Hyeok-Ki Hong, Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn, Seung-Tak Ryu:
Ternary-level thermometer C-DAC switching scheme for flash-assisted SAR ADCs. IEICE Electron. Express 12(10): 20150302 (2015) - [j21]Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Michael Choi, Ho-Jin Park, Seung-Tak Ryu:
A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC. IEEE J. Solid State Circuits 50(2): 543-555 (2015) - [j20]Jong-In Kim, Dong-Ryeol Oh, Dong-Shin Jo, Ba-Ro-Saim Sung, Seung-Tak Ryu:
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. IEEE J. Solid State Circuits 50(10): 2319-2330 (2015) - [j19]Dong-Hwan Jin, Ji-Wook Kwon, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Junho Cheon, Seung-Tak Ryu:
A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory. IEEE J. Solid State Circuits 50(10): 2431-2440 (2015) - [c19]Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu:
Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs. A-SSCC 2015: 1-4 - [c18]Dong-Ryeol Oh, Jong-In Kim, Min-Jae Seo, Jin-Gwang Kim, Seung-Tak Ryu:
A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS. ESSCIRC 2015: 323-326 - [c17]Hyeok-Ki Hong, Hyun-Wook Kang, Dong-Shin Jo, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu:
26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique. ISSCC 2015: 1-3 - [c16]Ba-Ro-Saim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu:
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. ISSCC 2015: 1-3 - [c15]Seung-Tak Ryu, Matt Straayer:
Session 15 overview: Data-converter techniques: Data converters subcommittee. ISSCC 2015: 270-271 - 2014
- [j18]Hyunsik Kim, Junhyeok Yang, Sang-Hui Park, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs. IEEE J. Solid State Circuits 49(3): 766-782 (2014) - [j17]Ghil-Geun Oh, Chang-Kyo Lee, Seung-Tak Ryu:
A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications. IEEE Trans. Circuits Syst. II Express Briefs 61-II(1): 6-10 (2014) - [c14]Ji-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Jong-Ho Kang, Seung-Tak Ryu:
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. CICC 2014: 1-4 - [c13]Young-Sub Yuk, Seungchul Jung, Hui-Dong Gwon, Sukhwan Choi, Si-Duk Sung, Tae-Hwang Kong, Sung-Wan Hong, Jun-Han Choi, Min-Yong Jeong, Jong-Pil Im, Seung-Tak Ryu, Gyu-Hyeong Cho:
23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface. ISSCC 2014: 402-403 - 2013
- [j16]Hyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-il Kim, Young Kim, Sangwook Kim, Dae-Kun Yoon, Jun Su Lee, Jae-Chul Park, Younghun Sung, Seong-Deok Lee, Seung-Tak Ryu, Gyu-Hyeong Cho:
An Asynchronous Sampling-Based 128x128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution. IEEE J. Solid State Circuits 48(2): 541-558 (2013) - [j15]Jong-In Kim, Ba-Ro-Saim Sung, Wan Kim, Seung-Tak Ryu:
A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS. IEEE J. Solid State Circuits 48(6): 1429-1441 (2013) - [j14]Junhyeok Yang, Seungchul Jung, Young-Suk Son, Seung-Tak Ryu, Gyu-Hyeong Cho:
A Noise-Immune High-Speed Readout Circuit for In-Cell Touch Screen Panels. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(7): 1800-1809 (2013) - [j13]Chang-Kyo Lee, Wan Kim, Hyun-Wook Kang, Seung-Tak Ryu:
A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design. IEEE Trans. Circuits Syst. II Express Briefs 60-II(9): 557-561 (2013) - [j12]Seung-Yeob Baek, Jae-Kyum Lee, Seung-Tak Ryu:
An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers. IEEE Trans. Circuits Syst. II Express Briefs 60-II(9): 562-566 (2013) - [c12]Junhyeok Yang, Sang-Hui Park, Jung-Min Choi, Hyunsik Kim, Changbyung Park, Seung-Tak Ryu, Gyu-Hyeong Cho:
A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels. ISSCC 2013: 390-391 - [c11]Hyunsik Kim, Junhyeok Yang, Sang-Hui Park, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDs. ISSCC 2013: 392-393 - [c10]Hyeok-Ki Hong, Hyun-Wook Kang, Barosaim Sung, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, Seung-Tak Ryu:
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement. ISSCC 2013: 470-471 - 2012
- [j11]Huy-Binh Le, Sang-Gug Lee, Seung-Tak Ryu:
A Single-Supply 84 dB DR Audio-Band ADC for Compact Digital Microphones. IEICE Trans. Electron. 95-C(1): 130-136 (2012) - [j10]Hundo Shin, Seung-Tak Ryu:
A 180-µW, 120-MHz, Fourth Order Low-Pass Bessel Filter Based on FVF Biquad Structure. IEICE Trans. Electron. 95-C(5): 949-957 (2012) - [j9]Jong-Pil Im, Se-Won Wang, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting. IEEE J. Solid State Circuits 47(12): 3055-3067 (2012) - [j8]Sang-Hyun Cho, Chang-Kyo Lee, Sang-Gug Lee, Seung-Tak Ryu:
A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 765-769 (2012) - [c9]Hyeok-Ki Hong, Wan Kim, Sun-Jae Park, Michael Choi, Ho-Jin Park, Seung-Tak Ryu:
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control. CICC 2012: 1-4 - [c8]Jong-Pil Im, Se-Won Wang, Kang-Ho Lee, Young-Jin Woo, Young-sub Yuk, Tae-Hwang Kong, Sung-Wan Hong, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting. ISSCC 2012: 104-106 - [c7]Hyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-il Kim, Young Kim, Sangwook Kim, Dae-Kun Yoon, Jun Su Lee, Jae-Chul Park, Younghun Sung, Seong-Deok Lee, Seung-Tak Ryu, Gyu-Hyeong Cho:
A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel. ISSCC 2012: 110-112 - 2011
- [j7]Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, Seung-Tak Ryu:
A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction. IEEE J. Solid State Circuits 46(8): 1881-1892 (2011) - [j6]Huy-Binh Le, Xuan-Dien Do, Sang-Gug Lee, Seung-Tak Ryu:
A Long Reset-Time Power-On Reset Circuit With Brown-Out Detection Capability. IEEE Trans. Circuits Syst. II Express Briefs 58-II(11): 778-782 (2011) - [j5]Hyunsik Kim, Jinyong Jeon, Sungwoo Lee, Junhyeok Yang, Seung-Tak Ryu, Gyu-Hyeong Cho:
A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 887-891 (2011) - [c6]Jong-In Kim, Wan Kim, Barosaim Sung, Seung-Tak Ryu:
A time-domain latch interpolation technique for low power flash ADCs. CICC 2011: 1-4 - [c5]Hyunsik Kim, Jinyong Jeon, Sungwoo Lee, Junhyeok Yang, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 0.014mm2 9b switched-current DAC for AMOLED mobile display drivers. ISSCC 2011: 316-318 - 2010
- [j4]Yeong-Shin Jang, Hoai-Nam Nguyen, Seung-Tak Ryu, Sang-Gug Lee:
Yield-Ensuring DAC-Embedded Opamp Design Based on Accurate Behavioral Model Development. IEICE Trans. Electron. 93-C(6): 935-937 (2010) - [c4]Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, Seung-Tak Ryu:
A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction. CICC 2010: 1-4 - [c3]Junhyeok Yang, Seungchul Jung, Young-Jin Woo, Jinyong Jeon, Sungwoo Lee, Changbyung Park, Hyunsik Kim, Seung-Tak Ryu, Gyu-Hyeong Cho:
A novel readout IC with high noise immunity for charge-based touch screen panels. CICC 2010: 1-4
2000 – 2009
- 2009
- [j3]Huy-Binh Le, Seung-Tak Ryu, Sang-Gug Lee:
A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones. IEICE Trans. Electron. 92-C(4): 587-588 (2009) - [c2]Ba Sung, Sang-Hyun Cho, Chang-Kyo Lee, Jong-In Kim, Seung-Tak Ryu:
A Time-interleaved Flash-SAR Architecture for High Speed A/D Conversion. ISCAS 2009: 984-987 - 2007
- [j2]Seung-Tak Ryu, Bang-Sup Song, Kantilal Bacrania:
A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse. IEEE J. Solid State Circuits 42(3): 475-485 (2007) - 2006
- [c1]Seung-Tak Ryu, Bang-Sup Song, Kantilal Bacrania:
A 10b 50MS/s pipelined ADC with opamp current reuse. ISSCC 2006: 792-801 - 2004
- [j1]Seung-Tak Ryu, Sourja Ray, Bang-Sup Song, Gyu-Hyeong Cho, Kantilal Bacrania:
A 14-b linear capacitor self-trimming pipelined ADC. IEEE J. Solid State Circuits 39(11): 2046-2051 (2004)
Coauthor Index
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Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-01-21 00:13 CET by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
