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ORCIDIEEE Journal of Solid-State Circuits, Volume 39
Volume 39, Number 1, January 2004
- Cheung Fai Lee, Philip K. T. Mok
:
A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique. 3-14 - Francesco Gatta, Danilo Manstretta, Paolo Rossi, Francesco Svelto:
A fully integrated 0.18-μm CMOS direct conversion receiver front-end with on-chip LO for UMTS. 15-23 - Christian Fager, José Carlos Pedro, Nuno Borges de Carvalho, Herbert Zirath, Fernando Fortes, Maria João Rosário:
A comprehensive analysis of IMD behavior in RF CMOS power amplifiers. 24-34 - Feng-Jung Huang, Kenneth K. O:
Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p-silicon substrates. 35-41 - In-Chul Hwang, Chulwoo Kim, Sung-Mo Kang:
A CMOS self-regulating VCO with low supply sensitivity. 42-48 - Sudhakar Pamarti, Lars C. Jansson, Ian Galton:
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation. 49-62 - Ruoxin Jiang, Terri S. Fiez:
A 14-bit delta-sigma ADC with 8×OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process. 63-74 - Shouli Yan, Edgar Sánchez-Sinencio:
A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth. 75-86 - Seng-Pan U, Rui Paulo Martins, José E. Franca:
A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS. 87-99 - Esther Rodríguez-Villegas, Alberto Yúfera, Adoración Rueda:
A 1.25-V micropower Gm-C filter based on FGMOS transistors operating in weak inversion. 100-111 - Sung Min Park, Hoi-Jun Yoo:
1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications. 112-121 - Chris Winstead, Jie Dai, Shuhuan Yu, Chris J. Myers, Reid R. Harrison, Christian Schlegel:
CMOS analog MAP decoder for (8, 4) Hamming code. 122-131 - Sangrok Lee, James C. Morizio, Kristina M. Johnson:
Novel frame buffer pixel circuits for liquid-crystal-on-silicon microdisplays. 132-139 - Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui:
An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction. 140-149 - Yong-Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
Synchronous mirror delay for multiphase locking. 150-156 - José Pineda de Gyvez, Hans Tuinhout:
Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits. 157-168 - Yuan-Hao Huang, Hsi-Pin Ma, Ming-Luen Liou, Tzi-Dar Chiueh:
A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications. 169-183 - Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu:
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. 184-193 - Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara:
A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. 194-206 - Koichi Murata, Kimikazu Sano, Hiroto Kitabayashi, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki:
100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology. 207-213 - Kostas Karadamoglou, Nikolaos P. Paschalidis, Emmanuel Sarris, Nikos Stamatopoulos, George Kottaras, Vassilis Paschalidis:
An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments. 214-222 - Tae Wook Kim, Bonkee Kim, Kwyro Lee:
Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors. 223-229 - Yalcin Alper Eken, John P. Uyemura:
A 5.9-GHz voltage-controlled ring oscillator in 0.18-μm CMOS. 230-233 - Wei-Zen Chen, Jia-Xian Chang, Ying-Jen Hong, Meng-Tzer Wong, Chien-Liang Kuo:
A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process. 234-237 - Farhang Vessal, C. André T. Salama:
An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology. 238-241 - Anna Richelli, Luigi Colalongo, Michele Quarantelli, M. Carmina, Zsolt Miklós Kovács-Vajna:
A fully integrated inductor-based 1.8-6-V step-up converter. 242-245 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A 120×110 position sensor with the capability of sensitive and selective light detection in wide dynamic range for robust active range finding. 246-251 - J. Doyle, Young Jun Lee, Yong-Bin Kim, H. Wilsch, Fabrizio Lombardi:
A CMOS subbandgap reference circuit with 1-v power supply voltage. 252-255 - Esther Rodríguez-Villegas, Alberto Yúfera, Adoración Rueda:
A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion. 256-259 - Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Design of ESD power protection with diode structures for mixed-power supply systems. 260-264 - Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa:
A dynamically reconfigurable SIMD processor for a vision chip. 265-268
Volume 39, Number 2, February 2004
- Bernhard Boser:
New Associate Editors. 274 - Federico Bruccoleri, Eric A. M. Klumperink, Bram Nauta:
Wide-band CMOS low-noise amplifier exploiting thermal noise canceling. 275-282 - Mostafa A. I. Elmala, Sherif H. K. Embabi:
Calibration of phase and gain mismatches in Weaver image-reject receiver. 283-289 - Angelika Schneider, Oliver Werther:
Nonlinear analysis of noise in current-steering variable gain amplifiers. 290-296 - Yorgos Palaskas, Yannis P. Tsividis, Vladimir I. Prodanov, Vito Boccuzzi:
A "divide and conquer" technique for implementing wide dynamic range continuous-time filters. 297-307 - Ji-Jon Sit, Rahul Sarpeshkar:
A micropower logarithmic A/D with offset and temperature compensation. 308-319 - Ralf Wunderlich, Carsten Thomas, Klaus Schumacher:
A monolithic positioning system. 320-326 - Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang:
The CMOS carry-forward adders. 327-336 - Rajeevan Amirtharajah, Anantha P. Chandrakasan:
A micropower programmable DSP using approximate signal processing based on distributed arithmetic. 337-347 - Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy:
Computation sharing programmable FIR filter for low-power and high-performance applications. 348-357 - Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Hoi-Jun Yoo:
A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications. 358-367 - Xiang Guan, Ali Hajimiri:
A 24-GHz CMOS front-end. 368-373 - Willy Hioe, Kenji Maio, Takashi Oshima, Yoshiyuki Shibahara, Takeshi Doi, Kiyoharu Ozaki, Satoshi Arayashiki:
0.18-μm CMOS Bluetooth analog receiver with -88-dBm sensitivity. 374-377 - Stefano Pellerano, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. 378-383 - Federico Baronti, Diego Lunardini, Roberto Roncella, Roberto Saletti:
A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme. 384-387 - Rajamohana Hegde, Naresh R. Shanbhag:
A voltage overscaled low-power digital filter IC. 388-391
Volume 39, Number 3, March 2004
- Bernhard Boser:
New Associate Editor. 410 - Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten:
A double-sampling extended-counting ADC. 411-418 - Jong-Sang Choi, Moon-Sang Hwang, Deog-Kyoon Jeong:
A 0.18-μm CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method. 419-425 - Alexandru A. Ciubotaru, Javier S. Garcia:
An integrated direct-coupled 10-Gb/s driver for common-cathode VCSELs. 426-433 - Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal, Fernando Muñoz Chavero:
Very low-voltage analog signal processing based on quasi-floating gate transistors. 434-442 - George Patounakis, Yee William Li, Kenneth L. Shepard:
A fully integrated on-chip DC-DC conversion and power management system. 443-451 - Zhinian Shu, Ka Lok Lee, Bosco H. Leung:
A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture. 452-462 - Sung-Rung Han, Shen-Iuan Liu:
A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle. 463-468 - Ching-Che Chung, Chen-Yi Lee:
A new DLL-based approach for all-digital multiphase clock generation. 469-475 - Liming Xiu, Wen Li, J. Meiners, R. Padakanti:
A novel all-digital PLL with software adaptive filter. 476-483 - Koushik Maharatna, Eckhard Grass, Ulrich Jagdhold:
A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM. 484-493 - Yasuhisa Shimazaki, Radu Zlatanovici, Borivoje Nikolic:
A shared-well dual-supply-voltage 64-bit ALU. 494-500 - Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan:
Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS. 501-510 - Josep Rius Vázquez, José Pineda de Gyvez:
Built-in current sensor for ΔIDDQ testing. 511-518 - Chung-Yu Wu, Chung-Yun Chou:
A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator. 519-521 - Frank Ellinger:
26-42 GHz SOI CMOS low noise amplifier. 522-528 - Kamran Farzan, David A. Johns:
A CMOS 10-gb/s power-efficient 4-PAM transmitter. 529-532 - Stephen Docking, Manoj Sachdev:
An analytical equation for the oscillation frequency of high-frequency ring oscillators. 533-537 - Viktor Gruev, Ralph Etienne-Cummings:
A pipelined temporal difference imager. 538-543
Volume 39, Number 4, April 2004
- Yoshinobu Nakagome, Bruce Gieseke:
Introduction to the Special Issue. 547-548 - Asad A. Abidi:
RF CMOS comes of age. 549-561 - Takahide Kadoyama, Norihito Suzuki, Noboru Sasho, Hiroshi Iizuka, Ikuho Nagase, Hideaki Usukubo, Masayuki Katakura:
A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-μm CMOS. 562-568 - Mamoru Ugajin, Akihiro Yamagishi, Junichi Kodate, Mitsuru Harada, Tsuneo Tsukahara:
Macromodels in the frequency domain analysis of microwave resonators. 569-576 - Takahiro Ohnakado, Satoshi Yamakawa, Takaaki Murakami, Akihiko Furukawa, Eiji Taniguchi, Hiro-omi Ueda, Noriharu Suematsu, Tatsuo Oomori:
21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs). 577-584 - David B. Barkin, Andrew C. Y. Lin, David K. Su, Bruce A. Wooley:
A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering. 585-593 - Jri Lee, Behzad Razavi:
A 40-GHz frequency divider in 0.18-μm CMOS technology. 594-601 - Jackie Koon Lun Wong, Hamid Hatamkhani, Mozhgan Mansuri, Chih-Kong Ken Yang:
A 27-mW 3.6-gb/s I/O transceiver. 602-612 - Yoshio Miki, Tatsuya Saito, Hiroki Yamashita, Fumio Yuki, Takashige Baba, Akio Koyama, Masahito Sonehara:
A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking. 613-621 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
Design and implementation of real-time 3-D image sensor with 640 × 480 pixel resolution. 622-628 - Ingo Hehemann, Werner Brockherde, Holger Hofmann, Armin Kemna, Bedrich J. Hosticka:
A single-chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems. 629-635 - Simon Tam, Rahul Dilip Limaye, Utpal Nagarji Desai:
Clock generation and distribution for the 130-nm Itanium® 2 processor with 6-MB on-die L3 cache. 636-642 - Eiichi Takahashi, Yuji Kasai, Masahiro Murakawa, Tetsuya Higuchi:
Post-fabrication clock-timing adjustment using genetic algorithms. 643-650 - Ali Muhtaroglu, Greg Taylor, Tawfik Rahal-Arabi:
On-die droop detector for analog sensing of power supply noise. 651-660 - Mitsuru Hiraki, Kenichi Fukui, Takayasu Ito:
A low-power microcontroller having a 0.5-μA standby current on-chip regulator with dual-reference scheme. 661-666 - Hugh P. McAdams, Randy Acklin, Terry Blake, Xiao-Hong Du, Jarrod Eliason, John Y. Fong, William F. Kraus, David Liu, Sudhir Madan, Ted Moise, Sreedhar Natarajan, Ning Qian, Yunchen Qiu, Keith Remack, J. Rodriguez, John Roscher, Anand Seshadri, Scott R. Summerfelt:
A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process. 667-677 - John K. DeBrosse, Dietmar Gogl, Alexander Bette, Heinz Hoenigschmid, Raphael Robertazzi, Christian Arndt, Daniel Braun, D. Casarotto, Robert Havreluk, Stefan Lammers, Werner Obermaier, William R. Reohr, Hans Viehmann, William J. Gallagher, Gerhard Müller:
A high-speed 128-kb MRAM core for future universal memory applications. 678-683 - Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade:
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. 684-693 - Jae-Yoon Sim, Kee-Won Kwon, Ki-Chul Chun:
Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs. 694-703 - Yee William Li, George Patounakis, Kenneth L. Shepard, Steven M. Nowick:
High-throughput asynchronous datapath with software-controlled voltage scaling. 704-708 - Shwetabh Verma, Junfeng Xu, Thomas H. Lee:
A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis. 709-713 - Raymond Montemayor:
A 410-mW 1.22-GHz downconverter in a dual-conversion tuner IC for OpenCable applications. 714-718
Volume 39, Number 5, May 2004
- Jiangfeng Wu, Gary K. Fedder, L. Richard Carley:
A low-noise low-offset capacitive sensing amplifier for a 50-μg√Hz monolithic CMOS MEMS accelerometer. 722-730 - SeongHwan Cho, Anantha P. Chadrakasan:
A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications. 731-739 - Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino:
PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. 740-750 - Thomas Olsson, Peter Nilsson:
A digitally controlled PLL for SoC applications. 751-760 - Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu:
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. 761-774 - Salvatore Levantino, Luca Romanò, Stefano Pellerano, Carlo Samori, Andrea L. Lacaita:
Phase noise in digital frequency dividers. 775-784 - Hsi-Pin Ma, Ming-Luen Liou, Tzi-Dar Chiueh:
A 123-mW W-CDMA uplink baseband receiver IC with beamforming capability. 785-794 - Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong:
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. 795-803 - Kenichiro Anjo, Atsushi Okamura, Masato Motomura:
Wrapper-based bus implementation techniques for performance improvement and cost reduction. 804-817 - Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan:
A leakage reduction methodology for distributed MTCMOS. 818-826 - Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takayuki Kawahara:
SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. 827-833 - Ming-Huang Liu, Kuo-Chan Huang, Wei-Yang Ou, Tsung-Yi Su, Shen-Iuan Liu:
A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC. 834-836 - Koon-Lun Jackie Wong, Chih-Kong Ken Yang:
Offset compensation in comparators with minimum input-referred supply noise. 837-840 - Neric H. W. Fong, Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Garry Tarr:
A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology. 841-846 - Yongchul Song, Beomsup Kim:
A 14-b direct digital frequency synthesizer with sigma-delta noise shaping. 847-851 - Chi-Fang Li, Yuan-Sun Chu, Wern-Ho Sheen, Fu-Chin Tian, Jan-Shin Ho:
A low-power ASIC design for cell search in the W-CDMA system. 852-857
Volume 39, Number 6, June 2004
- Bernhard Boser:
New Associate Editor. 862 - Niranjan A. Talwalkar, C. Patrick Yue, Haitao Gan, S. Simon Wong:
Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications. 863-870 - Kwang-Jin Koh, Mun-Yang Park, Cheon-Soo Kim, Hyun-Kyu Yu:
Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver. 871-884 - Christian Kromer, Gion Sialm, Thomas Morf, Martin L. Schmatz, Frank Ellinger, Daniel Erni, Heinz Jäckel:
A low-power 20-GHz 52-dBΩ transimpedance amplifier in 80-nm CMOS. 885-894 - Tom Zimmerman, James R. Hoff:
The design of a charge-integrating modified floating-point ADC chip. 895-905 - Yi-Ming Wang, Jinn-Shyan Wang:
A low-power half-delay-line fast skew-compensation circuit. 906-918 - Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu:
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI. 919-926 - Kouichi Kanda, Hattori Sadaaki, Takayasu Sakurai:
90% write power-saving SRAM using sense-amplifying memory cell. 927-933 - Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi:
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. 934-940 - Changsik Yoo, Kye-Hyun Kyung, Kyunam Lim, Hi-Choon Lee, Joon-Wan Chai, Nak-Won Heo, Dong-Jin Lee, Chang-Hyun Kim:
A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. 941-951 - Hye-Ryoung Kim, Choong-Yul Cha, Seung-Min Oh, Moon-Su Yang, Sang-Gug Lee:
A very low-power quadrature VCO with back-gate coupling. 952-955 - Qiurong He, Milton Feng:
Low-power, high-gain, and high-linearity SiGe BiCMOS wide-band low-noise amplifier. 956-959 - Paolo Cusinato:
Gain/bandwidth programmable PA control loop for GSM/GPRS quad-band cellular handsets. 960-966 - Youn Sub Noh, Chul Soon Park:
An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications. 967-970 - Sung Min Park, Jaeseo Lee, Hoi-Jun Yoo:
1-Gb/s 80-dBΩ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects. 971-974
Volume 39, Number 7, July 2004
- David Ruffieux, Thierry Melly, Vincent Peiris, Jean-Félix Perotto, Nicolas Raemy, Erwan Le Roux:
A 1.2 mW RDS receiver for portable applications. 995-1005 - Winfried Bakalski, Werner Simbürger, Ronald Thüringer, Andriy Vasylyev, Arpad L. Scholtz:
A fully integrated 5.3-GHz 2.4-V 0.3-W SiGe bipolar power amplifier with 50-Ω output. 1006-1014 - Nicolas Schlumpf, Michel J. Declercq, Catherine Dehollain:
A fast Modulator for dynamic supply linear RF power amplifier. 1015-1025 - Harish S. Muthali, Thomas P. Thomas, Ian A. Young:
A CMOS 10-gb/s SONET transceiver. 1026-1033 - Roger Steadman, Francisco Morales Serrano, Gereon Vogtmeier, Armin Kemna, Erol Oezkan, Werner Brockherde, Bedrich J. Hosticka:
A CMOS photodiode array with in-pixel data acquisition system for computed tomography. 1034-1043 - Gustavo Liñán Cembrano, Ángel Rodríguez-Vázquez, Ricardo Carmona-Galán, Francisco Jiménez-Garrido, Servando Espejo, Rafael Domínguez-Castro:
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O. 1044-1055 - Susana Patón, Antonio Di Giandomenico, Luis Hernández, Andreas Wiesbauer, Thomas Pötscher, Martin Clara:
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. 1056-1063 - Kevin O'Sullivan, Chris Gorman, Michael Hennessy, Vincent Callaghan:
A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm2. 1064-1072 - Jurgen Deveugele, Pieter Palmers, Michiel S. J. Steyaert:
Parallel-path digital-to-analog converters for Nyquist signal generation. 1073-1082 - Andrea Gerosa, Andrea Maniero, Andrea Neviani:
A fully integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakers. 1083-1093 - Christian Panis, Herbert Grünbacher, Jari Nurmi:
A scalable instruction buffer and align unit for xDSPcore. 1094-1100 - Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo:
A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals. 1101-1109 - Michele Sala, Fabrizio Salidu, Fabrizio Stefani, Christian Kutschenreiter, Andrea Baschirotto:
Design considerations and implementation of a DSP-based car-radio IF Processor. 1110-1118 - Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man:
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. 1119-1130 - Tobias Gemmeke, Michael Gansen, Heinrich J. Stockmanns, Tobias G. Noll:
Design optimization of low-power high-performance DSP building blocks. 1131-1139 - Daniel Kehrer, Hans-Dieter Wohlmuth:
A 30-gb/s 70-mW one-stage 4: 1 multiplexer in 0.13-μm CMOS. 1140-1147 - Bernhard Wicht, Thomas Nirschl, Doris Schmitt-Landsiedel:
Yield and speed optimization of a latch-type voltage sense amplifier. 1148-1158 - Arnoud P. van der Wel, Sander L. J. Gierkink, Robert C. Frye, Vito Boccuzzi, Bram Nauta:
A robust 43-GHz VCO in CMOS for OC-768 SONET applications. 1159-1163 - Han-Il Lee, Je-Kwang Cho, Kun-Seok Lee, In-Chul Hwang, Tae-Won Ahn, Kyung-Suc Nah, Byeong-Ha Park:
A Σ-Δ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications. 1164-1169 - Marc Tiebout:
A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider. 1170-1174 - Helen Waite, P. Ta, Jennie Chen, H. Li, M. Gao, C. S. Chang, Y. S. Chang, William Redman-White, Olivier Charlon, Y. Fan, R. Perkins, D. Brunel, E. Soudee, N. Lecacheur, S. Clamagirand:
A CDMA2000 zero-IF receiver with low-leakage integrated front-end. 1175-1179 - Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis, Nikos Haralabidis:
A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-μm CMOS transceiver for 802.11a/b/g wireless LAN. 1180-1184 - Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee, Donghyeon Seo, Inho Song, Sanghun Jung, Joonbae Park, Deog-Kyoon Jeong, Soo-Ik Chae, W. Kim:
A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b. 1185-1190 - Markus Zannoth, Thomas Rühlicke, Bernd-Ulrich Klepser:
A highly integrated dual-band multimode wireless LAN transceiver. 1191-1195 - Miguel E. Figueroa, Seth Bridges, David Hsu, Chris Diorio:
A 19.2 GOPS mixed-signal filter with floating-gate adaptation. 1196-1201 - Diego Barrettino, Markus Graf, Wan Ho Song, Kay-Uwe Kirstein, Andreas Hierlemann, Henry Baltes:
Hotplate-based monolithic CMOS microsystems for gas detection and material characterization for operating temperatures up to 500 °C. 1202-1207 - O. Elkhalili, Olaf M. Schrey, Peter Mengel, M. Petermann, Werner Brockherde, Bedrich J. Hosticka:
A 4×64 pixel CMOS image sensor for 3-D measurement applications. 1208-1212 - Yoshihisa Fujimoto, Hitoshi Tani, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto:
A low-power switched-capacitor variable gain amplifier. 1213-1216
Volume 39, Number 8, August 2004
- Bernhard E. Boser:
Editorial. 1219 - Krishnaswamy Nagaraj:
Editorial. 1220 - Sheng Ye, Ian Galton:
Techniques for phase noise suppression in recirculating DLLs. 1222-1230 - Eric A. M. Klumperink, Simon M. Louwsma, Gerard J. M. Wienk, Bram Nauta:
A CMOS switched transconductor mixer. 1231-1240 - Sotoudeh Hamedi-Hagh, C. André T. Salama:
CMOS wireless phase-shifted transmitter. 1241-1252 - Gabriel Brenna, David Tschopp, Jürgen Rogin, Ilian Kouchev, Qiuting Huang:
A 2-GHz carrier leakage calibrated direct-conversion WCDMA transmitter in 0.13-μm CMOS. 1253-1262 - Behnam Analui, Ali Hajimiri:
Bandwidth enhancement for transimpedance amplifiers. 1263-1270 - Francisco Serra-Graells, Lluís Gómez, José Luis Huertas:
A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip. 1271-1281 - Dejan Markovic, Vladimir Stojanovic, Borivoje Nikolic, Mark A. Horowitz, Robert W. Brodersen:
Methods for true energy-performance optimization. 1282-1293 - Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija:
A test circuit for measurement of clocked storage element characteristics. 1294-1304 - Hong-Yi Huang, Jing-Fu Lin:
Design and application of CMOS bulk input scheme. 1305-1312 - Chih-Wen Lu, Kuo-Jen Hsu:
A high-speed low-power rail-to-rail column driver for AMLCD application. 1313-1320 - Ahmed M. Eltawil, Babak Daneshrad:
A low-power DS-CDMA RAKE receiver utilizing resource allocation techniques. 1321-1330 - Sergio Pernici, Fabio Stevenazzi, Germano Nicollini:
Fully integrated voiceband codec in a standard digital CMOS technology. 1331-1334 - Jong-Bum Park, Sang-Min Yoo, Se-Won Kim, Young-Jae Cho, Seung-Hoon Lee:
A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth. 1335-1337 - Jesús Arias Álvarez, Vito Boccuzzi, Luis Quintanilla, Lourdes Enríquez, David Bisbal, Mihai Banu, Juan Barbolla:
Low-power pipeline ADC for wireless LANs. 1338-1340 - Vittorio Colonna, Gabriele Gandolfi, Fabrizio Stefani, Andrea Baschirotto:
A 10.7-MHz self-calibrated switched-capacitor-based multibit second-order bandpass ΣΔ modulator with on-chip switched buffer. 1341-1346 - Yang Xu, Cameron Boone, Lawrence T. Pileggi:
Metal-mask configurable RF front-end circuits. 1347-1351 - Mingquan Bao, Yinggang Li, Harald Jacobsson:
A 21.5/43-GHz dual-frequency balanced Colpitts VCO in SiGe technology. 1352-1355 - Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu:
A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet. 1356-1360 - Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi:
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. 1361-1365 - Wei-Ming Lin, Hong-Yi Huang:
A low-jitter mutual-correlated pulsewidth control loop circuit. 1366-1369 - Ren-Chieh Liu, Chin-Shen Lin, Kuo-Liang Deng, Huei Wang:
Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode. 1370-1374 - Shinichi Yasuda, Hideki Satake, Tetsufumi Tanamoto, Ryuji Ohba, Ken Uchida, Shinobu Fujita:
Physical random number generator based on MOS structure after soft breakdown. 1375-1377 - Ming-Dou Ker, Kun-Hsien Lin:
Design on ESD protection scheme for IC with power-down-mode operation. 1378-1382 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture. 1383-1387
Volume 39, Number 9, September 2004
- Edoardo Charbon, Albert Z. H. Wang, Sreedhar Natarajan:
Introduction to the Special Issue on the IEEE 2003 Custom Integrated Circuits Conference. 1391-1393 - Gennady Gildenblat, Hailing Wang, Ten-Lon Chen, Xin Gu, Xiaowen Cai:
SP: an advanced surface-potential-based compact MOSFET model. 1394-1406 - Tzung-Yin Lee, Yuhua Cheng:
High-frequency characterization and modeling of distortion behavior of MOSFETs for RF IC design. 1407-1414 - Behzad Razavi:
A study of injection locking and pulling in oscillators. 1415-1424 - Andrea Mazzanti, Paola Uggetti, Francesco Svelto:
Analysis and design of injection-locked LC dividers for quadrature generation. 1425-1433 - Dennis K. Ma, John R. Long:
A subharmonically injected LC delay line oscillator for 17-GHz quadrature LO generation. 1434-1445 - Enrico Temporiti, Guido Albasini, Ivan Bietti, Rinaldo Castello, Matteo Colombo:
A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications. 1446-1454 - Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert A. Groves, Robert Trzcinski, Mohamed Talbi, Asit Ray, Lawrence F. Wagner:
A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology. 1455-1461 - Susan Luschas, Richard Schreier, Hae-Seung Lee:
Radio frequency digital-to-analog converter. 1462-1467 - Jipeng Li, Un-Ku Moon:
A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique. 1468-1476 - Arokia Nathan, Anil Kumar, Kapil Sakariya, Peyman Servati, Sanjiv Sambandan, Denis Striakhilev:
Amorphous silicon thin film transistor circuit integration for organic LED displays on glass and plastic. 1477-1486 - Pablo M. Acosta-Serafini, Ichiro Masaki, Charles G. Sodini:
A 1/3" VGA linear wide dynamic range CMOS image sensor implementing a predictive multiple sampling algorithm with overlapping integration intervals. 1487-1496 - Jin-Hyeok Choi, Yingxue Xu, Takayasu Sakurai:
Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain. 1497-1503 - Benton H. Calhoun, Anantha P. Chandrakasan:
Standby power reduction using dynamic voltage scaling and canary flip-flop structures. 1504-1511 - Kostas Pagiamtzis, Ali Sheikholeslami:
A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme. 1512-1519 - Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown:
Resonant clocking using distributed parasitic capacitance. 1520-1528 - Robert J. Drost, Robert David Hopkins, Ron Ho, Ivan E. Sutherland:
Proximity communication. 1529-1535 - Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar:
Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. 1536-1543 - David Garrett, Linda M. Davis, Stephan ten Brink, Bertrand M. Hochwald, Geoff Knagge:
Silicon complexity for maximum likelihood MIMO detection using spherical decoding. 1544-1552 - Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng:
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. 1553-1561 - Masayuki Miyama, Junichi Miyakoshi, Yuki Kuroda, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. 1562-1570 - Jri Lee, Kenneth S. Kundert, Behzad Razavi:
Analysis and modeling of bang-bang clock and data recovery circuits. 1571-1580 - Mini Nanua, David T. Blaauw:
Noise analysis methodology for partially depleted SOI circuits. 1581-1585 - Tom Prokop, Charles Thomas, Mark Bickerstaff, J. Niemasz, Pierre Bernadac, Patrice Saintot, R. Laufer, Dominique Bescher, R. Michel, Brett C. Walker, F. Derriennic, N. Burban, E. Le Pape, J. P. Moreau, I. Cha, S. Angioni, K. Mhirsi, J. Lee, P. Prat, G. Rogard, V. L'Aubin, D. Le Gall, C. Dagorn, D. Guillerm, P. Ragon, T. Goumis, M. Cooke, B. Widdup, G. Zhou, David Garrett, C. Conan, P. Cabon, A. Carter, Chris Nicol, P. Keevill, P. Mankiewich:
An eight-user UMTS channel unit Processor for 3GPP base station applications. 1586-1590
Volume 39, Number 10, October 2004
- Yves Baeyens, Marino Juan Martinez:
Introduction to the Special Issue on the 25th Annual IEEE GaAs Integrated Circuits Conference. 1595-1597 - Freek van Straten, Bart Smolders, Albert van Zuijlen, Remco Ooijman:
Multiband cellular RF solutions. 1598-1604 - Jeffrey B. Johnson, Alvin J. Joseph, David C. Sheridan, Ramana M. Maladi, Per-Olof Brandt, Jonas Persson, Jesper Andersson, Are Bjorneklett, Ulrika Persson, Fariborz Abasi, Lars Tilly:
Silicon-germanium BiCMOS HBT technology for wireless power amplifier applications. 1605-1614 - Marko Sokolich, Mary Y. Chen, Rajesh D. Rajavel, David H. Chow, Yakov Royter, Stephen Thomas III, Charles H. Fields, Binqiang Shi, Steven S. Bui, James Chingwei Li, Donald A. Hitko, Kenneth R. Elliott:
InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers. 1615-1621 - Madjid Hafizi, Shen Feng, Taoling Fu, Kim Schulze, Robert Ruth, Richard Schwab, Per Karlsen, David Simmonds, Qizheng Gu:
RF front-end of direct conversion receiver RFIC for cdma-2000. 1622-1632 - Albert E. Cosand, Joseph F. Jensen, H. Chris Choe, Charles H. Fields:
IF-sampling fourth-order bandpass ΔΣ modulator for digital receiver applications. 1633-1639 - Herbert Zirath, Toru Masuda, Rumen Kozhuharov, Mattias Ferndahl:
Development of 60-GHz front-end circuits for a high-data-rate communication system. 1640-1649 - Hao Li, Hans-Martin Rein, Thomas Suttorp, Josef Böck:
Fully integrated SiGe VCOs with powerful output buffer for 77-GHz automotive Radar systems and applications around 100 GHz. 1650-1658 - Cattalen Pelard, Edward Gebara, Andrew J. Kim, Michael G. Vrazel, Franklin Bien, Youngsik Hur, Moonkyun Maeng, Soumya Chandramouli, Carl Chun, Sanjay Bajekal, Stephen E. Ralph, Bruce Schmukler, Vincent M. Hietala, Joy Laskar:
Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits. 1659-1670 - Jaesik Lee, Pascal Roux, Ut-Va Koc, Thomas Link, Yves Baeyens, Young-Kai Chen:
A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers. 1671-1679 - Hai Tran, Florin Pera, Douglas S. McPherson, Dorin Viorel, Sorin P. Voinigescu:
6-kΩ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range. 1680-1689 - Hiroyuki Fukuyama, Kimikazu Sano, Koichi Murata, Hiroto Kitabayashi, Yasuro Yamane, Takatomo Enoki, Hirohiko Sugahara:
Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/s. 1690-1696 - Yves Baeyens, Nils Weimann, Pascal Roux, Andreas Leven, Vincent Houtsma, Rose F. Kopf, Yang Yang, John Frackoviak, Alaric Tate, Joseph S. Weiner, Peter Paschke, Young-Kai Chen:
High gain-bandwidth differential distributed InP D-HBT driver amplifiers with large (11.3 Vpp) output swing at 40 Gb/s. 1697-1705 - Toshihide Suzuki, Tsuyoshi Takahashi, Tatsuya Hirose, Masahiko Takikawa:
A 80-gbit/s D-type flip-flop circuit using InP HEMT technology. 1706-1711 - Alexander V. Rylyakov, Thomas Zwick:
96-GHz static frequency divider in SiGe bipolar technology. 1712-1715 - J. M. Yang, R. Lai, Y. H. Chung, M. Nishimoto, M. Battung, W. Lee, R. Kagiwada:
Compact ka-band bi-directional amplifier for low-cost electronic scanning array antenna. 1716-1719 - Joseph S. Weiner, Jaesik Lee, Andreas Leven, Yves Baeyens, Vincent Houtsma, George Georgiou, Yang Yang, John Frackoviak, Alaric Tate, Roberto Reyes, Rose F. Kopf, Wei-Jer Sung, Nils Weimann, Young-Kai Chen:
An InGaAs-InP HBT differential transimpedance amplifier with 47-GHz bandwidth. 1720-1723 - Mourad El-Gamal:
Introduction to the Special Issue on the 2003 IEEE Bipolar/BiCMOS Circuits and Technology Meeting. 1724-1726 - Mark P. van der Heijden, Leo C. N. de Vreede, Joachim N. Burghartz:
On the design of unilateral dual-loop feedback low-noise amplifiers with simultaneous noise, impedance, and IIP3 match. 1727-1736 - Aichin Chung, John R. Long:
A 5-6-GHz bipolar quadrature-phase Generator. 1737-1745 - Keith Nellis, Peter J. Zampardi:
A comparison of linear handset power amplifiers in different bipolar technologies. 1746-1754 - Martin Pfost, Pietro Brenner, Thomas Huttner, Andriy Romanyuk:
An experimental study on substrate coupling in bipolar/BiCMOS technologies. 1755-1763 - Nebojsa Nenadovic, Slobodan Mijalkovic, Lis K. Nanver, Lode K. J. Vandamme, Vincenzo d'Alessandro, Hugo Schellevis, Jan W. Slotboom:
Extraction and modeling of self-heating and mutual thermal coupling impedance of bipolar transistors. 1764-1772 - Werner Perndl, Herbert Knapp, Klaus Aufinger, Thomas F. Meister, Werner Simbürger, Arpad L. Scholtz:
Voltage-controlled oscillators up to 98 GHz in SiGe bipolar technology. 1773-1777 - David Trémouilles, Marise Bafleur, Géraldine Bertrand, Nicolas Nolhier, Nicolas Mauran, Lionel Lescouzères:
Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency. 1778-1782
Volume 39, Number 11, November 2004
- Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis:
A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration. 1799-1808 - Libin Yao, Michiel S. J. Steyaert, Willy Sansen:
A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS. 1809-1818 - Elias H. Dagher, Peter A. Stubberud, Wesley K. Masenten, Matteo Conta, Thang Victor Dinh:
A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth. 1819-1828 - Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja:
A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer. 1829-1838 - Brian K. Swann, Benjamin J. Blalock, Lloyd G. Clonts, David M. Binkley, James M. Rochelle, Eric Breeding, K. Michelle Baldwin:
A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications. 1839-1852 - Yongchul Song, Beomsup Kim:
A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR. 1853-1861 - Remco C. H. van de Beek, Cicero S. Vaucher, Domine M. W. Leenaerts, Eric A. M. Klumperink, Bram Nauta:
A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS. 1862-1872 - Gerry C. T. Leung, Howard C. Luong:
A 1-V 5.2-GHz CMOS synthesizer for WLAN applications. 1873-1882 - Pietro Andreani, Xiaoyan Wang:
On the phase-noise and phase-error performances of multiphase LC CMOS VCOs. 1883-1893 - Robert J. Drost, Bruce A. Wooley:
An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-μm CMOS. 1894-1908 - Xavier Maillard, Maarten Kuijk:
An 8-Gb/s capacitively coupled receiver with high common-mode rejection for uncoded data. 1909-1915 - Thomas Byunghak Cho, David Kang, Chun-Huat Heng, Bang-Sup Song:
A 2.4-GHz dual-mode 0.18-μm CMOS transceiver for Bluetooth and 802.11b. 1916-1926 - Chengzhou Wang, Mani Vaidyanathan, Lawrence E. Larson:
A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers. 1927-1937 - Chih-Wen Lu:
High-speed driving scheme and compact high-speed low-power rail-to-rail class-B buffer amplifier for LCD applications. 1938-1947 - Paul Morrow, Eric Gaalaas, Oliver McCarthy:
A 20-W stereo class-D audio output power stage in 0.6-μm BCDMOS technology. 1948-1958 - Chris D. Holdenried, James W. Haslett, Michael W. Lynch:
Analysis and design of HBT Cherry-Hooper amplifiers with emitter-follower feedback for optical communications. 1959-1967 - Robert Rieger, Andreas Demosthenous, John Taylor:
A 230-nW 10-s time constant CMOS integrator for an adaptive nerve signal amplifier. 1968-1975 - Maysam Ghovanloo, Khalil Najafi:
Fully integrated wideband high-current rectifiers for inductively powered devices. 1976-1984 - Micah G. O'Halloran, Rahul Sarpeshkar:
A 10-nW 12-bit accurate analog storage cell with 10-aA leakage. 1985-1996 - Kihyuk Sung, Lee-Sup Kim:
A high-resolution synchronous mirror delay using successive approximation register. 1997-2004 - Yu-Wei Lin, Hsuan-Yu Liu, Chen-Yi Lee:
A dynamic scaling FFT processor for DVB-T applications. 2005-2013 - Binh Quang Le, Michael Achter, Chin Ghee Chng, Xin Guo, Lee Cleveland, Pau-Ling Chen, Michael Van Buskirk, Robert W. Dutton:
Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory. 2014-2023 - Yadollah Eslami, Ali Sheikholeslami, Shoichi Masui, Toru Endo, Shoichiro Kawashima:
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM). 2024-2031 - Leibo Liu, Ning Chen, Hongying Meng, Li Zhang, Zhihua Wang, Hongyi Chen:
A VLSI architecture of JPEG2000 encoder. 2032-2040 - Chien-Hung Kuo, Shen-Iuan Liu:
A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps. 2041-2045 - Seung-Tak Ryu, Sourja Ray, Bang-Sup Song, Gyu-Hyeong Cho, Kantilal Bacrania:
A 14-b linear capacitor self-trimming pipelined ADC. 2046-2051 - Takashi Oshima, Kenji Maio, Willy Hioe, Yoshiyuki Shibahara:
Novel automatic tuning method of RC filters using a digital-DLL technique. 2052-2054 - Eunseok Song, Seung-Wook Lee, Jeong-Woo Lee, Joonbae Park, Soo-Ik Chae:
A reset-free anti-harmonic delay-locked loop using a cycle period detector. 2055-2061 - Jing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay:
A 25-GHz emitter degenerated LC VCO. 2062-2064 - Scott K. Reynolds:
A 60-GHz superheterodyne downconversion mixer in silicon-germanium bipolar technology. 2065-2068 - Zhenbiao Li, Richard Quintal, Kenneth K. O:
A dual-band CMOS front-end with two gain modes for wireless LAN applications. 2069-2073 - Xiaohong Peng, Willy Sansen:
AC boosting compensation scheme for low-power multistage amplifiers. 2074-2079 - Mark Shane Peng, Hae-Seung Lee:
Study of substrate noise and techniques for minimization. 2080-2086 - Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, Kyo-Won Jin, Kyeong-Sik Min, Jin-Yong Chung, Hong-June Park:
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs. 2087-2092
Volume 39, Number 12, December 2004
- Raf L. J. Roovers, Arya R. Behzad, Vadim Gutnik, Dennis Polla:
Introduction to the Special Issue on the ISSCC2004. 2095-2097 - Pier Andrea Francese, Pascal Ferrat, Qiuting Huang:
A 13-b 1.1-MHz oversampled DAC with semidigital reconstruction filtering. 2098-2106 - Robert C. Taft, Chris A. Menkus, Maria Rosaria Tursi, Ols Hidri, Valerie Pons:
A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency. 2107-2115 - Jan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes:
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS. 2116-2125 - Eric Siragusa, Ian Galton:
A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC. 2126-2138 - Yun Chiu, Paul R. Gray, Borivoje Nikolic:
A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. 2139-2151 - Lucien J. Breems, Robert Rutten, Gunnar Wetzker:
A cascaded continuous-time ΣΔ Modulator with 67-dB dynamic range in 10-MHz bandwidth. 2152-2160 - Pio Balmelli, Qiuting Huang:
A 25-MS/s 14-b 200-mW ΣΔ Modulator in 0.18-μm CMOS. 2161-2169 - Kathleen Philips, Peter A. C. M. Nuijten, Raf L. J. Roovers, Arthur H. M. van Roermund, Fernando Muñoz Chavero, Macarena Tejero Pallarés, Antonio Torralba:
A continuous-time ΣΔ ADC with increased immunity to interferers. 2170-2178 - Tirdad Sowlati, Dmitriy Rozenblit, Rajasekhar Pullela, Morten Damgaard, Evan McCarthy, Dongsoo Koh, David Ripley, Florinel Balteanu, Ionel Gheorghe:
Quad-band GSM/GPRS/EDGE polar loop transmitter. 2179-2189 - Michael R. Elliott, Tony Montalvo, Brad P. Jeffries, Frank Murden, Jon Strange, Allen Hill, Sanjay Nandipaku, Johannes Harrebek:
A polar modulator transmitter for GSM/EDGE. 2190-2199 - See Taur Lee, Sher Jiun Fang, David J. Allstot, Abdellatif Bellaouar, Ahmed R. Fridi, Paul Fontaine:
A quad-band GSM-GPRS transmitter with digital auto-calibration. 2200-2214 - Vincent W. Leung, Lawrence E. Larson, Prasad S. Gudem:
Digital-IF WCDMA handset transmitter IC in 0.25-μm SiGe BiCMOS. 2215-2225 - Laurent Perraud, Marc Recouly, Christophe Pinatel, Nicolas Sornin, Jean-Louis Bonnot, Frederic Benoist, Myriam Massei, Olivier Gibrat:
A direct-conversion CMOS transceiver for the 802.11a/b/g WLAN standard utilizing a Cartesian feedback transmitter. 2226-2238 - Masoud Zargari, Manolis Terrovitis, Steve Hung-Min Jen, Brian J. Kaczynski, MeeLan Lee, Michael P. Mack, Srenik S. Mehta, Sunetra Mendis, Keith Onodera, Hirad Samavati, William W. Si, Kalwant Singh, Ali Tabatabaei, David Weber, David K. Su, Bruce A. Wooley:
A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN. 2239-2249 - Rami Ahola, Adem Aktas, James Wilson, Kishore Rama Rao, Fredrik Jonsson, Isto Hyyryläinen, Anders Brolin, Timo Hakala, Aki Friman, Tuula Mäkiniemi, Jenny Hanze, Martin Sandén, Daniel Wallner, Yuxin Guo, Timo Lagerstam, Laurent Noguer, Timo Knuuttila, Peter Olofsson, Mohammed Ismail:
A single-chip CMOS transceiver for 802.11a/b/g wireless LANs. 2250-2258 - Andrea Bevilacqua, Ali M. Niknejad:
An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers. 2259-2268 - Aly Ismail, Asad A. Abidi:
A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network. 2269-2277 - Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold, Chih-Ming Hung, Yo-Chuol Ho, John L. Wallberg, Chan Fernando, Ken Maggio, Roman Staszewski, Tom Jung, Jinseok Koh, Soji John, Irene Yuanying Deng, Vivek Sarda, Oscar Moreira-Tamayo, Valerian Mayega, Ran Katz, Ofer Friedman, Oren Eytan Eliezer, Elida de-Obaldia, Poras T. Balsara:
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. 2278-2291 - Hooman Darabi, Brima Ibrahim, Ahmadreza Rofougaran:
An analog GFSK modulator in 0.35-μm CMOS. 2292-2296 - Philip Quinlan, Patrick Crowley, Miguel Chanca, Sean Hudson, Bill Hunt, Kenneth Mulvaney, Guido Retz, Cormac E. O'Sullivan, Patrick Walsh:
A multimode 0.3-200-kb/s transceiver for the 433/868/915-MHz bands in 0.25-μm CMOS. 2297-2310 - Xiang Guan, Hossein Hashemi, Ali Hajimiri:
A fully integrated 24-GHz eight-element phased-array receiver in silicon. 2311-2320 - Stephen Y. Yue, Dennis K. Ma, John R. Long:
A 17.1-17.3-GHz image-reject downconverter with phase-tunable LO using 3× subharmonic injection locking. 2321-2332 - Shoji Otaka, Mitsuyuki Ashida, Masato Ishii, Tetsuro Itakura:
A +10-dBm IIP3 SiGe mixer with IM3 cancellation technique. 2333-2341 - Jinwen Xiao, Angel V. Peterchev, Jianhui Zhang, Seth R. Sanders:
A 4-μa quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications. 2342-2348 - Heinz Werker, Stephan Mechnig, Christophe Holuigue, Christian Ebner, Gerhard Mitteregger, Ernesto Romani, Frédéric Roger, Thomas Blon, Michael Moyal, Marcello Vena, Andrea Melodia, John Fisher, Gregoìre Le Grand de Mercey, Heribert Geib:
A 10-GB/s SONET-compliant CMOS transceiver with low crosstalk and intrinsic jitter. 2349-2358 - Byunghoo Jung, Ramesh Harjani:
ΣHigh-frequency LC VCO design using capacitive degeneration. 2359-2370 - Peter Pessl, Richard Gaggl, Johannes Hohl, Dario Giotta, Joerg Hauptmann:
A four-channel ADSL2+ analog front-end for CO applications with 75 mW per channel, built in 0.13-μm CMOS. 2371-2378 - Quan Le, Sang-Gug Lee, Yong-Hun Oh, Ho-Yong Kang, Tae-Whan Yoo:
A burst-mode receiver for 1.25-Gb/s ethernet PON with AGC and internally created reset signal. 2379-2388 - Sherif Galal, Behzad Razavi:
40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology. 2389-2396 - Yasuyuki Suzuki, Zin Yamazaki, Yasushi Amamiya, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida:
120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs. 2397-2402 - Mounir Meghelli:
132-Gb/s 4: 1 multiplexer in 0.13-μm SiGe-bipolar technology. 2403-2407 - Keiji Mabuchi, Nobuo Nakamura, Eiichi Funatsu, Takashi Abe, Tomoyuki Umeda, Tetsuro Hoshino, Ryoji Suzuki, Hirofumi Sumi:
CMOS image sensors comprised of floating diffusion driving pixels with buried photodiode. 2408-2416 - Hidekazu Takahashi, Masakuni Kinoshita, Kazumichi Morita, Takahiro Shirai, Toshiaki Sato, Takayuki Kimura, Hiroshi Yuzurihara, Shunsuke Inoue, Shigeyuki Matsumoto:
A 3.9-μm pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel. 2417-2425 - Mitsuyoshi Mori, Motonari Katsuno, Shigetaka Kasuga, Takahiko Murata, Takumi Yamaguchi:
1/4-inch 2-mpixel MOS image sensor with 1.75 transistors/pixel. 2426-2430 - Martin Jenkner, Marco Tartagni, Andreas Hierlemann, Roland Thewes:
Cell-based CMOS sensor and actuator arrays. 2431-2437 - Meinrad Schienle, Christian Paulus, Alexander Frey, Franz Hofmann, Birgit Holzapfl, Petra Schindler-Bauer, Roland Thewes:
A fully electronic DNA sensor with 128 positions and in-pixel A/D conversion. 2438-2445 - Louis S. Y. Wong, Shohan Hossain, Andrew Ta, Jörgen Edvinsson, Dominic H. Rivas, Hans Nääs:
A very low-power CMOS mixed-signal IC for implantable pacemaker applications. 2446-2456 - Maysam Ghovanloo, Khalil Najafi:
A Modular 32-site wireless neural stimulation microsystem. 2457-2466 - Babak Vakili-Amini, Farrokh Ayazi:
A 2.5-V 14-bit ΣΔ CMOS SOI capacitive accelerometer. 2467-2476 - Yu-Wei Lin, Seungbae Lee, Sheng-Shian Li, Yuan Xie, Zeying Ren, Clark T.-C. Nguyen:
Series-resonant VHF micromechanical resonator reference oscillators. 2477-2491 - Hai Tran, FlorinPera Pera, Douglas S. McPherson, Dorin Viorel, Sorin P. Voinigescu:
Correction to "6-k$Omega$43-Gb/s Differential Transimpedance-Limiting Amplifier With Auto-Zero Feedback and High Dynamic Range". 2492
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