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ORCIDTakashi Kono
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2020 – today
- 2024
[j10]Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda
, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C. IEEE J. Solid State Circuits 59(4): 1283-1292 (2024)- [c12]Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Masayuki Izuna, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono:
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs. ISSCC 2024: 290-292 - 2023
- [c11]Toyohiro Shimogawa, Makoto Nonaka, Toma Ogata, Toshiki Kiryu, Yasuto Igarashi, Kosuke Yayama, Masahiro Kitamura, Hiromichi Ishikura, Mitsuru Hiraki, Masao Ito, Takashi Kono:
An On-Chip DC-DC Converter and Power Management System Achieving Zero Standby-to-Active Transition Time in MCU. A-SSCC 2023: 1-3 - 2022
- [j9]Masaya Nakano, Yoshinobu Kaneda, Satoru Nakanishi, Yasumitsu Murai, Yosuke Tashiro, Yasuhiko Taito, Tomoya Ogawa, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier. IEEE J. Solid State Circuits 57(10): 3094-3102 (2022) - [c10]Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C. VLSI Technology and Circuits 2022: 134-135 - 2021
- [c9]Masaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier. A-SSCC 2021: 1-3 - 2020
- [j8]Takashi Kono, Yasuhiko Taito, Hideto Hidaka:
Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age. IEICE Trans. Electron. 103-C(4): 132-143 (2020)
2010 – 2019
- 2019
- [c8]Ken Matsubara, Tsutomu Nagasawa, Yoshinobu Kaneda, Hidenori Mitani, Hiroshi Sato, Takashi Iwase, Yasunobu Aoki, Keiichi Maekawa, Hideaki Yamakoshi, Takashi Ito, Hiroyuki Kondo, Takashi Kono:
A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications. VLSI Circuits 2019: 202- - [c7]Akihiko Kanda, Takashi Kurafuji, Koichi Takeda, Tomoya Ogawa, Yasuhiko Taito, Kazuo Yoshihara, Masaya Nakano, Takashi Ito, Hiroyuki Kondo, Takashi Kono:
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive. VLSI Circuits 2019: 210- - 2018
- [j7]Keith A. Bowman, Muhammad M. Khellah, Takashi Kono, Joseph Shor, Pui-In Mak:
Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 53(1): 3-7 (2018) - [p1]Takashi Kono, Tomoya Saito, Tadaaki Yamauchi:
Overview of Embedded Flash Memory Technology. Embedded Flash Memory for Embedded Systems 2018: 29-74 - 2017
- [c6]Takashi Kono, Ki-Tae Park, Leland Chang:
Session 11 overview: Nonvolatile memory solutions. ISSCC 2017: 194-195 - [c5]Takashi Kono:
Embedded non-volatile memory system as an enabler of smarter world. VLSI-DAT 2017: 1-4 - 2016
- [j6]Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C. IEEE J. Solid State Circuits 51(1): 213-221 (2016) - [c4]Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C. ISSCC 2016: 140-141 - 2015
- [c3]Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C. ISSCC 2015: 1-3 - [c2]Fatih Hamzaoglu, Takashi Kono:
Session 7 overview: Non-volatile memory solutions: Memory subcommittee. ISSCC 2015: 126-127 - 2014
- [j5]Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C. IEEE J. Solid State Circuits 49(1): 154-166 (2014) - 2013
- [c1]Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data. ISSCC 2013: 212-213
2000 – 2009
- 2005
- [j4]Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara:
Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories. IEICE Trans. Electron. 88-C(2): 255-263 (2005) - 2004
- [j3]Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara:
A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. IEEE J. Solid State Circuits 39(1): 194-206 (2004) - 2000
- [j2]Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki:
A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs. IEEE J. Solid State Circuits 35(8): 1179-1185 (2000) - [j1]Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara:
A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE J. Solid State Circuits 35(11): 1680-1689 (2000)
Coauthor Index
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