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ORCIDKoichi Takeda
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
Person information
Other persons with the same name
- Koichi Takeda 0001 — Renesas Electronics, LSI Research Laboratory, Kawasaki, Japan (and 1 more)
- Koichi Takeda 0002 (aka: Kohichi Takeda) — IBM Research, Tokyo, Japan
- Koichi Takeda 0003 — Nagoya University, Graduate School of Informatics, Japan
- Koichi Takeda 0004 — University of Tohoku, Department of Electrical and Communication Engineering, Sendai, Japan
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2020 – today
- 2024
[j4]Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda
, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C. IEEE J. Solid State Circuits 59(4): 1283-1292 (2024)- [c6]Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Masayuki Izuna, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono:
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs. ISSCC 2024: 290-292 - 2022
- [c5]Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C. VLSI Technology and Circuits 2022: 134-135 - 2021
- [c4]Masaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier. A-SSCC 2021: 1-3
2010 – 2019
- 2019
- [c3]Akihiko Kanda, Takashi Kurafuji, Koichi Takeda, Tomoya Ogawa, Yasuhiko Taito, Kazuo Yoshihara, Masaya Nakano, Takashi Ito, Hiroyuki Kondo, Takashi Kono:
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive. VLSI Circuits 2019: 210- - 2015
- [c2]Makoto Ueki, K. Takeuchi, T. Yamamoto, Akira Tanabe, N. Ikarashi, M. Saitoh, T. Nagumo, Hiroshi Sunamura, Mitsuru Narihiro, Kazuya Uejima, Koji Masuzaki, Naoya Furutake, S. Saito, Y. Yabe, Akira Mitsuiki, Koichi Takeda, Takashi Hase, Yoshihiro Hayashi:
Low-power embedded ReRAM technology for IoT applications. VLSIC 2015: 108- - 2013
- [j3]Koichi Takeda, Toshihiko Takemura, Takashi Kozu:
Investment Literacy and Individual Investor Biases: Survey Evidence in the Japanese Stock Market. Rev. Socionetwork Strateg. 7(1): 31-42 (2013)
2000 – 2009
- 2007
- [c1]Toshiyuki Sugimoto, Noriyuki Shirahata, Yoshio Higashiyama, Koichi Takeda:
Surface Potential of Insulating Plate Coated by Metallic Paint Spray. IAS 2007: 438-443
1990 – 1999
- 1996
- [j2]Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki:
A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. IEEE J. Solid State Circuits 31(1): 84-90 (1996) - 1995
- [j1]Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki:
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. IEEE J. Solid State Circuits 30(11): 1196-1202 (1995)
Coauthor Index
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