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ORCIDMasahide Takada
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1990 – 1999
- 1996
[j12]Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki:
A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. IEEE J. Solid State Circuits 31(1): 84-90 (1996)- [j11]Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki:
A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits 31(11): 1610-1617 (1996) - [j10]Hiraki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihiro Hayashi
, Yukihiko Maejima, Kazushi Amanuma, Nobuhira Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada:
A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme. IEEE J. Solid State Circuits 31(11): 1625-1634 (1996) - 1995
- [j9]Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki:
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. IEEE J. Solid State Circuits 30(11): 1196-1202 (1995) - 1994
- [j8]Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki:
A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. IEEE J. Solid State Circuits 29(11): 1317-1322 (1994) - 1993
- [j7]Toshiaki Inoue, Junichi Goto, Masakazu Yamashina, Kazumasa Suzuki, Masahiro Nomura, Youichi Koseki, Tohru Kimura, Takao Atsumo, Masato Motomura, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada, Masahide Takada:
A 300-MHz 16-b BiCMOS video signal processor. IEEE J. Solid State Circuits 28(12): 1321-1330 (1993) - [j6]Masao Fukuma, Hiroshi Furuta, Masahide Takada:
Memory LSI reliability. Proc. IEEE 81(5): 768-775 (1993) - 1992
- [j5]Kazuyuki Nakamura, Takashi Oguri, Takao Atsumo, Masahide Takada, Atsushi Ikemoto, Hisamitsu Suzuki, Tadashi Nishigori, Tohru Yamazaki:
A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits 27(11): 1504-1510 (1992) - [j4]Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda:
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. IEEE J. Solid State Circuits 27(11): 1525-1533 (1992) - 1990
- [j3]Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaki Koyama:
A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. IEEE J. Solid State Circuits 25(4): 903-911 (1990) - [j2]Masahide Takada, Kazuyuki Nakamura, Toshio Takeshima, Koichiro Furuta, Tohru Yamazaki, Kiyotaka Imai, Susumu Ohi, Yumi Sekine, Yukio Minato, Hisamitsu Kimuto:
A 5-ns 1-Mb ECL BiCMOS SRAM. IEEE J. Solid State Circuits 25(5): 1057-1062 (1990) - [c1]Hiroki Koike, Toshio Takeshima, Masahide Takada:
A BIST scheme using microprogram ROM for large capacity memories. ITC 1990: 815-822
1980 – 1989
- 1988
- [j1]Toshio Takeshima, Masahide Takada, Toshiyuki Shimizu, Takuya Katoh, Mitsuru Sakamoto:
Voltage limiters for DRAMs with substrate-plate-electrode memory cells. IEEE J. Solid State Circuits 23(1): 48-52 (1988)
Coauthor Index
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