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2000 – 2009
- 2000
[j5]Takashi Okuda, Isao Naritake, Tadahiko Sugibayashi, Yuji Nakajima, Tatsunori Murotani:
A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor. IEEE J. Solid State Circuits 35(8): 1153-1158 (2000)
1990 – 1999
- 1997
- [j4]Takashi Okuda, Tatsunori Murotani:
A four-level storage 4-Gb DRAM. IEEE J. Solid State Circuits 32(11): 1743-1747 (1997) - 1995
- [j3]Tadahiko Sugibayashi, Isao Naritake, Satoshi Utsugi, Kentaro Shibahara, Ryuichi Oikawa, Hidemitsu Mori, Shouichi Iwao, Tatsunori Murotani, Kuniaki Koyama, Shinichi Fukuzawa, Toshiro Itani, Kunihiko Kasama, Takashi Okuda, Shuichi Ohya, Masaki Ogawa:
A 1-Gb DRAM for file applications. IEEE J. Solid State Circuits 30(11): 1277-1280 (1995) - 1992
- [j2]Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda:
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. IEEE J. Solid State Circuits 27(11): 1525-1533 (1992) - 1990
- [j1]Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaki Koyama:
A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. IEEE J. Solid State Circuits 25(4): 903-911 (1990)
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