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ORCIDIEEE Journal of Solid-State Circuits, Volume 27
Volume 27, Number 1, January 1992
- Yuval Tamir:
Self-checking self-repairing computer nodes using the Mirror Processor. 4-16 - Gregory A. Uvieghara, Wen-mei W. Hwu, Yoshinobu Nakagome, Deog-Kyoon Jeong, David D. Lee, David A. Hodges, Yale N. Patt:
An experimental single-chip data flow CPU. 17-28 - Keshab K. Parhi, Ching-Yi Wang, Andrew P. Brown:
Synthesis of control circuits in folded pipelined DSP architectures. 29-43 - Rajeev Jain, Henry Samueli, Paul T. Yang, Charles Chien, Gloria G. Chen, Linda K. Lau, Bong-Young Chung, Etan G. Cohen:
Computer-aided design of a BPSK spread-spectrum chip set. 44-58 - Mehdi Katoozi, Arnold W. Nordsieck:
Built-in testable error detection and correction. 59-66 - Srinagesh Satyanarayana, Yannis P. Tsividis, Hans Peter Graf:
A reconfigurable VLSI neural network. 67-81 - Jan Van der Spiegel, Paul Mueller, David Blackman, Peter Chance, Christopher Donham, Ralph Etienne-Cummings, Peter R. Kinget:
An analog neural computer with modular architecture for real-time dynamic computations. 82-92 - Chu Phoon Chong, C. André T. Salama, Kenneth C. Smith:
Image-motion detection using analog VLSI. 93-96 - Juan Casas, Ryotaro Kamikawai, Eiichi Goto:
High-frequency operation of quantum flux parametron (QFP) based shift registers and frequency prescalers. 97-105 - Ralph Mason, William Robertson, Douglas Pincock:
An hierarchical VLSI neural network architecture. 106-108 - Sung-Ming Yen, Chi-Sung Laih, Chin-Hsing Chen, Jau-Yien Lee:
An efficient redundant-binary number to binary number converter. 109-112 - Matthew Thompson:
Low-latency, high-speed numerically controlled oscillator using progression-of-states technique. 113-117 - Craig Prunty, Laszlo Gal:
Optimum tapered buffer. 118-119 - Umberto Gatti, Franco Maloberti, Giuseppe Palmisano:
An accurate CMOS sample-and-hold circuit. 120-122 - Nhat M. Nguyen, Robert G. Meyer:
A Si bipolar monolithic RF bandpass amplifier. 123-127 - Fred U. Rosenberger, Charles E. Molnar, Robert W. Dutton:
Comments, with reply, on 'Metastability of CMOS latch/flip-flop'. 128-132 - Jordi Cortadella, Teodor Jové:
Comments on 'Using cache mechanisms to exploit nonrefreshing DRAM's for on-chip memories'. 132
Volume 27, Number 2, February 1992
- Bram Nauta:
A CMOS transconductance-C filter technique for very high frequencies. 142-153 - Christopher Michael, Mohammed Ismail:
Statistical modeling of device mismatch for analog MOS integrated circuits. 154-166 - Kunihiko Yamaguchi, Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Toshiro Hiramoto, Nobuo Tamba, Kunihiko Watanabe, Masanori Odaka, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai:
A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM. 167-174 - Medhi Hatamian, Keshab K. Parhi:
An 85-MHz fourth-order programmable IIR digital filter chip. 175-183 - Michael A. Bree, David E. Dodds, Ronald J. Bolton, Surinder Kumar, Brian L. F. Daku:
A modular bit-serial architecture for large-constraint-length Viterbi decoding. 184-190 - Wen Fang, Arthur Brunnschweiler, Peter Ashburn:
An accurate analytical BiCMOS delay expression and its application to optimizing high-speed BiCMOS circuits. 191-202 - Qiuting Huang:
A CMOS power amplifier with a novel output structure. 203-207 - Guangming Yin, Frank Op't Eynde, Willy Sansen:
A high-speed CMOS comparator with 8-b resolution. 208-211 - Sen-Jung Wei, Hung Chang Lin:
Multivalued SRAM cell using resonant tunneling diodes. 212-216 - G. M. Tharakan, Sung-Mo Kang:
A new design of a fast barrel switch network. 217-221 - Toshiharu Kurosawa, Yuji Maruyama:
A high-speed halftoning processor for raster scanned images. 222-224 - Ching-Te Chuang, K. Chin, Johannes M. C. Stork, Gary L. Patton, Emmanuel F. Crabbé, James H. Comfort:
On the leverage of high-f/sub T/ transistors for advanced high-speed bipolar circuits. 225-228 - Tsin-Yuan Chang, Cheng-Chi Wang, Jain-Bean Hsu:
Two schemes for detecting CMOS analog faults. 229-233
Volume 27, Number 3, March 1992
- Chenming Hu:
IC reliability simulation. 241-246 - Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda, Chang-Gyu Hwang:
Advanced integrated-circuit reliability simulation including dynamic stress effects. 247-257 - Fred L. Yang, Resve A. Saleh:
Simulation and analysis of transient faults in digital circuits. 258-264 - Goodwin R. Chin, Robert W. Dutton:
A tool towards integration of IC process, device, and circuit simulation. 265-273 - Chung-Yu Wu, Ming-Dou Ker, Chung-Yuan Lee, Joe Ko:
A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI. 274-280 - Satwant Singh, Jonathan Rose, Paul Chow, David M. Lewis:
The effect of logic block architecture on FPGA performance. 281-287 - Charles E. Cox, Wolf-Ekkehard Blanz:
GANGLION-a fast field-programmable gate array implementation of a connectionist classifier. 288-299 - Larry Wissel, Elliot L. Gould:
Optimal usage of CMOS within a BiCMOS technology. 300-306 - Hans J. Busschaert, Peter P. Reusens, G. Van Wauwe, M. De Langhe, Ronny M. A. Van Camp, Christiaan M. W. Gouwy, Luc Dartoi:
A power-efficient channel coder/decoder chip for GSM terminals. 307-313 - W. Martin Snelgrove, Ayal Shoval:
A balanced 0.9- mu m CMOS transconductance-C filter tunable over the VHF range. 314-323 - Geert A. De Veirman, Richard G. Yamasaki:
Design of a bipolar 10-MHz programmable continuous-time 0.05 degrees equiripple linear phase filter. 324-331 - Loic Le Toumelin, Pierre Carbou, Yves Leduc, Pascal Guignon, Jan Oredsson, Anders Lindberg:
A 5-V CMOS line controller with 16-b audio converters. 332-342 - Gregory J. Manlove, Jeffrey J. Marrah, Richard A. Kennedy:
A fully integrated high-performance FM stereo decoder. 343-350 - Stephen H. Lewis, H. Scott Fetterman, George F. Gross, Ravi Ramachandran, T. R. Viswanathan:
A 10-b 20-Msample/s analog-to-digital converter. 351-358 - Yasuo Arai, Tsuneo Matsumura, Ken-ichi Endo:
A CMOS four-channel*1K time memory LSI with 1-ns/b resolution. 359-364 - Hiraku Nakano, Masaitsu Nakajima, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota:
An 80-MFLOPS (peak) 64-b microprocessor for parallel computer. 365-372 - Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki:
3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules. 373-381 - Anthony J. McAuley:
Dynamic asynchronous logic for high-speed CMOS systems. 382-388 - Catherine H. Gebotys, Mohamed I. Elmasry:
Optimal synthesis of high-performance architectures. 389-397 - Sabrina E. Kemeny, Habib H. Torbey, Henry E. Meadows, Richard A. Bredthauer, Melanie A. La Shell, Eric R. Fossum:
CCD focal-plane image reorganization processors for lossless image compression. 398-405 - William N. Schnaitter, Steve L. Urmston, Allyn Pon:
A 170-MHz CMOS pixel processor for windowing graphics. 406-416 - Jarvis C. Tou, Perry Gee, John Duh, Richard Eesley:
A submicrometer CMOS embedded SRAM compiler. 417-424 - Wojciech Maly, Marek J. Patyra:
Built-in current testing. 425-428 - S. L. Wong, S. Venkitasubrahmanian, M. J. Kim, J. C. Young:
Design of a 60-V 10-A intelligent power switch using standard cells. 429-432 - Jin Ji, Kensall D. Wise:
An implantable CMOS circuit interface for multiplexed microelectrode recording arrays. 433-443 - Nhat M. Nguyen, Robert G. Meyer:
A 1.8-GHz monolithic LC voltage-controlled oscillator. 444-450 - S. Aur, Charvaka Duvvury, Hugh McAdams, C. Perrin:
Identification of DRAM sense-amplifier imbalance using hot-carrier evaluation. 451-453 - Muhammad E. S. Elrabaa, Mohamed I. Elmasry:
Multiemitter BiCMOS CML circuits. 454-458
Volume 27, Number 4, April 1992
- Minoru Nagata:
Limitations, innovations, and challenges of circuits and devices into a half micrometer and beyond. 465-472 - Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen:
Low-power CMOS digital design. 473-484 - Chih-Liang Chen:
2.5-V bipolar/CMOS circuits for 0.25- mu m BiCMOS technology. 485-491 - Shin-ichi Uramoto, Yoshitsugu Inoue, Akihiko Takabatake, Jun Takeda, Yukihiro Yamashita, Hideyuki Terane, Masahiko Yoshimoto:
A 100-MHz 2-D discrete cosine transform core processor. 492-499 - Michitaka Kameyama, Tadao Amada, Tatsuo Higuchi:
Highly parallel collision detection processor for intelligent robots. 500-506 - Yasushi Ooi, Masahiko Kashimura, Hidenori Takeuchi, Eiji Kawamura:
Fault-tolerant architecture in a cache memory control LSI. 507-514 - Alexander S. Shubat, Cuong Q. Trinh, Arkady Zaliznyak, Arye Ziklik, Anirban Roy, Reza Kazerounian, Y. Cedar, Boaz Eitan:
A family of user-programmable peripherals with a functional unit architecture. 515-529 - Yusuke Ohtomo, Masao Suzuki:
A 250-Mb/s, 700-mW, 32-highway*8-b S/P converter LSI with cross-access memory. 530-538 - Haideh Khorramabadi:
A CMOS line driver with 80-dB linearity for ISDN applications. 539-544 - Paul C. Yu, Steven J. Decker, Hae-Seung Lee, Charles G. Sodini, John L. Wyatt Jr.:
CMOS resistive fuses for image smoothing and segmentation. 545-553 - Noboru Ishihara, Eiichi Sano, Yuhki Imai, Hiroyuki Kikuchi, Yasuro Yamane:
A design technique for a high-gain, 10-GHz class-bandwidth GaAs MESFET amplifier IC module. 554-562 - Katsufumi Nakamura, L. Richard Carley:
An enhanced fully differential folded-cascode op amp. 563-568 - Masanori Hayashikoshi, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima:
A dual-mode sensing scheme of capacitor-coupled EEPROM cell. 569-573 - Clinton Kuo, Mark Weidner, Thomas Toms, Henry Choe, Ko-Min Chang, Ann Hanvood, Joseph Jelemensky, Philip Smith:
A 512-kb flash EEPROM embedded in a 32-b microcontroller. 574-582 - Yoshikazu Miyawaki, Takeshi Nakayama, Shin'ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara:
A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories. 583-588 - Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh:
Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's. 589-596 - Mikio Asakura, Kazutami Arimoto, Hideto Hidaka, Kazuyasu Fujishima:
Cell-plate line connecting complementary bit-line (C/sup 3/) architecture for battery-operated DRAMs. 597-602 - Daisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Kazunori Ohuchi:
Word-line architecture for highly reliable 64-Mb DRAM. 603-609 - Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima:
A high-density dual-port memory cell operation and array architecture for ULSI DRAMs. 610-617 - Travis N. Blalock, Richard C. Jaeger:
A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier. 618-625 - Dong-Sun Min, Soo-In Cho, Dong Soo Jun, Dong-Jae Lee, Yongsik Seok, Daeje Chin:
Temperature-compensation circuit techniques for high-density CMOS DRAMs. 626-631 - Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Kunihiko Yamaguchi, Toshiro Hiramoto, Nobuo Tamba, Masanori Odaka, Kunihiko Watanabe, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai:
High-speed sensing techniques for ultrahigh-speed SRAMs. 632-640 - Tadahiro Kuroda, Toshiyuki Fukunaga, Kenji Matsuo, Kazuhiko Kasai, Ayako Hirata, Shinji Fujii, Masahiro Kimura, Hiroaki Suzuki:
Automated bias control (ABC) circuit for high-performance VLSIs. 641-648 - Henry A. Bonges III, R. Dean Adams, Archibald J. Allen, Roy Flaker, Kenneth S. Gray, Erik L. Hedberg, W. Timothy Holman, George M. Lattimore, David A. Lavalette, Kim Yen T. Nguyen, Alan L. Roberts:
A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-in self-test. 649-656 - Tomio Sato, Masato Sakate, H. Okada, T. Sukemura, Gensuke Goto:
An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit. 657-659 - Ching-Te Chuang, Denny D. Tang:
High-speed low-power AC-coupled complementary push-pull ECL circuit. 660-663 - M. Ohuchi, Toshihiko Okamura, A. Sawairi, F. Kuniba, K. Matsumoto, T. Tashiro, S. Hatakeyama, K. Okuyama:
A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer. 664-667 - Mehmet Soyuer, James D. Warnock:
Multigigahertz voltage-controlled oscillators in advanced silicon bipolar technology. 668-670 - Manabu Ishibe, Shoji Otaka, Junichi Takeda, Shigeru Tanaka, Yoshiaki Toyoshima, Satoru Takatsuka, Shoichi Shimizu:
High-speed CMOS I/O buffer circuits. 671-673 - Koichiro Ishibashi, Katsuro Sasaki, Toshiaki Yamanaka, Hiroshi Toyoshima, Fumio Kojima:
A 1.7-V adjustable I/O interface for low-voltage fast SRAMs. 674-677 - Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong:
A pulsed sensing scheme with a limited bit-line swing. 678-682 - Hideo Kato, Katsuhiko Sato, Masataka Matsui, H. Shibata, K. Hashimoto, Takayuki Ootani, Kiyofumi Ochii:
Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs. 683-685
Volume 27, Number 5, May 1992
- Lloyd Watts, Douglas A. Kerns, Richard F. Lyon, Carver A. Mead:
Improved implementation of the silicon cochlea. 692-700 - Bernabé Linares-Barranco, Edgar Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José L. Huertas:
A modular T-mode design approach for analog neural network hardware implementations. 701-713 - Marc H. Cohen, Andreas G. Andreou:
Current-mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network. 714-727 - Fabrizio Lombardi, Jon C. Muzio:
Concurrent error detection and fault location in an FFT architecture. 728-736 - Yong-Chul Shin, Ramalingam Sridhar, Victor Demjanenko, Paul W. Palumbo, Sargur N. Srihari:
A special-purpose content addressable memory chip for real-time image processing. 737-744 - Derek C. Wong, Giovanni De Micheli, Michael J. Flynn, Robert E. Huston:
A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency. 745-753 - Torkel Arnborg:
Performance predictions of scaled BiCMOS gates using physical simulation. 754-760 - Hosahalli R. Srinivas, Keshab K. Parhi:
A fast VLSI adder architecture. 761-767 - Timothy M. Gould, Jay H. Harris:
Single-chip design of bit-error-correcting stack decoders. 768-775 - Akinori Sekiyama, Teruo Seki, Shinji Nagai, Akihiro Iwase, Noriyuki Suzuki, Masato Hayasaka:
A 1-V operating 256-kb full-CMOS SRAM. 776-782 - Hussein I. Hanafi, Robert H. Dennard, Chih-Liang Chen, Russell J. Weiss, David S. Zicherman:
Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance. 783-791 - Muhammad E. S. Elrabaa, Mohamed I. Elmasry:
Design and optimization of buffer chains and logic circuits in a BiCMOS environment. 792-801 - Douglas J. Fouts:
A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems. 802-809 - Nhat M. Nguyen, Robert G. Meyer:
Start-up and frequency stability in high-frequency oscillators. 810-820 - Steven J. Daubert, David Vallancourt:
A transistor-only current-mode Sigma Delta modulator. 821-830 - Igor M. Filanovsky, Henry Baltes:
CMOS two-quadrant multiplier using transistor triode regime. 831-833 - Samir S. Rofail, Mohamed I. Elmasry:
Analytical and numerical analyses of the delay time of BiCMOS structures. 834-839 - Nan Zhuang, Haomin Wu:
A new design of the CMOS full adder. 840-844
Volume 27, Number 6, June 1992
- Lothar Schmidt, Hans-Martin Rein:
Continuously variable gigahertz phase-shifter IC covering more than one frequency decade. 854-862 - Tzu-Wang Pan, Asad A. Abidi:
A wide-band CMOS read amplifier for magnetic data storage systems. 863-873 - John E. LeMoncheck:
An analog VLSI model of the jamming avoidance response in electric fish. 874-882 - Masato Motomura, Hachiro Yamada, Tadayoshi Enomoto:
A 2 K-word dictionary search processor (DISP) LSI with an approximate word search capability. 883-891 - Sateh M. S. Jalaleddine, Louis G. Johnson:
Associative IC memories with relational search and nearest-match capabilities. 892-900 - Bernard K. Gunther:
An integrated pre-access architecture for CMOS SRAM. 901-907 - Drew E. Wingard, Don C. Stark, Mark A. Horowitz:
Circuit techniques for large CSEA SRAMs. 908-919 - Koichiro Ishibashi, Katsuro Sasaki, Hiroshi Toyoshima:
A voltage down converter with submicroampere standby current for low-power static RAMs. 920-926 - Satoshi Sakurai, Mohamnmed Ismail, Jean-Yves Michel, Edgar Sanchez-Sinencio, Robert Brannen:
A MOSFET-C variable equalizer circuit with simple on-chip automatic tuning. 927-934 - Ramon A. Gomez, Asad A. Abidi:
A 50-MHz CMOS variable gain amplifier for magnetic data storage systems. 935-939 - Olli Vainio, Mani Sundaram, Stephen I. Long, Yrjö Neuvo:
A 600-MHz median-type digital filter on GaAs. 940-943 - Aly Ezzat Salama, Mohamed I. Elmasry:
Fault characterization, testing considerations, and design for testability of BiCMOS logic circuits. 944-947 - Keith A. Jenkins, Robert L. Franch:
Measurement of VLSI power supply current by electron-beam probing. 948-950 - P. V. Ananda Mohan:
Comments on 'New monolithic switched-capacitor differentiators with good noise rejection'. 951
Volume 27, Number 7, July 1992
- Bernard Ginetti, Paul G. A. Jespers, Andre M. Vandemeulebroecke:
A CMOS 13-b cyclic RSD A/D converter. 957-964 - Marco M. Monti, Domenico Rossi, Mauro Belloli:
Low-noise tape preamplifier with new self-biasing architecture. 966-973 - Jörg Hauptmann, Franz Dielacher, Reinhard Steiner, Christian C. Enz, François Krummenacher:
A low-noise amplifier with automatic gain control and anticlipping control in CMOS technology. 974-981 - Michael P. Flynn, Sverre U. Lidholm:
A 1.2- mu m CMOS current-controlled oscillator. 982-987 - Pieter Vorenkamp, Johan P. M. Verdaasdonk:
Fully bipolar, 120-Msample/s 10-b track-and-hold circuit. 988-992 - Jose Silva-Martinez, Michel S. J. Steyaert, Willy Sansen:
Design techniques for high-performance full-CMOS OTA-RC continuous-time filters. 993-1001 - Georgios K. Konstadinidis, Horst H. Berger:
Optimization of buffer stages in bipolar VLSI systems. 1002-1013 - Takayasu Sakurai:
A unified theory for mixed CMOS/BiCMOS buffer optimization. 1014-1019 - Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima:
A 34-ns 16-Mb DRAM with controllable voltage down-converter. 1020-1027 - Heribert Geib, Werner Weber, Erdi Wohlrab, Lothar Risch:
Experimental investigation of the minimum signal for reliable operation of DRAM sense amplifiers. 1028-1035 - Rudiger Hofmann, Rudi Muller:
A multifunctional high-speed switch element for ATM applications. 1036-1040 - Harry T. Weston, Mihai Banu, San-Chin Fang, Philip W. Diodato, Thomas D. Stanik, Paul A. Wilford, Frank M. Hsu:
A submicrometer NMOS multiplexer-demultiplexer chip set for 622.08-Mb/s SONET applications. 1041-1049 - Andreas Laudenbach, Manfred Glesner:
VLSI system design for automotive control. 1050-1056 - Dirk Weinsziehr, Harald Ebert, Gisela Mahlich, Joachim Preißner, Hans Sahm, Johannes Schuck, Harald Bauer, Karl Hellwig, Dietmar Lorenz:
KISS-16V2: a one-chip ASIC DSP solution for GSM. 1057-1066 - Gerhard Roos, Bernd Hoefflinger:
Complex 3D CMOS circuits based on a triple-decker cell. 1067-1072 - Stanley E. Schuster, Terry I. Chappell, Barbara A. Chappell, Robert L. Franch:
On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM. 1073-1079 - Hiroshige Fujii, Chikahiro Hori, Tomoji Takada, Naoyuki Hatanaka, Tatsuhiko Demura, Goichi Ootomo:
A floating-point cell library and a 100-Mflops image signal processor. 1080-1088 - F. Mistlberger, Rudolf Koch:
Class-AB high-swing CMOS power amplifier. 1089-1092 - Luca Selmi, D. B. Estreich, Bruno Riccò:
Small-signal MMIC amplifiers with bridged T-coil matching networks. 1093-1096 - Chris J. M. Verhoeven:
A high-frequency electronically tunable quadrature oscillator. 1097-1100 - Jürgen Fichtel, Bedrich J. Hosticka, Werner Schardein:
Design and applications of tunable analog BiCMOS circuits. 1101-1104 - Eleonora Franchi, Marco Tartagni, Roberto Guerrieri, Giorgio Baccarani:
Random access analog memory for early vision. 1105-1109 - Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez, José Luis Huertas, Edgar Sánchez-Sinencio:
Analog neural programmable optimizers in CMOS VLSI technologies. 1110-1115 - Alain Chemarin, Alain André, Alain Botta, Jacques Majos, Jean-Luc Rainard, Henri Teyssier, Pierre Thorel:
A high-speed CMOS circuit for 1.2-Gb/s 16*16 ATM switching. 1116-1120 - Dirk Reuver, Heinrich Klar:
A configurable convolution chip with programmable coefficients. 1121-1123
Volume 27, Number 8, August 1992
- Kazumasa Kioi, Toshiyuki Shinozaki, Shinji Toyoyama, Kazuhiko Shirakawa, Koui Ohtake, Shuhei Tsuchimoto:
Design and implementation of a 3D-LSI image sensing processor. 1130-1140 - Yong S. Lee:
A secondary cache controller design for a high-end microprocessor. 1141-1146 - Tomohisa Wada, Suresh Rajan, Steven A. Przybylski:
An analytical access time model for on-chip cache memories. 1147-1156 - Sailesh R. Maskai, Sayfe Kiaei, David J. Allstot:
Synthesis techniques for CMOS folded source-coupled logic circuits. 1157-1167 - James H. Atherton, H. Thomas Simmonds:
An offset reduction technique for use with CMOS integrated comparators and amplifiers. 1168-1175 - Thaddeus J. Gabara, Scott C. Knauer:
Digitally adjustable resistors in CMOS for high-performance applications. 1176-1185 - Rupert Howes, William Redman-White:
A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET's. 1186-1193 - Michiel Steyaert, Raf Roovers:
A 1-GHz single-chip quadrature modulator. 1194-1197 - Z. X. Yan, M. Jamal Deen:
A new resonant-tunnel diode-based multivalued memory circuit using a MESFET depletion load. 1198-1202 - Manjit S. Cheema, Parag K. Lala:
Totally self-checking CMOS circuit design for breaks and stuck-on faults. 1203-1206 - Ching-Te Chuang, Ken Chin, Hyun J. Shin, Pong-Fei Lu:
High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage. 1207-1210 - Gerard M. Blair:
PLA design for single-clock CMOS. 1211-1213 - Robert L. Franch, Sang H. Dhong, Roy E. Scheuerlein:
A large V/sub DS/ data retention test pattern for DRAM's. 1214-1217
Volume 27, Number 9, September 1992
- Toshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa:
A 14-ns 14-Mb CMOS DRAM with 300-mW active power. 1222-1228 - Gensuke Goto, Tomio Sato, Masao Nakajima, Takao Sukemura:
A 54*54-b regularly structured tree multiplier. 1229-1236 - Bong-Hee Park, Premachandran R. Menon:
Stuck-open testable scan-based CMOS sequential circuits. 1237-1244 - Andrew T. Yang, Yu-Hsu Chang:
Physical timing modeling for bipolar VLSI. 1245-1254 - Rinaldo Castello, Ferdinando Lari, Marco Siligoni, Luciano Tomasini:
100-V high-performance amplifiers in BCD technology for SLIC applications. 1255-1263 - Katsuyoshi Washio, Takeaki Okabe, Katsuhiro Norisue, Toshio Nagashima:
An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Si bipolar technology. 1264-1269 - Anna M. Durham, William Redman-White, John B. Hughes:
High-linearity continuous-time filter in 5-V VLSI CMOS. 1270-1276 - Zhenhua Wang:
Automatic V/sub T/ extractors based on an n*n/sup 2/ MOS transistor array and their application. 1277-1285 - Heribert Geib, Wolfgang Raab, Doris Schmitt-Landsiedel:
Block-decoded sense-amplifier driver for high-speed sensing in DRAM's. 1286-1288 - Bart A. De Cock, Danny Maurissens, Jan Cornelis:
A CMOS pulse-width modulator/pulse-amplitude modulator for four-quadrant analog multipliers. 1289-1293 - Li Ping, R. C. J. Taylor, Robert K. Henderson, John I. Sewell:
Design of a switched-capacitor filter for a mobile telephone receiver. 1294-1298 - Bang W. Lee, Bing J. Sheu:
General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons. 1299-1302 - Hwang-Cherng Chow, Wu-Shiung Feng:
An analytical CMOS inverter delay model including channel-length modulations. 1303-1306
Volume 27, Number 10, October 1992
- Richard Hagelauer, Frank Oehler, Günter Rohmer, Josef Sauerer, Dieter Seitzer:
A gigasample/second 5-b ADC with on-chip track and hold based on an industrial 1 mu m GaAs MESFET E/D process. 1313-1320 - G. Van Andrews, Christopher T. M. Chang, John D. Cayo, Steven Sabin, William A. White, Michael P. Harris:
A monolithic digital chirp synthesizer chip with I and Q channels. 1321-1326 - John F. Naber, Hausila P. Singh, William J. Tanis, Andrew J. Koshar, Gregory L. Segalla:
A fast-settling GaAs-enhanced frequency synthesizer. 1327-1331 - Klaus Runge, Detlef Daniel, R. D. Standley, James L. Gimlett, Randall B. Nubling, Richard L. Pierson, Steve M. Beccue, Keh-Chung Wang, Neng-Huang Sheng, Mau-Chung Frank Chang, Dong Ming Chen, Peter M. Asbeck:
AlGaAs/GaAs HBT IC's for high-speed lightwave transmission systems. 1332-1341 - Yasuyuki Suzuki, Tetsuyuki Suzaki, Yumi Ogawa, Sadao Fujita, Wendy Liu, Akihiko Okamoto:
Pseudomorphic 2DEG FET IC's for 10 Gb/s optical communication systems with external optical modulation. 1342-1346 - Peter Wennekers, Ulrich Novotny, Axel Hülsmann, Gudrun Kaufel, Klaus Köhler, Brian Raynor, Joachim Schneider:
10 GB/s bit-synchronizer circuit with automatic timing alignment by clock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs. 1347-1352 - Hans Rohdin, Joseph Straznicky, Hans Jekat, Avelina Nagy, Alice Fischer-Colbrie, Dan E. Mars, Rolf Jaeger:
A 23. 1353-1358 - Koutarou Tanaka, Makoto Shikata, Tamotsu Kimura, Yoshiaki Sano, Masahiro Akiyama:
8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFL circuit. 1359-1363 - Kevin R. Nary, Stephen I. Long:
GaAs two-phase dynamic FET logic: a low-power logic family for VLSI. 1364-1371 - Keh-Chung Wang, Steve M. Beccue, Mau-Chung Frank Chang, Randall B. Nubling, Arthur M. Cappon, Tom C.-T. Tsen, Dong Ming Chen, Peter M. Asbeck, Chung Y. Kwok:
Diode-HBT-logic circuits monolithically integrable with ECl/CML circuits. 1372-1378 - Ken Poulton, Knud L. Knudsen, John J. Corcoran, Keh-Chung Wang, Richard L. Pierson, Randall B. Nubling, Mau-Chung Frank Chang:
Thermal design and simulation of bipolar integrated circuits. 1379-1387 - Jyoti P. Mondal, John J. Geddes, Robert C. Becker, Athanase Contolatis, Mark Vickberg, Douglas Carlson, Sommy S. Bounnak, Carol Anderson, Vladimir Sokolov:
MESFET MMIC Ka-band transmitter performance for high-volume system applications. 1388-1396 - Huei Wang, Daniel C. Yang, Michael V. Aust, Edward A. Rezek, Barry R. Allen, Louis A. Fletcher, Robert C. Becker:
A monolithic Ka-band 0.25 mu m GaAs MESFET transmitter for high volume production. 1397-1404 - Aryeh Platzker, Keith T. Hetzler, J. Bradford Cole:
Development of highly dense four-stage flat-gain 1-W 6-18-GHz MMIC power amplifier chip. 1405-1412 - Nobuo Shiga, Takeshi Sekiguchi, Shigeru Nakajima, Kenji Otobe, Nobuhiro Kuwata, Ken-ichiro Matsuzaki, Hideki Hayashi:
MMIC family for DBS down-converter with pulse-doped GaAs MESFETs. 1413-1420 - Makoto Nakamura, Yuhki Imai, Eiichi Sano, Yoshiki Yamauchi, Osaake Nakajima:
A limiting amplifier with low phase deviation using an AlGaAs/GaAs HBT. 1421-1427 - Motomu Takatsu, Kenichi Imamura, Hiroaki Ohnishi, Toshihiko Mori, Takami Adachihara, Shunichi Muto, Naoki Yokoyama:
Logic circuits using resonant-tunneling hot-electron transistors (RHETs). 1428-1430 - Chiaki Takano, Kiyoshi Tanaka, Akihiko Okubora, Jiro Kasahara:
Monolithic integration of 5-Gb/s optical receiver block for short distance communication. 1431-1433 - Cindy Yuen, Yi-Ching Pao, N. G. Bechtel:
5-60-GHz high-gain distributed amplifier utilizing InP cascode HEMTs. 1434-1438 - Nan-Lei Wang, Wu-Jing Ho:
X-band HBT VCO with high-efficiency CB buffer amplifier. 1439-1443 - Yoshiki Yamauchi, Hideki Kamitsuna, Masashi Nakatsugawa, Hiroshi Ito, Masahiro Muraguchi, Kazuo Osafune:
A 15-GHz monolithic low-phase-noise VCO using AlGaAs/GaAs HBT technology. 1444-1447 - Toshihiko Yoshimasu, Keiichi Sakuno, Nobuyuki Matsumoto, Eiji Suematsu, Toshiya Tsukao, Takashi Tomita:
A low-current Ku-band GaAs monolithic image rejection down-converter. 1448-1451 - K. M. Simon, Manfred J. Schindler, V. A. Mieczkowski, P. F. Newman, M. E. Goldfarb, Elias Reese, B. A. Small:
A production ready, 6-18-GHz, 5-b phase shifter with integrated CMOS compatible digital interface circuitry. 1452-1456 - Brian Khabbaz, Anthony Pospishil, H. P. Singh:
DC-to-20-GHz MMIC multibit digital attenuators with on-chip TTL control. 1457-1462 - Thomas Apel, S. Ludvik:
A compact, high-gain, 2-20-GHz MMIC amplifier. 1463-1469 - Alexandre Ternes Behr, Márcio Cherem Schneider, Sidnei Noceti Filho, Carlos Galup-Montoro:
Harmonic distortion caused by capacitors implemented with MOSFET gates. 1470-1475 - Allan Armstrong, Hans-Jurgen Wagner:
A 5-V/sub p-p/ 100-ps GaAs pulse amplifier IC with improved pulse fidelity. 1476-1481
Volume 27, Number 11, November 1992
- Hiroyuki Goto, Hiroaki Ohkubo, Kenji Kondou, Masayoshi Ohkawa, Hitoshi Mitani, Shinichi Horiba, Masakazu Soeda, Fumihiko Hayashi, Yutaro Hachiya, Toshiyuki Shimizu, Manabu Ando, Zensuke Matsuda:
A 3.3-V 12-ns 16-Mb CMOS SRAM. 1490-1496 - Masato Matsumiya, Shoichiro Kawashima, Makoto Sakata, Masahiko Ookura, Toru Miyabo, Tom Koga, Kazuo Itabashi, Kazuhiro Mizutani, Hiroshi Shimada, Noriyuki Suzuki:
A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture. 1497-1503 - Kazuyuki Nakamura, Takashi Oguri, Takao Atsumo, Masahide Takada, Atsushi Ikemoto, Hisamitsu Suzuki, Tadashi Nishigori, Tohru Yamazaki:
A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM. 1504-1510 - Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu:
A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier. 1511-1518 - Koichiro Ishibashi, Koichi Takasugi, Toshiaki Yamanaka, Takashi Hashimoto, Katsuro Sasaki:
A 1-V TFT-load SRAM using a two-step word-voltage method. 1519-1524 - Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda:
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. 1525-1533 - Katsumi Dosaka, Yasuhiro Konishi, Kouji Hayano, Katsumitsu Himukashi, Akira Yamazaki, Hisashi Iwamoto, Masaki Kumanoya, Hisanori Hamano, Tsutomu Yoshihara:
A 100-MHz 4-Mb cache DRAM with fast copy-back scheme. 1534-1539 - Akira Umezawa, Shigeru Atsumi, Masao Kuriyama, Hironori Banba, Ken-ichi Imamiya, Kiyomi Naruke, Seiji Yamada, Etsushi Obi, Masamitsu Oshikiri, Tomoko Suzuki, Sumio Tanaka:
A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure. 1540-1546 - Toshikatsu Jinbo, Hidetoshi Nakata, Kiyokazu Hashimoto, Takeshi Watanabe, Kazuhisa Ninomiya, Takahiko Urai, Mikio Koike, Tatsuo Sato, Noriaki Kodama, Ken-ichi Oyama, Takeshi Okazawa:
A 5-V-only 16-Mb flash memory with sector erase mode. 1547-1554 - Daniel W. Dobberpuhl, Richard T. Witek, Randy L. Allmon, Robert Anglin, David Bertucci, Sharon M. Britton, Linda Chao, Robert A. Conrad, Daniel E. Dever, Bruce Gieseke, Soha Hassoun, Gregory W. Hoeppner, Kathryn Kuchler, Maureen Ladd, Burton M. Leary, Liam Madden, Edward J. McLellan, Derrick Meyer, James Montanaro, Donald A. Priore, Vidya Rajagopalan, Sridhar Samudrala, Sribalan Santhanam:
A 200-MHz 64-b dual-issue CMOS microprocessor. 1555-1567 - Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki:
A 1.5-V full-swing BiCMOS logic circuit. 1568-1574 - Masaya Tamamura, Shinichi Shiotsu, Masayasu Hojo, Katsunobu Nomura, Shinji Emori, Hiromichi Ichikawa, Takao Akai:
A 9.5-Gb/s Si-bipolar ECL array. 1575-1578 - Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba:
0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file. 1579-1584 - Roy W. Badeau, R. Iris Bahar, Debra Bemstein, Larry L. Biro, William J. Bowhill, John F. Brown III, Michael A. Case, Ruben W. Castelino, Elizabeth M. Cooper, Maureen A. Delaney, David R. Deverell, John H. Edmondson, John J. Ellis, Timothy C. Fischer, Thomas F. Fox, Mary K. Gowan, Paul E. Gronowski, William V. Herrick, Ani1 K. Jain, Jeanne E. Meyer, Daniel G. Miner, Hamid Partovi, Victor Peng, Ronald P. Preston, Chandrasekhara Somanathan, Rebecca L. Stamm, Stephen C. Thierauf, G. Michael Uhler, Nicholas D. Wade, William R. Wheeler:
A 100-MHz macropipelined VAX microprocessor. 1585-1598 - Ian A. Young, Jeffrey K. Greason, Keng L. Wong:
A PLL clock generator with 5 to 110 MHz of lock range for microprocessors. 1599-1607 - Katsuyuki Sato, Mitsuteru Kobayashi, Hiroyuki Hida, Hideyuki Miyazawa, Yuji Shirai, Kenji Fujita, Toshiyuki Nakao, Masamichi Ishihara:
A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array. 1608-1613 - Gert Groenewold:
A high-dynamic-range integrated continuous-time bandpass filter. 1614-1622 - Pinaki Mazumder:
An on-chip ECC circuit for correcting soft errors in DRAMs with trench capacitors. 1623-1633 - H. Jonathan Chao, Necdet Uzun:
A VLSI sequencer chip for ATM traffic shaper and queue manager. 1634-1643 - Manish Mittal, C. André T. Salama:
DPTL 4-b carry lookahead adder. 1644-1647 - Kenneth Chin, Ching-Te Chuang, James D. Warnock:
12.8-ps 1.0-mW charge-buffered active pull-down NTL circuit. 1648-1650
Volume 27, Number 12, December 1992
- Johan van Valburg, Rudy J. van de Plassche:
An 8-b 650-MHz folding ADC. 1662-1666 - Behzad Razavi, Bruce A. Wooley:
A 12-b 5-Msample/s two-step CMOS A/D converter. 1667-1678 - Seung-Hoon Lee, Bang-Sup Song:
Digital-domain calibration of multistep analog-to-digital converters. 1679-1688 - Donald A. Kerth, Douglas S. Piasecki:
An oversampling converter for strain gauge transducers. 1689-1696 - Myles H. Wakayama, Hiroshi Tanimoto, Takahiro Tasai, Yoshihiro Yoshida:
A 1.2- mu m BiCMOS sample-and-hold circuit with a constant-impedance, slew-enhanced sampling gate. 1697-1708 - Ruud G. H. Eschauzier, Leo P. T. Kerklaan, Johan H. Huijsing:
A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure. 1709-1717 - Frank J. M. Thus:
A compact bipolar class-HB output stage using 1-V power supply. 1718-1722 - Haideh Khorramabadi, Joseph Anidjar, Thomas R. Peterson:
A highly efficient CMOS line driver with 80-dB linearity for ISDN U-interface applications. 1723-1729 - Klaas Bult, Govert J. G. M. Geelen:
An inherently linear and compact MOST-only current division technique. 1730-1735 - Thomas H. Lee, John F. Bulzacchelli:
A 155-MHz clock recovery delay- and phase-locked loop. 1736-1746 - Ansgar Pottbacker, Ulrich Langmann, Hans-Ulrich Schreiber:
A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s. 1747-1751 - Aaron W. Buchwald, Kenneth W. Martin, Aaron K. Oki, Kevin W. Kobayashi:
A 6-GHz integrated phase-locked loop using AlGaAs/GaAs heterojunction bipolar transistors. 1752-1762 - S. Khursheed Enam, Asad A. Abidi:
NMOS IC's for clock and data regeneration in gigabit-per-second optical-fiber receivers. 1763-1774 - Toshiyuki Okamura, Chiharu Kurioka, Yoshiaki Kuraishi, Orie Tsuzuki, Takashi Senba, Mizuyuki Ushirozawa, Mikio Fujimaru:
10-GHz Si bipolar amplifier and mixer ICs for coherent optical systems. 1775-1780 - Tetsuyuki Suzaki, Masaaki Soda, Takenori Morikawa, Hiroshi Tezuka, Chihiro Ogawa, Sadao Fujita, Hisashi Takemura, Tsutomu Tashiro:
Si bipolar chip set for 10-Gb/s optical receiver. 1781-1786 - Mehran Bagheri, Keh-Chung Wang, Mau-Chung Frank Chang, Randy B. Nubling, Peter M. Asbeck, Andy Chen:
11.6-GHz 1:4 regenerating demultiplexer with bit-rotation control and 6.1-GHz auto-latching phase-aligner ICs using AlGaAs/GaAs HBT technology. 1787-1793 - Moriaki Mizuno, Hirokazu Suzuki, Masami Ogawa, Kouji Sato, Hiromichi Ichikawa:
A 3-mW 1.0-GHz silicon-ECL dual-modulus prescaler IC. 1794-1798 - Masakazu Kurisu, Gohiko Uemura, Masahiro Ohuchi, Chihiro Ogawa, Hisashi Takemura, Takenori Morikawa, Tsutomu Tashiro:
A Si bipolar 28-GHz dynamic frequency divider. 1799-1804 - Richard C. Walker, Cheryl L. Stout, Jieh-Tsorng Wu, Benny Lai, Chu-Sun Yen, Thomas Hornak, Patrick T. Petruno:
A two-chip 1.5-GBd serial link interface. 1805-1811 - Hyun J. Shin, Michael Immediato:
An experimental 5-Gb/s 16*16 Si-bipolar crosspoint switch. 1812-1818 - Steven J. Tanghe, Kensall D. Wise:
A 16-channel CMOS neural stimulating array. 1819-1825 - Kenneth W. Fernald, John J. Paulos, Blaine A. Stackhouse, Robert A. Heaton:
A self-tuning digital telemetry IC for use in a microprocessor-based implantable instrument. 1826-1832 - Alan G. Lewis, David D. Lee, Richard H. Bruce:
Polysilicon TFT circuit design and performance. 1833-1842 - Jose Silva-Martinez, Michel S. J. Steyaert, Willy Sansen:
A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning. 1843-1853 - Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara:
A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses. 1854-1861 - Kuniharu Uchimura, Osamu Saito, Yoshihito Amemiya:
A high-speed digital neural network chip with low-power chain-reaction architecture. 1862-1867 - Takeshi Shima, Tomohisa Kimura, Yukio Kamatani, Tetsuro Itakura, Yasuhiko Fujita, Tetsuya Iida:
Neuro chips with on-chip back-propagation and/or Hebbian learning. 1868-1876 - Peter J. Black, Teresa H. Meng:
A 140-Mb/s, 32-state, radix-4 Viterbi decoder. 1877-1885 - Kunitoshi Aono, Masaki Toyokura, Toshiyuki Araki, Akihiko Ohtani, Hisashi Kodama, Kiyoshi Okamoto:
A video digital signal processor with a vector-pipeline architecture. 1886-1894 - Dev C. Chen, Jan M. Rabaey:
A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths. 1895-1904 - Roberto Alini, Andrea Baschirotto, Rinaldo Castello:
Tunable BiCMOS continuous-time filter for high-frequency applications. 1905-1915 - Behzad Razavi, Bruce A. Wooley:
Design techniques for high-speed, high-resolution comparators. 1916-1926 - Tadato Yamagata, Masaaki Mihara, Takeshi Hamamoto, Yasumitsu Murai, Toshifumi Kobayashi, Michihiro Yamada, Hideyuki Ozaki:
A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure. 1927-1933 - Mel Bazes, Roni Ashuri:
A novel CMOS digital clock and data decoder. 1934-1940
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