"A high-speed digital neural network chip with low-power chain-reaction ..."

Kuniharu Uchimura, Osamu Saito, Yoshihito Amemiya (1992)

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DOI: 10.1109/4.173116

access: closed

type: Journal Article

metadata version: 2025-02-03

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Kuniharu Uchimura, Osamu Saito, Yoshihito Amemiya:
A high-speed digital neural network chip with low-power chain-reaction architecture. IEEE J. Solid State Circuits 27(12): 1862-1867 (1992)

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