"A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture."

Masato Matsumiya et al. (1992)

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DOI: 10.1109/4.165328

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type: Journal Article

metadata version: 2025-02-03

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Masato Matsumiya, Shoichiro Kawashima, Makoto Sakata, Masahiko Ookura, Toru Miyabo, Tom Koga, Kazuo Itabashi, Kazuhiro Mizutani, Hiroshi Shimada, Noriyuki Suzuki:
A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture. IEEE J. Solid State Circuits 27(11): 1497-1503 (1992)

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