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ORCIDDavid M. Lewis
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2010 – 2019
- 2019
[j14]David M. Lewis
, Herman Schmit:
Spatial Timing Analysis With Exact Propagation of Delay and Application to FPGA Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2153-2166 (2019)- 2017
- [c33]David Greenhill, Ron Ho, David M. Lewis, Herman Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, Dana How, Peter McElheny, Keith Duwel, Jeffrey Schulz, Darren Faulkner, Gopal Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay:
3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration. ISSCC 2017: 54-55 - 2016
- [c32]Carl Ebeling, Dana How, David M. Lewis, Herman Schmit:
Stratix™ 10 High Performance Routable Clock Networks. FPGA 2016: 64-73 - [c31]David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken:
The Stratix™ 10 Highly Pipelined FPGA Architecture. FPGA 2016: 159-168 - 2015
- [c30]Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang:
Arria™ 10 device architecture. CICC 2015: 1-8 - 2013
- [c29]David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu:
Architectural enhancements in Stratix V™. FPGA 2013: 147-156 - 2011
- [j13]David M. Lewis, Vandana Pursnani Janeja:
An Empirical Evaluation of Similarity Coefficients for Binary Valued Data. Int. J. Data Warehous. Min. 7(2): 44-66 (2011) - 2010
- [c28]Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz:
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. FPGA 2010: 167-176
2000 – 2009
- 2009
- [c27]David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan:
Architectural enhancements in Stratix-IIITM and Stratix-IVTM. FPGA 2009: 33-42 - 2005
- [c26]David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose:
The Stratix II logic and routing architecture. FPGA 2005: 14-20 - 2004
- [c25]Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis:
MAX II: A low-cost, high-performance LUT-based CPLD. CICC 2004: 443-446 - [c24]Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini:
Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144 - 2003
- [c23]Paul Leventis, Mark Chan, Michael Chan, David M. Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello:
Cyclone ™: a low-cost, high-performance FPGA. CICC 2003: 49-52 - [c22]Andy Gean Ye, Jonathan Rose, David M. Lewis:
Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. CICC 2003: 61-64 - [c21]David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose:
The StratixTM routing and logic architecture. FPGA 2003: 12-20 - 2002
- [c20]Guy G. Lemieux, David M. Lewis:
Circuit design of routing switches. FPGA 2002: 19-28 - [c19]Guy G. Lemieux, David M. Lewis:
Analytical Framework for Switch Block Design. FPL 2002: 122-131 - [c18]Andy Gean Ye, Jonathan Rose, David M. Lewis:
Synthesizing datapath circuits for FPGAs with emphasis on area minimization. FPT 2002: 219-226 - 2001
- [c17]Guy G. Lemieux, David M. Lewis:
Using sparse crossbars within LUT. FPGA 2001: 59-68 - 2000
- [c16]L. Louis Zhang, Qiang Wang, David M. Lewis:
Design of a VLIW Compute Accelerator on the Transmogrifier-2. FCCM 2000: 3-12 - [c15]Guy G. Lemieux, Paul Leventis, David M. Lewis:
Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164
1990 – 1999
- 1999
- [c14]Andy Gean Ye, David M. Lewis:
Procedural Texture Mapping on FPGAs. FPGA 1999: 112-120 - 1998
- [j12]David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow:
The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 188-198 (1998) - 1997
- [c13]Qiang Wang, David M. Lewis:
Automated field-programmable compute accelerator design using partial evaluation. FCCM 1997: 145-154 - [c12]David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow:
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA 1997: 53-61 - 1996
- [j11]Don Cherepacha, David M. Lewis:
DP-FPGA: An FPGA Architecture Optimized for Datapaths. VLSI Design 4(4): 329-343 (1996) - [c11]Vi Cuong Chan, David M. Lewis:
Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. FPGA 1996: 51-57 - 1995
- [j10]David M. Lewis:
114 MFLOPS logarithmic number system arithmetic unit for DSP applications. IEEE J. Solid State Circuits 30(12): 1547-1553 (1995) - 1994
- [j9]David M. Lewis:
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit. IEEE Trans. Computers 43(8): 974-982 (1994) - [c10]Aditya A. Aggarwal, David M. Lewis:
Routing Architectures for Hierarchical Field Programmable Gate Arrays. ICCD 1994: 475-478 - 1993
- [j8]Ahmet N. Parlakbilek, David M. Lewis:
A multiple-strength multiple-delay compiled-code logic simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1937-1946 (1993) - [c9]David M. Lewis:
An accurate LNS arithmetic unit using interleaved memory function interpolator. IEEE Symposium on Computer Arithmetic 1993: 2-9 - [c8]David M. Lewis, Marcus van Ierssel, Daniel H. Wong:
A Field Programmable Accelerator for Compiled-Code Applications. ICCD 1993: 491-496 - [c7]David A. Johns, David M. Lewis, Don Cherepacha:
Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering. ISCAS 1993: 1302-1305 - 1992
- [j7]David M. Lewis:
A compiled-code hardware accelerator for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 555-565 (1992) - 1991
- [j6]Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White:
Hector: A Hierarchically Structured Shared-memory Multiprocessor. Computer 24(1): 72-79 (1991) - [j5]David M. Lewis:
A hierarchical compiled code event-driven logic simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(6): 726-737 (1991) - 1990
- [j4]David M. Lewis:
An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System. IEEE Trans. Computers 39(11): 1325-1336 (1990) - [j3]David M. Lewis:
Device model approximation using 2N trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1): 30-38 (1990) - [c6]Brian W. Thomson, E. Stewart Lee, Peter I. P. Boulton, Michael Stumm, David M. Lewis:
Using Deducibility in Secure Network Modelling. ESORICS 1990: 117-123
1980 – 1989
- 1989
- [c5]David M. Lewis, Lawrence K. Yu:
Algorithm design for a 30-bit integrated logarithmic processor. IEEE Symposium on Computer Arithmetic 1989: 192-199 - [c4]David M. Lewis:
Hierarchical compiled event-driven logic simulation. ICCAD 1989: 498-501 - 1988
- [j2]David M. Lewis, Brian W. Thomson, Peter I. P. Boulton, E. Stewart Lee:
Transforming bit-serial communication circuits into fast parallel VLSI implementations. IEEE J. Solid State Circuits 23(2): 549-557 (1988) - [j1]David M. Lewis:
Hardware accelerators for timing simulation of VLSI digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(11): 1134-1149 (1988) - [c3]David M. Lewis:
A Programmable Hardware Accelerator for Compiled Electrical Simulation. DAC 1988: 172-177 - 1986
- [c2]David M. Lewis, David R. Galloway, Robert J. Francis, Brian W. Thomson:
Swamp: A Fast Processor for Smalltalk-80. OOPSLA 1986: 131-139 - 1985
- [c1]David M. Lewis:
A hardware engine for analogue mode simulation of MOS digital circuits. DAC 1985: 345-351
Coauthor Index
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